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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 16-bit single-chip microcomputer 7700 family / 7700 series 7733 group 7735 group 7736 group users manual
keep safety first in your circuit designs ! l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
preface this manual describes the hardware of the mitsubishi cmos 16-bit microcomputers 7733/7735/7736 group. after reading this manual, the user will be able to understand the functions, so that the capabilities of the microcomputers can fully be utilized. for details concerning the software for the 7733/7735/ 7736 group, refer to the 7700 family software manual.
i before using this manual 1. introduction this manual consists of the following: part 1: 7733 group, part 2: 7735 group, and part 3: 7736 group. the peripheral functions are common to all of these groups, but the external bus mode differs according to the group, as follows: ? 7733 group: external bus mode a is assigned. ? 7735 group: external bus mode b is assigned. ? 7736 group: external bus mode a or b is selectable. in parts 2 and 3, only the differences occurring between the 7735/7736 group and the 7733 group are described. also, the chapter, section, table and figure numbers are the same as those in part 1 and the differences are described by the section. part 1: 7733 group l chapter 1. overview through chapter 17. applications the common functions of the 7733 group microcomputers are described. the m37733mhbxxxfp is used as a typical microcomputer in this group to describe all common functions. l chapter 18. low voltage version read this chapter when using the microcomputers with the electrical characteristics indicated by l. (see page 1-2 in part 1.) ex.: m37733mh lxxxhp the differences between the m37733mhlxxxhp, which is a typical low voltage version of the 7733 group, and the m37733mhbxxxfp are described. l chapter 19. built-in prom version read this chapter when using the microcomputers with the memory type indicated by e. (see page 1-2 in part 1.) ex.: m37733 ehbxxxfp the differences between the m37733ehbxxxfp, which is a typical built-in prom version of the 7733 group, and the m37733mhbxxxfp are described. l chapter 20. external rom version read this chapter when using the microcomputers with the memory type indicated by s. (see page 1-2 in part 1.) ex.: m37733 s4bfp the differences between the m37733s4bfp, which is a typical external rom version of the 7733 group, and the m37733mhbxxxfp are described. l appendix practical information for using the 7733 group is described . part 2: 7735 group, part 3: 7736 group refer to the table on the next page.
ii before using this manual refer to part 1: 7733 group chapter 1. overview chapter 2. central processing unit (cpu) chapter 3. programmable i/o ports chapter 4. interrupts chapter 5. key input interrupts chapter 6. timer a chapter 7. timer b chapter 8. serial i/o chapter 9. a-d converter chapter 10. watchdog timer chapter 11. stop and wait modes chapter 12. connecting external devices chapter 13. reset chapter 14. clock generating circuit chapter 15. electrical characteristics chapter 16. standard characteristics chapter 17. applications chapter 18. low voltage version chapter 19. built-in prom version chapter 20. external rom version appendix part 2 (note 1) 7735 group refer to part 2: 7735 group refer to part 1: 7733 group refer to part 2: 7735 group note 1: in part 2 and 3, when there is no reference provided about the part, refer to the corresponding chapter/section in that part. 2: when referring to the chapters and sections listed below, use the following guide: external bus mode a: refer to part 1, external bus mode b: refer to part 2. ?chapter 11. stop and wait modes ?chapter 12. connecting external devices ?chapter 15. electrical characteristics?(electrical characteristics related to the external bus mode) ?paragraph 17.1 memory expansion ?chapter 18. low voltage version (electrical characteristics related to the external bus mode) ?paragraph 18.6 applications part 1 7733 group refer to part 1: 7733 group refer to part 2: 7735 group part 3 (note 1) 7736 group refer to part 1: 7733 group refer to part 3: 7736 group (note 2) refer to part 3: 7736 group refer to part 3: 7736 group 2. notes l for product expansion information, refer to the latest catalog and data book, or contact the appropriate office, as listed in contact addresses for further information on the last page. l always refer to the latest data book for electrical characteristics. l this manual does not include the forms listed below. when necessary, copy the corresponding page of the latest data book, or contact the appropriate office, as listed in contact addresses for further information: ? mask rom order confirmation form ? prom order confirmation form ? mark specification form l for details concerning development support tools, refer to the latest data book of development support tools. l for details concerning software, refer to the 7700 family software manual.
iii before using this manual 3. register structure below is the structure diagram for all registers. 0 1 0 xxx register (address xx 16 ) b1 b0 b2 b3 b4 b5 b6 b7 0 ] 1 ] 2 ] 3 2 3 ... select bit 0 : ... 1 : ... ... select bit 0 : ... 1 : ... the value is 0 at reading. 0 : ... 1 : ... fix this bit to 0. 4 7 to 5 not implemented. 5 rw wo ro rw rw C 0 0 0 bit bit name this bit is ignored in ... mode. functions at reset rw ... flag undefined undefined ] 1 blank : set to 0 or 1 according to the usage. 0 : set to 0 at writing. 1 : set to 1 at writing. 5 : ignored depending on the mode or state. it may be 0 or 1. : not implemented. ] 2 0 : 0 immediately after reset. 1 : 1 immediately after reset. undefined : undefined immediately after reset. ] 3 rw : it is possible to read the bit state at readin g. the written value becomes valid. r o : it is possible to read the bit state at reading. t he written value becomes invalid. accordingly, the written value may be 0 or 1. w o : the written value becomes valid. it is impossible to read the bit state. the value is undefined at reading. however, when [0 at reading ] is indicated in the function or note column, the bit is always 0 at re ading.(see to ] 4 above.) : it is impossible to read the bit state. the value is undefined at reading. however, when [0 at reading] is indicated in the func tion or note column, the bit is always 0 at reading.(see to ] 4 above.) the written value becomes invalid. accordingly, the writ ten value may be 0 or 1. ] 4
7733 group user s manual i table of contents t able of contents part 1 7733 g roup chapter 1. overview 1.1 performance overview ............................................................ ............................................... 1 - 3 1.2 pin configuration ............................................................ ........................................................ 1 - 4 1.3 pin description ............................................................ ........................................................... 1 - 5 1.3.1 examples of handling unused pins ............................................................ .................. 1 - 8 1.4 block diagram ............................................................ ........................................................... 1-11 chapter 2. central processing unit (cpu) 2.1 central processing unit ............................................................ ............................................ 2 - 2 2.1.1 accumulator (acc) ............................................................ .............................................. 2 - 3 2.1.2 index register x (x) ............................................................ ............................................ 2 - 3 2.1.3 index register y (y) ............................................................ ............................................ 2 - 3 2.1.4 stack pointer (s) ............................................................ ................................................. 2 - 4 2.1.5 program counter (pc) ............................................................ ........................................ 2 - 5 2.1.6 program bank register (pg) ............................................................ .............................. 2 - 5 2.1.7 data bank register (dt) ............................................................ ..................................... 2 - 6 2.1.8 direct page register (dpr) ............................................................ ................................ 2 - 6 2.1.9 processor status register (ps) ............................................................ .......................... 2 - 8 2.2 bus interface unit ............................................................ .................................................... 2-10 2.2.1 overview ............................................................ ............................................................ 2-10 2.2.2 functions of bus interface unit (biu) ............................................................ ............ 2-12 2.2.3 operation of bus interface unit (biu) ............................................................ ............ 2-14 2.3 accessible area ............................................................ ........................................................ 2-16 2.3.1 banks ............................................................ ............................................................ ..... 2-17 2.3.2 direct page ............................................................ ........................................................ 2-17 2.4 memory allocation ............................................................ .................................................... 2-18 2.4.1 memory allocation in internal area ............................................................ ................. 2-18 2.5 processor modes ............................................................ ..................................................... 2-24 2.5.1 single-chip mode ............................................................ .............................................. 2-25 2.5.2 memory expansion and microprocessor modes ....................................................... 2-25 2.5.3 setting of processor modes ............................................................ ............................ 2-28 chapter 3. programmable i/o ports 3.1 programmable i/o ports ............................................................ ........................................... 3 - 2 3.1.1 port pi direction register ............................................................ .................................... 3 - 3 3.1.2 port pi register ............................................................ .................................................... 3 - 4 3.2 port peripheral circuits ............................................................ ............................................. 3 - 6 3.3 pull-up function ............................................................ .......................................................... 3 - 8 ___ ___ 3.3.1 pull-up function for ports p5 4 to p5 7 ( ki 0 to ki 3 ) ...................................................... 3 - 8 ____ ____ 3.3.2 pull-up function for ports p6 2 to p6 4 ( int 0 to int 2 ) ................................................. 3 - 8 3.4 internal peripheral devices i/o functions (ports p4 2 a n d p 5 t o p 8 ) ...................... 3-10
7733 group users manual table of contents ii chapter 4. interrupts 4.1 overview .................................................................................................................................. 4-2 4.2 interrupt sources .................................................................................................................... 4-4 4.3 interrupt control ..................................................................................................................... 4-6 4.3.1 interrupt disable flag (i) .................................................................................................4-8 4.3.2 interrupt request bit ........................................................................................................ 4-8 4.3.3 interrupt priority level selection bits and processor interrupt priority level (ipl) .. 4-8 4.4 interrupt priority level ......................................................................................................... 4-10 4.5 interrupt priority level detection circuit ......................................................................... 4-11 4.6 interrupt priority level detection time ............................................................................. 4-13 4.7 how interrupts are processed (from acceptance of interrupt request until execution of interrupt routine) ........................................................................................ 4-14 4.7.1 change in ipl at acceptance of interrupt request ................................................... 4-15 4.7.2 how to push registers .................................................................................................. 4-16 4.8 return from interrupt routine ............................................................................................ 4-17 4.9 multiple interrupts ................................................................................................................ 4-17 ____ 4.10 external interrupts ( inti interrupt) ................................................................................. 4-19 ____ 4.10.1 inti interrupt request bits function .......................................................................... 4-21 ____ 4.10.2 how to switch inti interrupt request occurrence condition ................................... 4-22 4.11 precautions for interrupts ................................................................................................ 4-23 chapter 5. key input interrupt function 5.1 overview .................................................................................................................................. 5-2 5.2 block description ................................................................................................................... 5-3 ___ ___ ____ 5.2.1 pins ki 0 to ki 3 and p6 4 / int 2 ................................................................................................................................ 5-3 5.2.2 port function control register ......................................................................................... 5-4 5.2.3 interrupt function ............................................................................................................. 5-6 5.3 initial setting example for related registers ....................................................................5-7 chapter 6. timer a 6.1 overview .................................................................................................................................. 6-2 6.2 block description ................................................................................................................... 6-3 6.2.1 counter and reload register (timer ai register) ........................................................ 6-4 6.2.2 count start flag ............................................................................................................... 6-5 6.2.3 timer ai mode register .................................................................................................. 6-6 6.2.4 timer ai interrupt control register ................................................................................ 6-7 6.2.5 port p5 and port p6 direction registers ...................................................................... 6-8 6.3 timer mode (bits 1 and 0 of timer ai mode register = 00 2 ) .................................. 6-9 6.3.1 setting for timer mode ................................................................................................. 6-11 6.3.2 count source ................................................................................................................. 6-13 6.3.3 operation in timer mode .............................................................................................. 6-14 6.3.4 selectable functions ..................................................................................................... 6-15 6.4 event counter mode (bits 1 and 0 of timer ai mode register = 01 2 ) ................. 6-19 6.4.1 setting for event counter mode .................................................................................. 6-23 6.4.2 operation in event counter mode ............................................................................... 6-25 6.4.3 selectable functions ..................................................................................................... 6-27
7733 group users manual iii table of contents 6.5 one-shot pulse mode (bits 1 and 0 of timer ai mode register = 10 2 ) ............... 6-32 6.5.1 setting for one-shot pulse mode ................................................................................ 6-34 6.5.2 count source ................................................................................................................. 6-36 6.5.3 trigger ............................................................................................................................ 6-37 6.5.4 operation in one-shot pulse mode ............................................................................. 6-38 6.6 pulse width modulation (pwm) mode (bits 1 and 0 of timer ai mode register = 11 2 ) .................. 6-41 6.6.1 setting for pwm mode ................................................................................................ 6-43 6.6.2 count source ................................................................................................................. 6-45 6.6.3 trigger ............................................................................................................................ 6-46 6.6.4 operation in pwm mode ............................................................................................. 6-47 chapter 7. timer b 7.1 overview .................................................................................................................................. 7-2 7.2 block description ................................................................................................................... 7-3 7.2.1 counter and reload register (timer bi register) ....................................................... 7-4 7.2.2 count start flag ............................................................................................................... 7-5 7.2.3 timer bi mode register .................................................................................................. 7-6 7.2.4 timer bi interrupt control register ................................................................................ 7-7 7.2.5 port p6 direction register .............................................................................................. 7-8 7.2.6 port function control register ......................................................................................... 7-9 7.3 timer mode (bits 1 and 0 of timer bi mode register = 00 2 ) ................................ 7-10 7.3.1 setting for timer mode ................................................................................................. 7-12 7.3.2 count source ................................................................................................................. 7-14 7.3.3 operation in timer mode .............................................................................................. 7-15 7.4 event counter mode (bits 1 and 0 of timer bi mode register = 01 2 ) ................. 7-17 7.4.1 setting for event counter mode .................................................................................. 7-19 7.4.2 operation in event counter mode ............................................................................... 7-21 7.4.3 selectable functions ..................................................................................................... 7-22 7.5 pulse period/pulse width measurement mode (bits 1 and 0 of timer bi mode register = 10 2 ) ... 7-25 7.5.1 setting for pulse period/pulse width measurement mode ...................................... 7-27 7.5.2 count source ................................................................................................................. 7-29 7.5.3 operation in pulse period/pulse width measurement mode ................................... 7-30 7.6 clock timer ............................................................................................................................ 7-34 7.6.1 setting for clock timer .................................................................................................. 7-37 7.6.2 operation of clock timer .............................................................................................. 7-38 chapter 8. serial i/o 8.1 overview .................................................................................................................................. 8-2 8.2 block description ................................................................................................................... 8-4 8.2.1 uarti transmit/receive mode register ......................................................................... 8-5 8.2.2 uarti transmit/receive control register 0 ...................................................................8-8 8.2.3 uarti transmit/receive control register 1 ................................................................ 8-10 8.2.4 serial transmit control register .................................................................................... 8-12 8.2.5 uarti transmission register and uarti transmission buffer register .................. 8-13 8.2.6 uarti receive register and uarti receive buffer register .................................... 8-15 8.2.7 uarti baud rate register (brgi) ............................................................................... 8-17 8.2.8 interrupt control register related to uarti ............................................................... 8-18 8.2.9 ports p7 and p8 direction registers ........................................................................... 8-20
7733 group users manual table of contents iv 8.3 clock synchronous serial i/o mode ................................................................................ 8-21 8.3.1 transfer clock (sync clock) ......................................................................................... 8-22 8.3.2 transfer data format ..................................................................................................... 8-26 8.3.3 method of transmission ................................................................................................ 8-27 8.3.4 transmit operation ........................................................................................................ 8-32 8.3.5 method of reception ..................................................................................................... 8-35 8.3.6 receive operation ......................................................................................................... 8-39 8.3.7 processing when an overrun error is detected ....................................................... 8-42 8.3.8 precautions for clock synchronous serial i/o .......................................................... 8-43 8.4 clock asynchronous serial i/o (uart) mode ............................................................... 8-44 8.4.1 transfer rate (baud rate: transfer clock frequency) ................................................ 8-45 8.4.2 transfer data format ..................................................................................................... 8-47 8.4.3 method of transmission ................................................................................................ 8-49 8.4.4 transmit operation ........................................................................................................ 8-53 8.4.5 method of reception ..................................................................................................... 8-56 8.4.6 receive operation ......................................................................................................... 8-59 8.4.7 processing when error is detected ............................................................................. 8-61 8.4.8 precautions for uart .................................................................................................. 8-61 8.4.9 sleep mode (uart0 and uart1) ............................................................................. 8-62 chapter 9. a-d converter 9.1 overview .................................................................................................................................. 9-2 9.2 block description ................................................................................................................... 9-3 9.2.1 a-d control register 0 .................................................................................................... 9-4 9.2.2 a-d control register 1 .................................................................................................... 9-6 9.2.3 a-d register i (i = 0 to 7) .............................................................................................. 9-7 9.2.4 a-d/uart2 trans./rece. interrupt control register ...................................................... 9-8 9.2.5 port p7 direction register ............................................................................................ 9-10 9.3 a-d conversion method ...................................................................................................... 9-11 9.4 absolute accuracy and differential non-linearity error .............................................. 9-14 9.4.1 absolute accuracy ........................................................................................................ 9-14 9.4.2 differential non-linearity error ...................................................................................... 9-15 9.4.3 comparison voltage when resolution = 8 bits ......................................................... 9-16 9.5 one-shot mode ..................................................................................................................... 9-17 9.5.1 setting for one-shot mode ........................................................................................... 9-17 9.5.2 operation in one-shot mode ........................................................................................ 9-19 9.6 repeat mode ......................................................................................................................... 9-20 9.6.1 setting example for repeat mode ............................................................................... 9-20 9.6.2 operation in repeat mode ........................................................................................... 9-22 9.7 single sweep mode ............................................................................................................. 9-23 9.7.1 setting for single sweep mode ................................................................................... 9-23 9.7.2 operation in single sweep mode ................................................................................ 9-25 9.8 repeat sweep mode ............................................................................................................ 9-27 9.8.1 setting for repeat sweep mode .................................................................................. 9-27 9.8.2 operation in repeat sweep mode ............................................................................... 9-29 9.9 precautions for a-d converter .......................................................................................... 9-31 chapter 10. watchdog timer 10.1 block description ............................................................................................................... 10-2 10.1.1 watchdog timer ........................................................................................................... 10-3 10.1.2 watchdog timer frequency selection flag ................................................................ 10-4
7733 group users manual v table of contents 10.2 operation description ....................................................................................................... 10-5 10.2.1 basic operation ........................................................................................................... 10-5 10.2.2 operation in stop mode ............................................................................................. 10-6 10.2.3 operation in wait mode ............................................................................................. 10-7 10.2.4 operation in hold state .............................................................................................. 10-8 10.3 precautions for watchdog timer ................................................................................... 10-10 chapter 11. stop and wait modes 11.1 overview .............................................................................................................................. 11-2 11.2 clock generating circuit ................................................................................................... 11-3 11.3 stop mode ........................................................................................................................... 11-6 11.3.1 output levels of external bus and bus control signals in stop mode ................. 11-7 11.3.2 stop mode terminating operation by interrupt request occurrence (when using watchdog timer) 11-9 11.3.3 stop mode terminating operation by interrupt request occurrence (when not using watchdog timer) .............................................................................................. 11-10 11.3.4 stop mode terminating operation by hardware reset .......................................... 11-12 11.3.5 precautions for stop mode ...................................................................................... 11-12 11.4 wait mode .......................................................................................................................... 11-13 11.4.1 state of clocks f 2 to f 512 in wait mode ................................................................ 11-15 11.4.2 output levels of external bus and bus control signals in wait mode ............... 11-15 11.4.3 wait mode terminating operation by interrupt request occurrence ................... 11-17 11.4.4 wait mode terminating operation by hardware reset .......................................... 11-17 chapter 12. connecting external devices 12.1 signals required for accessing external devices ...................................................... 12-2 12.1.1 external bus (a 0 to a 7 , a 8 /d 8 to a 15 /d 15 , and a 16 /d 0 to a 23 /d 7 ) ..................... 12-5 12.1.2 external data bus width selection signal (pin bytes level) ................................ 12-6 __ 12.1.3 enable signal (e) ........................................................................................................ 12-6 __ 12.1.4 read/write signal (r/w) ............................................................................................ 12-6 ____ 12.1.5 byte high enable signal (bhe) ................................................................................. 12-7 12.1.6 address latch enable signal (ale) ........................................................................... 12-7 ____ 12.1.7 signal related to ready function (rdy) .................................................................. 12-7 _____ _____ 12.1.8 signals related to hold function (hold, hlda) .................................................... 12-7 12.1.9 clock f 1 ....................................................................................................................... 12-7 12.1.10 operation of bus interface unit (biu) ................................................................. 12-10 12.2 software wait .................................................................................................................... 12-13 12.3 ready function ................................................................................................................. 12-16 12.3.1 operation in ready state .......................................................................................... 12-17 12.4 hold function .................................................................................................................... 12-19 12.4.1 operation in hold state .......................................................................................... 12-20 chapter 13. reset 13.1 hardware reset ................................................................................................................... 13-2 13.1.1 pin state ...................................................................................................................... 13-3 13.1.2 state of cpu, sfr area, and internal ram area ................................................. 13-4 13.1.3 internal processing sequence after a reset ........................................................... 13-9 ______ 13.1.4 time required for applying l level to pin reset ............................................ 13-10 13.2 software reset ................................................................................................................... 13-12
7733 group users manual table of contents vi chapter 14. clock generating circuit 14.1 overview .............................................................................................................................. 14-2 14.2 oscillation circuit example .............................................................................................. 14-3 14.2.1 main-clock oscillation circuit example ..................................................................... 14-3 14.2.2 sub-clock oscillation circuit example ...................................................................... 14-4 14.3 clock control ...................................................................................................................... 14-5 14.3.1 clock generated in clock generating circuit ........................................................... 14-6 14.3.2 system clock switching procedure ........................................................................ 14-11 14.3.3 clock transition ......................................................................................................... 14-14 14.3.4 clock prescaler reset ............................................................................................... 14-15 chapter 15. electrical characteristics 15.1 absolute maximum ratings ............................................................................................. 15-2 15.2 recommended operating conditions ............................................................................ 15-3 15.3 electrical characteristics ................................................................................................. 15-4 15.4 a-d converter characteristics ......................................................................................... 15-5 15.5 internal peripheral devices .............................................................................................. 15-6 15.6 ready and hold ............................................................................................................... 15-11 15.7 single-chip mode ............................................................................................................. 15-13 15.8 memory expansion mode and microprocessor mode : with no wait ................. 15-15 15.9 memory expansion mode and microprocessor mode : with wait 1 ................... 15-17 15.10 memory expansion mode and microprocessor mode : with wait 0 ................. 15-19 _ 15.11 testing circuit for ports p0 to p8, f 1 , and e ....................................................... 15-21 chapter 16. standard characteristics 16.1 standard characteristics .................................................................................................. 16-2 16.1.1 programmable i/o port (cmos output) standard characteristics: p0 to p3, p4 0 to p4 3 , p5 4 to p5 7 , p6, p7, and p8 ......................................................................................................................................... 16-2 16.1.2 programmable i/o port (cmos output) standard characteristics: p4 4 to p4 7 and p5 0 to p5 3 ..... 16-3 16.1.3 iccCf(x in ) standard characteristics ........................................................................... 16-4 16.1.4 a-d converter standard characteristics .................................................................... 16-5 chapter 17. applications 17.1 memory expansion ............................................................................................................. 17-2 17.1.1 memory expansion model .......................................................................................... 17-2 17.1.2 calculation ways for timing ....................................................................................... 17-4 17.1.3 points in memory expansion ..................................................................................... 17-7 17.1.4 memory expansion example ................................................................................... 17-19 17.1.5 i/o expansion example ............................................................................................ 17-25 17.2 serial i/o ............................................................................................................................ 17-28 17.2.1 connection examples with external device (clock synchronous serial i/o mode) ....................... 17-28 17.2.2 examples of transmission for several peripheral ics (clock synchronous serial i/o mode) ..... 17-30 17.2.3 transmission/reception example (uart mode, transfer data length = 8 bits) ........................... 17-33 17.2.4 8-bit transmission example (clock synchronous serial i/o mode) .................... 17-38 17.3 watchdog timer ................................................................................................................ 17-41 17.3.1 program runaway detection example .................................................................... 17-41
7733 group users manual vii table of contents 17.4 power saving .................................................................................................................... 17-44 17.4.1 power saving example with stop mode used ...................................................... 17-44 17.4.2 power saving example with wait mode used ....................................................... 17-49 17.5 timer b ............................................................................................................................... 17-54 17.5.1 application example of clock timer ....................................................................... 17-54 chapter 18. low voltage version 18.1 performance overview ...................................................................................................... 18-3 18.2 pin configuration ............................................................................................................... 18-4 18.3 functional description ...................................................................................................... 18-5 18.3.1 power-on reset condition ........................................................................................... 18-6 18.4 electrical characteristics ................................................................................................. 18-7 18.4.1 absolute maximum ratings ........................................................................................ 18-7 18.4.2 recommended operating conditions ....................................................................... 18-8 18.4.3 electrical characteristics ............................................................................................ 18-9 18.4.4 a-d converter characteristics ................................................................................. 18-10 18.4.5 internal peripheral devices ...................................................................................... 18-11 18.4.6 ready and hold ........................................................................................................ 18-16 18.4.7 single-chip mode ...................................................................................................... 18-18 18.4.8 memory expansion mode and microprocessor mode : with no wait ................ 18-20 18.4.9 memory expansion mode and microprocessor mode : with wait 1 .................. 18-22 18.4.10 memory expansion mode and microprocessor mode : with wait 0 ................ 18-24 _ 18.4.11 testing circuit for ports p0 to p8, f 1 , and e ................................................... 18-26 18.5 standard characteristics ................................................................................................ 18-27 18.5.1 programmable i/o port (cmos output) standard characteristics: p0 to p3, p4 0 to p4 3 , p5 4 to p5 7 , p6, p7, and p8 ...................................................................................................................................... 18-27 18.5.2 programmable i/o port (cmos output) standard characteristics: p4 4 to p4 7 and p5 0 to p5 3.. 18-28 18.5.3 iccCf(x in ) standard characteristics ........................................................................ 18-29 18.5.4 a-d converter standard characteristics ................................................................. 18-30 18.6 application ........................................................................................................................ 18-32 18.6.1 memory expansion .................................................................................................... 18-32 18.6.2 memory expansion example in minimum model .................................................. 18-34 18.6.3 memory expansion example in medium model a ............................................... 18-36 18.6.4 memory expansion example in maximum model ................................................. 18-38 18.6.5 ready generation circuit example ......................................................................... 18-40 chapter 19. built-in prom version 19.1 eprom mode ..................................................................................................................... 19-3 19.1.1 pin functions in eprom mode ................................................................................. 19-3 19.1.2 read/program from and to built-in prom ............................................................. 19-4 19.1.3 programming algorithm to built-in prom ............................................................... 19-8 19.1.4 electrical characteristics of the programming algorithm ....................................... 19-9 19.2 usage precaution ............................................................................................................ 19-10 chapter 20. external rom version 20.1 performance overview ...................................................................................................... 20-3 20.2 pin configuration ............................................................................................................... 20-4 20.3 pin description ................................................................................................................... 20-5 20.4 block description ............................................................................................................... 20-7
7733 group user s manual table of contents viii 20.5 memory allocation ............................................................ ................................................. 20-8 20.6 processor modes ............................................................ ................................................. 20-11 20.7 timer a ............................................................ ............................................................ ....... 20-12 20.7.1 overview ............................................................ ........................................................ 20-12 20.7.2 pulse output port mode ............................................................ ............................... 20-13 20.8 reset ............................................................ ............................................................ ........... 20-26 20.9 electrical characteristics ............................................................ .................................... 20-29 20.10 low voltage version ............................................................ .......................................... 20-30 20.10.1 performance overview ............................................................ ................................ 20-30 20.10.2 pin configuration ............................................................ ......................................... 20-31 20.10.3 functional description ............................................................ ................................ 20-32 20.10.4 electrical characteristics ............................................................ ............................ 20-32 appendix appendix 1. memory allocation of 7733 group ............................................................ ....... 21-2 appendix 2. memory allocation in sfr area ............................................................ ............ 21-6 appendix 3. control registers ............................................................ ................................... . 21-10 appendix 4. package outlines ............................................................ ................................... 21-38 appendix 5. hexadecimal instruction code table ............................................................ . 21-41 appendix 6. machine instructions ............................................................ ............................ 21-44 appendix 7. examples of handling unused pins ............................................................ . 21-58 appendix 8. countermeasure examples against noise ................................................... 21-61 appendix 9. q & a ............................................................ ....................................................... 21-71
7735 group users manual ix table of contents part 2 7735 group chapter 1. overview 1.1 performance overview ............................................................ ............................................... 1 - 2 1.2 pin configuration ............................................................ ........................................................ 1 - 3 1.3 pin description ............................................................ ........................................................... 1 - 4 1.3.1 examples of handling unused pins ............................................................ .................. 1 - 6 1.4 block diagram ............................................................ ......................................... 1-11 in part 1 chapter 2. central processing unit (cpu) 2.1 central processing unit ............................................................ .......................... 2-2 in part 1 2.2 bus interface unit ............................................................ ...................................................... 2 - 2 2.3 accessible area ............................................................ .......................................................... 2 - 5 2.4 memory allocation ............................................................ .................................. 2-18 in part 1 2.5 processor modes ............................................................ ....................................................... 2 - 6 ____ ____ 2.5.4 relationship between access addresses and chip select signals cs 0 to cs 4 .......... 2-9 chapter 3. programmable i/o ports 3.1 programmable i/o ports ............................................................ ......................... 3-2 in part 1 3.2 port peripheral circuits ............................................................ ............................................. 3 - 2 3.3 pull-up function ............................................................ ........................................ 3-8 in part 1 3.4 internal peripheral devices i/o functions (ports p4 2 and p5 to p8) ..... 3-10 in part 1 chapter 4. interrupts 4.1 overview ............................................................ ....................................................... 4-2 in part 1 4.2 interrupt sources ............................................................ ......................................... 4-4 in part 1 4.3 interrupt control ............................................................ .......................................... 4-6 in part 1 4.4 interrupt priority level ............................................................ .............................. 4-10 in part 1 4.5 interrupt priority level detection circuit .......................................................... 4-11 in part 1 4.6 interrupt priority level detection time ............................................................ .. 4-13 in part 1 4.7 how interrupts are processed (from acceptance of interru pt request until execution of interrupt routine) ............................................................ .............. 4-14 in part 1 4.8 return from interrupt routine ............................................................ ................. 4-17 in part 1 4.9 multiple interrupts ............................................................ ..................................... 4-17 in part 1 ____ 4.10 external interrupts ( inti interrupt) ............................................................ ...... 4-19 in part 1 4.11 precautions for interrupts ............................................................ ..................... 4-23 in part 1 chapter 5. key input interrupt function 5.1 overview ............................................................ ..................................................... 5-2 in part 1 5.2 block description ............................................................ ..................................... 5-3 in part 1 5.3 initial setting example for related registers .................................................. 5-7 in part 1
7735 group users manual table of contents x chapter 6. timer a 6.1 overview ................................................................................................................. 6-2 in part 1 6.2 block description ................................................................................................. 6-3 in part 1 6.3 timer mode (bits 1 and 0 of timer ai mode register = 00 2 ) ................. 6-9 in part 1 6.4 event counter mode (bits 1 and 0 of timer ai mode register = 01 2 ) ............................ 6-19 in part 1 6.5 one-shot pulse mode (bits 1 and 0 of timer ai mode register = 10 2 ) ......................... 6-32 in part 1 6.6 pulse width modulation (pwm) mode (bits 1 and 0 of timer ai mode register = 11 2 ) ................................................................................................... 6-41 in part 1 chapter 7. timer b 7.1 overview ................................................................................................................. 7-2 in part 1 7.2 block description ................................................................................................. 7-3 in part 1 7.3 timer mode (bits 1 and 0 of timer bi mode register = 00 2 ) ............... 7-10 in part 1 7.4 event counter mode (bits 1 and 0 of timer bi mode register = 01 2 ) 7-17 in part 1 7.5 pulse period/pulse width measurement mode (bits 1 and 0 of timer bi mode register = 10 2 ) ..................................................................................... 7-25 in part 1 7.6 clock timer .......................................................................................................... 7-34 in part 1 chapter 8. serial i/o 8.1 overview ................................................................................................................. 8-2 in part 1 8.2 block description ................................................................................................. 8-4 in part 1 8.3 clock synchronous serial i/o mode .............................................................. 8-21 in part 1 8.4 clock asynchronous serial i/o (uart) mode .............................................. 8-44 in part 1 chapter 9. a-d converter 9.1 overview ................................................................................................................. 9-2 in part 1 9.2 block description ................................................................................................. 9-3 in part 1 9.3 a-d conversion method .................................................................................... 9-11 in part 1 9.4 absolute accuracy and differential non-linearity error ............................. 9-14 in part 1 9.5 one-shot mode ................................................................................................... 9-17 in part 1 9.6 repeat mode ....................................................................................................... 9-20 in part 1 9.7 single sweep mode ........................................................................................... 9-23 in part 1 9.8 repeat sweep mode .......................................................................................... 9-27 in part 1 9.9 precautions for a-d converter ........................................................................ 9-31 in part 1 chapter 10. watchdog timer 10.1 block description ................................................................................................ 10-2 in part 1 10.2 operation description ....................................................................................................... 10-2 10.3 precautions for watchdog timer .................................................................... 10-10 in part 1 chapter 11. stop and wait modes 11.1 overview ............................................................................................................ 11-2 in part 1 11.2 clock generating circuit ................................................................................................... 11-2 11.3 stop mode ........................................................................................................................... 11-3 11.4 wait mode ............................................................................................................................ 11-6
7735 group users manual xi table of contents chapter 12. connecting external devices 12.1 signals required for accessing external devices ...................................................... 12-3 ____ ____ 12.1.1 external bus (a 0 /d 0 to a 15 /d 15 , a 16 and a 17 ) and chip select signals ( cs 0 to cs 4 ) .................... 12-6 12.1.2 external data bus width selection signal (pin bytes level) ................................ 12-8 ____ ____ ____ 12.1.3 read enable signal (rde) and write enable signals (wel, weh) ................... 12-8 12.1.4 address latch enable signal (ale) ........................................................................... 12-8 ____ _____ 12.1.5 signals related to ready function (rdy, rsmp) ................................................... 12-8 _____ _____ 12.1.6 signals related to hold function (hold, hlda) .................................................... 12-8 12.1.7 clock f 1 ....................................................................................................................... 12-8 12.1.8 operation of bus interface unit (biu) ................................................................... 12-12 12.2 software wait .................................................................................................................... 12-16 12.3 ready function ................................................................................................................. 12-19 12.3.1 operation in ready state .......................................................................................... 12-20 12.4 hold function .................................................................................................................... 12-23 12.4.1 operation in hold state ............................................................................................ 12-24 chapter 13. reset 13.1 hardware reset ................................................................................................................... 13-2 13.2 software reset ................................................................................................. 13-12 in part 1 chapter 14. clock generating circuit 14.1 overview ............................................................................................................ 14-2 in part 1 14.2 oscillation circuit example ............................................................................ 14-3 in part 1 14.3 clock control ...................................................................................................................... 14-2 chapter 15. electrical characteristics 15.1 absolute maximum ratings ........................................................................... 15-2 in part 1 15.2 recommended operating conditions .......................................................... 15-3 in part 1 15.3 electrical characteristics ............................................................................... 15-4 in part 1 15.4 a-d converter characteristics ....................................................................... 15-5 in part 1 15.5 internal peripheral devices ............................................................................ 15-6 in part 1 15.6 ready and hold ................................................................................................................. 15-3 15.7 single-chip mode ........................................................................................... 15-13 in part 1 15.8 memory expansion mode and microprocessor mode : with no wait ................... 15-5 15.9 memory expansion mode and microprocessor mode : with wait 1 ..................... 15-7 15.10 memory expansion mode and microprocessor mode : with wait 0 ................... 15-9 _ 15.11 testing circuit for ports p0 to p8, f 1 , and e ...................................... 15-21 in part 1 chapter 16. standard characteristics 16.1 standard characteristics ................................................................................... 16-2 in part 1
7735 group users manual table of contents xii chapter 17. applications 17.1 memory expansion ............................................................................................................. 17-2 17.1.1 memory expansion model .......................................................................................... 17-2 17.1.2 calculation ways for timing ....................................................................................... 17-4 17.1.3 points in memory expansion ..................................................................................... 17-7 17.1.4 memory expansion example ................................................................................... 17-19 17.1.5 i/o expansion example ............................................................................................ 17-21 17.2 serial i/o .......................................................................................................... 17-28 in part 1 17.3 watchdog timer .............................................................................................. 17-41 in part 1 17.4 power saving .................................................................................................................... 17-22 17.5 timer b ............................................................................................................. 17-54 in part 1 chapter 18. low voltage version 18.1 performance overview ...................................................................................................... 18-2 18.2 pin configuration ............................................................................................................... 18-3 18.3 functional description ...................................................................................................... 18-4 18.4 electrical characteristics .................................................................................................. 18-5 18.4.6 ready and hold .......................................................................................................... 18-5 18.4.8 memory expansion mode and microprocessor mode : with no wait .................. 18-7 18.4.9 memory expansion mode and microprocessor mode : with wait 1 .................... 18-9 18.4.10 memory expansion mode and microprocessor mode : with wait 0 ................ 18-11 18.5 standard characteristics .............................................................................. 18-27 in part 1 18.6 application ........................................................................................................................ 18-13 18.6.1 memory expansion .................................................................................................... 18-13 18.6.2 memory expansion example ................................................................................... 18-15 18.6.3 ready generation circuit example ......................................................................... 18-17 chapter 19. built-in prom version 19.1 eprom mode ..................................................................................................................... 19-2 19.2 usage precaution ........................................................................................... 19-10 in part 1 chapter 20. external rom version 20.1 performance overview ...................................................................................................... 20-3 20.2 pin configuration ............................................................................................................... 20-4 20.3 pin description ................................................................................................................... 20-5 20.4 block description ............................................................................................................... 20-7 20.5 memory allocation ............................................................................................................. 20-8 20.6 processor modes ............................................................................................................. 20-11 20.7 timer a ............................................................................................................................... 20-12 20.8 reset ................................................................................................................................... 20-12 20.9 electrical characteristics ................................................................................................ 20-15 20.10 low voltage version ...................................................................................................... 20-16 20.10.1 performance overview ............................................................................................ 20-16 20.10.2 pin configuration ..................................................................................................... 20-17 20.10.3 functional description ............................................................................................ 20-18 20.10.4 electrical characteristics ........................................................................................ 20-18
7735 group user s manual xiii table of contents appendix appendix 1. memory allocation of 7735 group ............................................................ ...... 21-3 appendix 2. memory allocation in sfr area ............................................................ ........... 21-7 appendix 3. control registers ............................................................ ...................................... 21-9 appendix 4. package outlines ............................................................ ................. 21-38 in part 1 appendix 5. hexadecimal instruction code table ............................................ 21-41 in part 1 appendix 6. machine instructions ............................................................ .......... 21-44 in part 1 appendix 7. examples of handling unused pins ............................................................ . 21-11 appendix 8. countermeasure examples against noise .................................. 21-61 in part 1 appendix 9. q & a ............................................................ ..................................... 21-71 in part 1
7736 group users manual table of contents xiv part 3 7736 group chapter 1. overview 1.1 performance overview ............................................................ ............................................... 1 - 2 1.2 pin configuration ............................................................ ........................................................ 1 - 3 1.3 pin description ............................................................ ........................................................... 1 - 4 1.3.1 examples of handling unused pins ............................................................ .................. 1 - 8 1.4 block diagram ............................................................ ........................................................... 1-13 chapter 2. central processing unit (cpu) 2.1 central processing unit ............................................................ ............................ 2C2 in part 1 2.2 bus interface unit external bus mode a ............................................................ ............................... 2C10 in part 1 external bus mode b ............................................................ ................................. 2C2 in part 2 2.3 accessible area external bus mode a ............................................................ ............................... 2C16 in part 1 external bus mode b ............................................................ ................................. 2C5 in part 2 2.4 memory allocation ............................................................ .................................... 2C18 in part 1 2.5 processor modes ............................................................ ....................................................... 2 - 2 chapter 3. programmable i/o ports 3.1 programmable i/o ports and output-only ports ............................................................ 3 - 2 3.1.1 port pi direction register ............................................................ ................................... 3 - 3 3.1.2 port pi register ............................................................ ................................................... 3 - 4 3.2 port peripheral circuits ............................................................ ............................................ 3 - 6 3.3 pull-up function ............................................................ ......................................................... 3 - 8 ___ ___ 3.3.1 pull-up function for ports p10 4 to p10 7 (ki 0 to ki 3 ) ................................................ 3 - 8 ____ ____ 3.3.2 pull-up function for ports p6 2 to p6 4 (int 0 to int 2 ) ................................................ 3 - 8 3.4 internal peripheral devices i/o functions (ports p4 2 , p5 to p8, p9 0 to p9 3 and p10 4 to p10 7 ) ..... 3-10 chapter 4. interrupts 4.1 overview ............................................................ ....................................................... 4-2 in part 1 4.2 interrupt sources ............................................................ ......................................... 4-4 in part 1 4.3 interrupt control ............................................................ .......................................... 4-6 in part 1 4.4 interrupt priority level ............................................................ .............................. 4-10 in part 1 4.5 interrupt priority level detection circuit .......................................................... 4-11 in part 1 4.6 interrupt priority level detection time ............................................................ .. 4-13 in part 1 4.7 how interrupts are processed (from acceptance of interru pt request until execution of interrupt routine) ............................................................ ..... 4-14 in part 1 4.8 return from interrupt routine ............................................................ ................. 4-17 in part 1 4.9 multiple interrupts ............................................................ ..................................... 4-17 in part 1 ____ 4.10 external interrupts ( inti interrupt) ............................................................ ...... 4-19 in part 1 4.11 precautions for interrupts ............................................................ ..................... 4-23 in part 1
7736 group users manual xv table of contents chapter 5. key input interrupt function 5.1 overview ................................................................................................................................. 5-2 5.2 block description .................................................................................................................. 5-3 ___ ___ ____ 5.2.1 pins ki 0 to ki 3 and p6 4 /int 2 ............................................................................................................ 5-3 5.2.2 port function control register ........................................................................................ 5-4 5.2.3 interrupt function ............................................................................................................ 5-6 5.3 initial setting example for related registers ................................................................... 5-7 chapter 6. timer a 6.1 overview ................................................................................................................. 6-2 in part 1 6.2 block description ................................................................................................. 6-3 in part 1 6.3 timer mode (bits 1 and 0 of timer ai mode register = 00 2 ) ................. 6-9 in part 1 6.4 event counter mode (bits 1 and 0 of timer ai mode register = 01 2 ) .............................. 6-19 in part 1 6.5 one-shot pulse mode (bits 1 and 0 of timer ai mode register = 10 2 ) ........................... 6-32 in part 1 6.6 pulse width modulation (pwm) mode (bits 1 and 0 of timer ai mode register = 11 2 ) ................................................................................................... 6-41 in part 1 chapter 7. timer b 7.1 overview ................................................................................................................. 7-2 in part 1 7.2 block description ................................................................................................. 7-3 in part 1 7.3 timer mode (bits 1 and 0 of timer bi mode register = 00 2 ) ............... 7-10 in part 1 7.4 event counter mode (bits 1 and 0 of timer bi mode register = 01 2 ) ............................ 7-17 in part 1 7.5 pulse period/pulse width measurement mode (bits 1 and 0 of timer bi mode register = 10 2 ) ..................................................................................... 7-25 in part 1 7.6 clock timer .......................................................................................................... 7-34 in part 1 chapter 8. serial i/o 8.1 overview ................................................................................................................... 8-2 in part 1 8.2 block description .................................................................................................................. 8-2 8.2.9 port p8 direction register ............................................................................................. 8-3 8.3 clock synchronous serial i/o mode ................................................................................. 8-4 8.4 clock asynchronous serial i/o (uart) mode ................................................................. 8-5 chapter 9. a-d converter 9.1 overview ................................................................................................................... 9-2 in part 1 9.2 block description ................................................................................................................... 9-2 9.2.5 port p7 direction register .............................................................................................. 9-3 9.3 a-d conversion method ....................................................................................... 9-11 in part 1 9.4 absolute accuracy and differential non-linearity error ............................... 9-14 in part 1 9.5 one-shot mode ...................................................................................................... 9-17 in part 1 9.6 repeat mode .......................................................................................................... 9-20 in part 1 9.7 single sweep mode .............................................................................................. 9-23 in part 1 9.8 repeat sweep mode ............................................................................................. 9-27 in part 1 9.9 precautions for a-d converter ........................................................................... 9-31 in part 1
7736 group users manual table of contents xvi chapter 10. watchdog timer 10.1 block description ................................................................................................ 10-2 in part 1 10.2 operation description ....................................................................................................... 10-2 10.3 precautions for watchdog timer .................................................................... 10-10 in part 1 chapter 11. stop and wait modes 11.1 overview external bus modes a .......................................................................................... 11-2 in part 1 external bus modes b .......................................................................................... 11-2 in part 2 11.2 clock generating circuit external bus mode a ............................................................................................ 11-3 in part 1 external bus mode b ............................................................................................ 11-2 in part 2 11.3 stop mode external bus mode a ............................................................................................ 11-6 in part 1 external bus mode b ............................................................................................ 11-3 in part 2 11.4 wait mode external bus mode a .......................................................................................... 11-13 in part 1 external bus mode b ............................................................................................ 11-6 in part 2 chapter 12. connecting external devices 12.1 signals required for accessing external devices external bus mode a ............................................................................................ 12-2 in part 1 external bus mode b ............................................................................................ 12-3 in part 2 12.2 software wait external bus mode a .......................................................................................... 12-13 in part 1 external bus mode b .......................................................................................... 12-16 in part 2 12.3 ready function external bus mode a .......................................................................................... 12-16 in part 1 external bus mode b .......................................................................................... 12-19 in part 2 12.4 hold function external bus mode a .......................................................................................... 12-19 in part 1 external bus mode b .......................................................................................... 12-23 in part 2 chapter 13. reset 13.1 hardware reset ................................................................................................................... 13-2 13.2 software reset .................................................................................................... 13-12 in part 1 chapter 14. clock generating circuit 14.1 overview ............................................................................................................... 14-2 in part 1 14.2 oscillation circuit example ............................................................................... 14-3 in part 1 14.3 clock control ...................................................................................................................... 14-2
7736 group users manual xvii table of contents chapter 15. electrical characteristics 15.1 absolute maximum ratings ............................................................ ................................ 15-2 15.2 recommended operating conditions ............................................................ ................ 15-3 15.3 electrical characteristics ............................................................ ..................................... 15-4 15.4 a-d converter characteristics ............................................................ ........... 15-5 in part 1 15.5 internal peripheral devices ............................................................ ................ 15-6 in part 1 15.6 ready and hold external bus mode a ............................................................ ............................ 15-11 in part 1 external bus mode b ............................................................ .............................. 15-3 in part 2 15.7 single-chip mode ............................................................ .................................................. 15-6 15.8 memory expansion mode and microprocessor mode : with no wait external bus mode a ............................................................ ............................ 15-15 in part 1 external bus mode b ............................................................ .............................. 15-5 in part 2 15.9 memory expansion mode and microprocessor mode : with wa it 1 external bus mode a ............................................................ ............................ 15-17 in part 1 external bus mode b ............................................................ .............................. 15-7 in part 2 15.10 memory expansion mode and microprocessor mode : with w ait 0 external bus mode a ............................................................ ............................ 15-19 in part 1 external bus mode b ............................................................ ............................... 15-9 in part 2 _ 15.11 measuring circuit for ports p0 to p10 and pins f 1 and e .................................... 15-8 chapter 16. standard characteristics 16.1 standard characteristics ............................................................ ...................................... 16-3 16.1.1 programmable i/o port (cmos output) standard characte ristics: p0 to p3, p4 0 to p4 3 , p5 to p9, and p10 4 to p10 7 ............................................................ ... 16-3 16.1.2 programmable i/o port (cmos output) standard characte ristics: p4 4 to p4 7 and p10 0 to p10 3 ............................................................ ............................................................ ........ 16-4 16.1.3 iccCf(x in ) standard characteristics ............................................................ . 16-4 in part 1 16.1.4 a-d converter standard characteristics ...................................................... 16-5 in part 1 chapter 17. applications 17.1 memory expansion external bus mode a ............................................................ ............................... 17C2 in part 1 external bus mode b ............................................................ ............................... 17C2 in part 2 17.2 serial i/o ............................................................ ................................................ 17C28 in part 1 17.3 watchdog timer ............................................................ .................................... 17C41 in part 1 17.4 power saving ............................................................ .......................................................... 17-3 17.4.1 power saving example with stop mode used ......................................................... 17-3 17.4.2 power saving example with wait mode used .......................................................... 17-8 17.5 timer b ............................................................ ................................................... 17C54 in part 1 chapter 18. low voltage version 18.1 performance overview ............................................................ ......................................... 18-3 18.2 pin configuration ............................................................ .................................................. 18-4 18.3 functional description ............................................................ ......................................... 18-5
7736 group user s manual table of contents xviii 18.4 electrical characteristics ............................................................ ..................................... 18-6 18.4.1 absolute maximum ratings ............................................................ ........................... 18-7 18.4.2 recommended operating conditions ............................................................ ........... 18-8 18.4.3 electrical characteristics ............................................................ ............................... 18-9 18.4.4 a-d converter characteristics ............................................................ ....... 18-10 in part 1 18.4.5 internal peripheral devices ............................................................ ........... 18-11 in part 1 18.4.6 ready and hold external bus mode a ............................................................ .................... 18-16 in part 1 external bus mode b ............................................................ ...................... 18-5 in part 2 18.4.7 single-chip mode ............................................................ .......................................... 18-11 18.4.8 memory expansion mode and microprocessor mode : with no wait external bus mode a ............................................................ .................... 18-20 in part 1 external bus mode b ............................................................ ...................... 18-7 in part 2 18.4.9 memory expansion mode and microprocessor mode : with wait 1 external bus mode a ............................................................ .................... 18-22 in part 1 external bus mode b ............................................................ ...................... 18-9 in part 2 18.4.10 memory expansion mode and microprocessor mode : with wait 0 external bus mode a ............................................................ .................... 18-24 in part 1 external bus mode b ............................................................ .................... 18-11 in part 2 _ 18.4.11 measuring circuit for ports p0 to p10 and pins f 1 and e .................................. 18-13 18.5 standard characteristics ............................................................ ................................... 18-14 18.5.1 programmable i/o port (cmos output) standard characteristics : ports p0 to p3, p 4 0 to p4 3 , p5 to p9 and p10 4 to p10 7 ............................................................ .............. 18-14 18.5.2 programmable i/o port (cmos output) standard characteristics : ports p4 4 to p4 7 and p5 0 to p5 3 ............................................................ ............................................................ ........ 18-15 18.6 applications ............................................................ ......................................................... 18-16 external bus mode a ............................................................ .............................. 18-32 in part 1 external bus mode b ............................................................ .............................. 18-13 in part 2 chapter 19. built-in prom version 19.1 eprom mode ............................................................ .......................................................... 19-2 19.2 usage precaution ............................................................ .................................. 19-10 in part 1 appendix appendix 1. memory allocation of 7736 group ............................................................ ....... 20-3 appendix 2. memory allocation in sfr area ............................................................ ............ 20-6 appendix 3. control registers ............................................................ ...................................... 20-8 appendix 4. package outlines ............................................................ ................................... 20-12 appendix 5. hexadecimal instruction code table ............................................. 21-41 in part 1 appendix 6. machine instructions ............................................................ ............ 21-44 in part 1 appendix 7. examples of handling unused pins ............................................................ .. 20-14 appendix 8. countermeasure examples against noise ................................... 21-61 in part 1 appendix 9. q & a ............................................................ ....................................... 21-71 in part 1 glossary
part 1 part 1 7733 group chapter 1 overview chapter 2 central processing unit (cpu) chapter 3 programmable i/o ports chapter 4 interrupts chapter 5 key input interrupt function chapter 6 timer a chapter 7 timer b chapter 8 serial i/o chapter 9 a-d converter chapter 10 watchdog timer chapter 11 stop and wait modes chapter 12 connecting external devices chapter 13 reset chapter 14 clock generating circuit chapter 15 electrical characteristics chapter 16 standard characteristics chapter 17 applications chapter 18 low voltage version chapter 19 built-in prom version chapter 20 external rom version appendix
7733 group users manual 2 part 1 7733 group the 7733 group is described in part 1. for the 7735 group, refer to part 2. 7735 group. in part 2, the differences between the 7735 group and the 7733 group are mainly described. for the 7736 group, refer to part 3. 7736 group. in part 3, the differences between the 7736 group and the 7733 group are mainly described.
chapter 1 chapter 1 overview 1.1 performance overview 1.2 pin configuration 1.3 pin description 1.4 block diagram
overview 1-2 7733 group users manual the 7733 group is a 16-bit single-chip microcomputer designed with high-performance cmos silicon gate technology. it is housed in an 80-pin plastic molded flat package. this single-chip microcomputer has a large 16-mbyte accessible space, three instruction queue buffers, and two data buffers for high-speed instruction execution. the cpu is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. this microcomputer is suitable for communication and office equipment controllers. h about details concerning each microcomputers development state of the 7733 group, inquire contact addresses for further information described last. h functional codes of the 7733 group are described below. m 3 77 33 m h b xxx fp represents mitsubishi integrated prefix represents uses and operating temperature range represents circuit type and family name represents group name 2-digit numerals (running number) represents memory type m:mask rom e:eprom s:external rom represents memory size 1-digit alphanumeric represents electrical characteristics represents roms contents 3-digit numerals package type fp: molded plastic flat package gp: molded plastic flat package hp: molded fine-pitch plastic flat package sp: molded plastic sdip fs: ceramic flat package
overview 7733 group users manual 1-3 rom ram ports p0Cp2, p4Cp8 port p3 timers a0Ca4 timers b0Cb2 uart0Cuart2 main-clock oscillation circuit sub-clock oscillation circuit input/output withstand voltage output current items number of basic instructions the minimum instruction execution time main-clock frequency f(x in ) sub-clock frequency f(x cin ) memory size programmable i/o ports multifunction timers serial i/o a-d converter watchdog timer interrupts clock generating circuits power source voltage power consumption in single-chip mode port input/output characteristics memory expansion operating temperature range device structure package 1.1 performance overview table 1.1.1 lists the m37733mhbxxxfps performance overview. table 1.1.1 m37733mhbxxxfps performance overview performance 103 160 ns (when f(x in ) = 25 mhz and the main clock is the system clock) 25 mhz (max.) (note 3) 32.768 khz (typ.) 124 kbytes 3968 bytes 8 bits 5 8 4 bits 5 1 16 bits 5 5 16 bits 5 3 (uart or clock synchronous serial i/o) 5 3 (10-bit successive approximation method) 5 1 (8 channels) 12 bits 5 1 3 external, 16 internal (by software, one of interrupt priority levels 0 to 7 can be set for each interrupt) built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator.) built-in (externally connected to a quartz-crystal oscillator) 5 v 10% (when the main clock is the system clock) 2.7 v to 5.5 v (when the sub clock is the system clock) 47.5 mw (when f(x in ) = 25 mhz, v cc = 5 v, and the main clock is the system clock, typ.) 250 m w (when f(x cin ) = 32 khz, v cc = 5 v, the sub clock is the system clock, and the main clock is stopped, typ.) 5 v 5 ma possible (maximum of 16 mbytes) C20 c to +85 c high-performance cmos silicon gate process 80-pin plastic molded qfp notes 1: all of the 7733 group microcomputers are the same except for package type, memory type, memory size, and electrical characteristics. 2: for the low voltage version, refer to chapter 18. low voltage version. 3: when the main clock division selection bit = 1, the maximum value of f(x in ) = 12.5 mhz. 1.1 performance overview
over view 1-4 7733 group users manual 1.2 pin configuration figure 1.2.1 shows the m37733mhbxxxfp pin configuration. note: for the low voltage version, refer to chapter 18. low voltage version. fig. 1.2.1 m37733mhbxxxfp pin configuration (top view) 1.2 pin configuration 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out p4 0 /hold byte cnv ss reset x in x out e v ss p3 3 /hlda p3 2 /ale p3 1 /bhe p3 0 /r/w p2 7 /a 23 /d 7 p2 6 /a 22 /d 6 p2 5 /a 21 /d 5 p2 4 /a 20 /d 4 p7 4 /an 4 /r x d 2 p7 5 /an 5 /ad trg /t x d 2 p7 6 /an 6 /x cout p7 7 /an 7 /x cin v ss av ss v ref av cc v cc p8 0 /cts 0 /rts 0 /clks 1 p8 1 /clk 0 p8 2 /r x d 0 /clks 0 p8 3 /t x d 0 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 /a 0 p0 1 /a 1 p0 2 /a 2 p0 3 /a 3 p0 4 /a 4 p0 5 /a 5 p0 6 /a 6 p0 7 /a 7 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 1 4 3 2 5 6 7 8 9 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 p1 7 /a 15 /d 15 p2 0 /a 16 /d 0 p2 1 /a 17 /d 1 p2 2 /a 18 /d 2 p2 3 /a 19 /d 3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 m37733mhbxxxfp 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p4 1 /rdy p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / f 1 p7 1 /an 1 p7 2 /an 2 /cts 2 p7 3 /an 3 /clk 2 outline 80p6n-a
overview 7733 group users manual 1-5 1.3 pin description tables 1.3.1C1.3.3 list the pin description. note that the pin description of the built-in prom version in the eprom mode is described in section 19.1 eprom mode. table 1.3.1 pin description (1) input/output input input input output output input input name power source input cnv ss reset input clock input clock output enable output external data bus width selection input analog power source input reference voltage input note: in the low voltage version, it is 2.7 v to 5.5 v. pin v cc , v ss cnv ss ______ reset x in x out _ e byte av cc av ss v ref functions to pin v cc , apply 5 v 10% (note) (when the main clock is the system clock) or 2.7 v to 5.5 v (when the sub clock is the system clock). to pin v ss , apply 0 v. this pin switches the processor mode. [single-chip mode] [memory expansion mode] connect to pin v ss . [microprocessor mode] connect to pin v cc . the microcomputer is reset when l level is input to this pin. pins x in and x out are the i/o pins of the clock generating circuit, respectively. connect these pins via a ceramic resonator or a quartz-crystal oscillator. when an external clock is used, the clock should be input to pin x in , and pin x out should be left open. __ this pin outputs signal e. when es level is l, the microcomputer reads data and instruction codes or _ writes data. also, output of signal e can be stopped by software. [single-chip mode] connect to pin v ss . [memory expansion mode] [microprocessor mode] input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. a 16-bit width is selected when the level is l, and an 8-bit width is selected when the level is h. power source input for the a-d converter. connect to pin v cc . power source input for the a-d converter. connect to pin v ss . this is the reference voltage input pin for the a-d converter. 1.3 pin description
overview 1-6 7733 group users manual 1.3 pin description table 1.3.2 pin description (2) input/output i/o output i/o i/o i/o output functions [single-chip mode] p0 is an 8-bit cmos i/o port and has an i/o direction register. each pin can be programmed for input or output. [memory expansion mode] [microprocessor mode] addresss low-order 8 bits (a 0 Ca 7 ) are output. [single-chip mode] p1 is an 8-bit i/o port with the same function as port p0. [memory expansion mode] [microprocessor mode] l when the external data bus width = 8 bits (pin byte is at h level) addresss middle-order 8 bits (a 8 Ca 15 ) are output. l when the external data bus width = 16 bits (pin byte is at l level) input/output of data (d 8 Cd 15 ) and output of addresss middle-order 8 bits (a 8 Ca 15 ) are performed with the time sharing method. [single-chip mode] p2 is an 8-bit i/o port with the same function as port p0. [memory expansion mode] [microprocessor mode] input/output of data (d 0 Cd 7 ) and output of addresss high-order 8 bits (a 16 Ca 23 ) are performed with the time sharing method. [single-chip mode] p3 is a 4-bit i/o port with the same function as port p0. [memory expansion mode] [microprocessor mode] __ ____ these pins respectively output signals r/ w , bhe , ale, _____ and hlda . __ l signal r/ w this signal indicates the data bus state. when this signal level is h, a data bus is in the read state. when this signal level is l, a data bus is in the write state. ____ l signal bhe this signals level is l when the microcomputer accesses an odd address. l signal ale this signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. _____ l signal hlda this signal informs the external whether this microcomputer enters the hold state or not. _____ in hold state, pin hlda outputs l level. name i/o port p0 i/o port p1 i/o port p2 i/o port p3 pin p0 0 Cp0 7 a 0 Ca 7 p1 0 Cp1 7 a 8 /d 8 C a 15 /d 15 p2 0 Cp2 7 a 16 /d 0 C a 23 /d 7 p3 0 Cp3 3 __ r/ w , ____ bhe , ale, _____ hlda
overview 7733 group users manual 1-7 1.3 pin description functions [single-chip mode] p4 is an 8-bit i/o port with the same function as port p0. p4 2 can also be programmed as the clock f 1 output pin. (refer to chapter 14. clock generating circuit. ) [memory expansion mode] _____ ____ p4 0 functions as pin hold , and p4 1 as pin rdy . _____ the microcomputer is in hold state while pin hold s ____ input level is l and is in ready state while pin rdy s input level is l. p4 2 Cp4 7 function as i/o ports with the same function as port p0. p4 2 can also be programmed as the clock f 1 output pin. (refer to chapter 14. clock generating circuit. ) [microprocessor mode] _____ ____ p4 0 functions as pin hold , p4 1 as pin rdy , and p4 2 as the clock f 1 output pin. (refer to [memory expansion mode]. ) p4 3 Cp4 7 function as i/o ports with the same function as port p0. p5 is an 8-bit i/o port with the same function as port p0 and can be programmed as i/o pins for timers a0C _____ ______ a3 and input pins ( ki 0 C ki 3 ) for the key input interrupt. p6 is an 8-bit i/o port with the same function as port p0 and can be programmed as i/o pins for timer a4, external interrupt input pins, and input pins for timers b0Cb2. p6 7 also functions as an output pin for the sub clock ( f sub ). p7 is an 8-bit i/o port with the same function as port p0 and can be programmed as analog input pins for the a-d converter. p7 6 and p7 7 can be programmed as i/o pins (x cout , x cin ) for the sub-clock (32 khz) oscillation circuit. when using p7 6 and p7 7 as pins x cout and x cin , connect a quartz-crystal oscillator between them. when inputting an external clock, input the clock from pin x cin . p7 2 Cp7 5 also function as uart2s i/o pins. p8 is an 8-bit i/o port with the same function as port p0 and can be programmed as serial i/os i/o pins. input/output i/o input input i/o input input output i/o i/o i/o i/o i/o pin p4 0 Cp4 7 _____ hold , ____ rdy , p4 2 Cp4 7 _____ hold , ____ rdy , f 1 , p4 3 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7 name i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 table 1.3.3 pin description (3)
over view 1-8 7733 group users manual 1.3 pin description 1.3.1 examples of handling unused pins the following are examples of handling unused pins. these are, however, just examples. in actual use, make the necessary adaptations and properly evaluate performance according to the users application. (1) in single-chip mode table 1.3.4 examples of handling unused pins in single-chip mode handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins open aft er they are set to the output mode ( note 1 ). leave this pin open. connect this pin to pin vcc. connect these pins to pin vss. notes 1: when leaving these pins open after they are set to the outpu t mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. for unused pins, use the shortest possible wiring (within 20 mm from the microcomputers pins). 2: this is applied when an external clock is input to pin x in . pins p0Cp8 __ e x out ( note 2 ) avcc avss, v ref , byte p0Cp8 avss v ref byte m37733mhbxxxfp vss avcc e x out left open n when setting ports to input mode v cc p0Cp8 avss v ref byte m37733mhbxxxfp vss avcc e x out left open n when setting ports to output mode left open vcc fig. 1.3.1 examples of handling unused pins in single-chip m ode
over view 7733 group users manual 1-9 1.3 pin description (2) in memory expansion mode table 1.3.5 examples of handling unused pins in memory expan sion mode pins p4 2 Cp4 7 , p5Cp8 ____ bhe ( note 3 ) ale ( note 4 ) _____ hlda x out ( note 6 ) _____ ____ hold , rdy avcc avss, v ref handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins open aft er they are set to the output mode ( notes 1, 2, and 7 ). leave this pin open. ( note 5 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be en hanced when the contents of the above ports direction registers are set periodically. this is bec ause these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputers pins). 3: this is applied when h level is input to pin byte. 4: this is applied when h level is input to pin byte and the accessible area has a capacity of 64 kbytes. 5: when vss level is applied to pin cnvss, note the following: this pin functions as an input port from reset until the processor mode is switched to the memory exp ansion mode by software. therefore, a voltage level of this pin is undefined and the power sourc e current may increase while this pin functions as an input port. 6: this is applied when an external clock is input to pin x in . 7: set pin p4 2 / f 1 as pin p4 2 . (clock f 1 output is disabled.) and then, for this pin, do the same handling as that for pins p4 3 to p4 7 and p5 to p8. p4 2 Cp4 7 , p5Cp8 avss v ref hold rdy left open m37733mhbxxxfp hlda vcc vss avcc x out n when setting ports to input mode left open p4 2 Cp4 7 , p5Cp8 avs s v ref left open vss avcc x out n when setting ports to output mode left open left open vcc m37733mhbxxxfp bhe ale hold rdy bhe ale hlda fig. 1.3.2 examples of handling unused pins in memory expans ion mode
over view 1-10 7733 group users manual 1.3 pin description (3) in microprocessor mode table 1.3.6 examples of handling unused pins in microprocess or mode handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins open aft er they are set to the output mode ( notes 1 and 2 ). leave this pin open. ( note 5 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputers pins). 3: this is applied when h level is input to pin byte. 4: this is applied when h level is input to pin byte and the accessible area has a capacity of 64 kbytes. 5: when vss level is applied to pin cnvss, note the following: this pin functions as an input port from reset until the processor mode is switched to the microproce ssor mode by software. therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: this is applied when an external clock is input to pin x in . pins p4 3 Cp4 7 , p5Cp8 ____ bhe ( note 3 ) ale ( note 4 ) _____ hlda , f 1 x out ( note 6 ) _____ ____ hold , rdy avcc avss, v ref p4 3 Cp4 7 , p5Cp8 avss v ref hold rdy left open m37733mhbxxxfp hlda vcc vss avcc x out n when setting ports to input mode left open p4 3 Cp4 7 , p5Cp8 avss v ref left open vss avcc x out n when setting ports to output mode left open left open vcc m37733mhbxxxfp bhe ale hold rdy bhe ale hlda f 1 f 1 fig. 1.3.3 examples of handling unused pins in microprocesso r mode
overview 7733 group users manual 1-11 1.4 block diagram figure 1.4.1 shows the m37733mhbxxxfp block diagram. fig.1.4.1 m37733mhbxxxfp block diagram 1.4 block diagram
overview 1-12 7733 group users manual memo 1.4 block diagram
chapter 2 chapter 2 central processing unit (cpu) 2.1 central processing unit 2.2 bus interface unit 2.3 accessible area 2.4 memory allocation 2.5 processor modes
central processing unit (cpu) 7733 group users manual 2C2 2.1 central processing unit the cpu of the 7733 group has ten registers as shown in figure 2.1.1. each of these registers is described below. fig. 2.1.1 cpu registers structure b0 b7 b8 b15 a h a l b0 b7 b8 b15 b h b l b0 b7 b8 b15 x h x l b0 b7 b8 b15 y h y l b0 b7 b8 b15 s h s l b0 b7 b8 b15 b7 b0 b8 b23 b16 b15 b7 b0 pc h pc l pg b0 b7 dt b0 b7 b8 b15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b10 00000 c z i d x m v n ipl accumulator a (a) accumulator b (b) index register x (x) index register y (y) stack pointer (s) data bank register (dt) program counter (pc) program bank register (pg) direct page register (dpr) processor status register (ps) processor interrupt priority level carry flag zero flag interrupt disable flag index register length flag decimal mode flag data length flag overflow flag negative flag dpr l dpr h ps l ps h b9 b15 2.1 central processing unit
central processing unit (cpu) 7733 group users manual 2C3 2.1.1 accumulator (acc) accumulators a and b are available. (1) accumulator a (a) data processing such as calculation, data transfer, or data input/output is executed mainly through accumulator a. it consists of 16 bits and its low-order 8 bits can also be used separately. the data length flag (m), which is a part of the processor status register, specifies whether accumulator a is used as a 16-bit register or an 8-bit register. when the data length is 8 bits wide, only the low-order 8 bits of accumulator a are used and the contents of the high-order 8 bits is unchanged. (2) accumulator b (b) accumulator b has the same function as accumulator a and can be used instead of accumulator a. note that, except for some instructions, the use of accumulator b requires more instruction bytes and execution cycles than that of accumulator a. accumulator b consists of 16 bits and is also affected by the data length flag (m) just as for accumulator a. 2.1.2 index register x (x) index register x consists of 16 bits and its low-order 8 bits can also be used separately. the index register length flag (x), which is a part of the processor status register, specifies whether index register x is used as a 16-bit register or an 8-bit register. when the index register length is 8 bits wide, only the low-order 8 bits of index register x are used and the contents of the high-order 8 bits is unchanged. in an addressing mode where index register x is used as an index register, the address obtained by adding the contents of index register x to the operand is accessed. in execution of a block transfer instruction (mvp or mvn) , the contents of index register x is the low-order 16 bits of the source address and the third byte of the instruction is the high-order 8 bits of the address. h refer to 7700 family software manual for addressing modes. 2.1.3 index register y (y) index register y has the same function as index register x. index register y consists of 16 bits and is also affected by the index register length flag (x) just as for index register x. in execution of a block transfer instruction (mvp or mvn) , the contents of index register y is the low-order 16 bits of the destination address and the second byte of the instruction is the high-order 8 bits of the address. 2.1 central processing unit
central processing unit (cpu) 7733 group users manual 2C4 2.1.4 stack pointer (s) the stack pointer (s) consists of 16 bits and is used for an interrupt, a subroutine call, or execution of an addressing mode where a stack is used. the contents of s indicates a store address for a register and so on during an interrupt or a subroutine call (stack area). the stack area is set in bank 0 16 . (refer to section 2.1.6 program bank register (pg). ) when an interrupt request is accepted, the microcomputer stores the contents of the program bank register (pg) into an address indicated by the contents of s and decrements the contents of s by 1. then the microcomputer stores the contents of the program counter (pc) and the processor status register (ps). after acceptance of an interrupt request, the contents of s becomes [s] C 5. ([s] is the initial address that the stack pointer (s) indicates when an interrupt request is accepted.) (refer to figure 2.1.2. ) after processing in an interrupt routine is finished, processing for return to the original routine is performed as follows. when the rti instruction is executed, the contents of registers which were stored in the stack area are restored into the original registers. (the contents are restored ps, pc, and pg in that order.) the contents of s is also returned to the state before acceptance of an interrupt request. during a subroutine call, the same processing as for an interrupt is performed. the contents of ps, however, are not automatically stored. (the contents of pg may not be stored. this depends on the addressing mode.) during an interrupt or a subroutine call, registers other than the above registers are not automatically stored. therefore, be sure to store necessary registers by software. the contents of s is undefined at reset. therefore, be sure to initialize s at the start of a program. furthermore, a stack area changes according to subroutines nesting or acceptance of multiple interrupts requests. therefore, give careful consideration to subroutines nesting depth not to destroy the necessary data. h refer to 7700 family software manual for addressing modes. fig. 2.1.2 stored registers in stack area h [s] is the initial address that the stack pointer (s) indicates when an interrupt request is accepted. s? contents is ?s] ?5?after all of the above registers are pushed. address [s] ?4 [s] ?3 [s] ?2 [s] ?1 [s] processor status register? low-order byte (ps l ) stack area [s] ?5 processor status register? high-order byte (ps h ) program counter? low-order byte (pc l ) program counter? high-order byte (pc h ) program bank register (pg) 2.1 central processing unit
central processing unit (cpu) 7733 group users manual 2C5 2.1.5 program counter (pc) the program counter consists of 16 bits. this counter indicates the low-order 16 bits of a store address, which consists of 24 bits, of an instruction to be executed next, in other words an instruction which is read from an instruction queue buffer. at reset, value ff 16 is set to the high-order byte (pc h ) of the program counter and value fe 16 is set to the low-order byte (pc l ) of the counter. and then, immediately after reset, the contents of the resets vector addresses (addresses fffe 16 , ffff 16 ) are set to the counter. figure 2.1.3 shows the program counter and the program bank register. fig. 2.1.3 program counter and program bank register 2.1.6 program bank register (pg) the program bank register consists of 8 bits. (refer to figure 2.1.3. ) this register indicates the high-order 8 bits of a store address, which consists of 24 bits, of an instruction to be executed next, in other words an instruction which is read from an instruction queue buffer. these 8 bits indicate bank. the contents of the program bank register is automatically incremented by 1 when a carry occurs in the following cases: ?when a certain value is added to the contents of the program counter ?when the displacement is added to the program counter by executing a branch instruction and others the contents of the program bank register is automatically decremented by 1 when a borrow occurs in the following case: ?when a certain value is subtracted from the contents of the program counter therefore, when normally programming, it is not necessary to give consideration to bank boundaries. at reset, this register is cleared to 00 16. pc h pc l b7 b0 b15 b8 b7 b0 (b16) pg (b23) 2.1 central processing unit
central processing unit (cpu) 7733 group users manual 2C6 2.1.7 data bank register (dt) the data bank register consists of 8 bits. in an addressing mode where the data bank register is used, the contents of this register is processed as the high-order 8 bits (bank) of an address to be accessed, which consists of 24 bits. when setting a certain value to this register, execute the ldt instruction. at reset, this register is cleared to 00 16. h addressing modes where the data bank register is used are listed below: direct ? indirect direct ? indexed x ? indirect direct ? indirect ? indexed y absolute absolute ? bit absolute ? indexed x absolute ? indexed y absolute ? bit ? relative stack pointer ? relative ? indirect ? indexed y 2.1.8 direct page register (dpr) the direct page register consists of 16 bits. the contents of this register specifies a direct page area to bank 0 16 or an area which extends banks 0 16 and 1 16 . the direct page area can be accessed with two bytes ( note ) by using the direct page addressing mode. the contents of the direct page register indicates the base address (the lowest address) of a direct page area which is extended to 256 bytes above this address. values from 0000 16 to ffff 16 can be set to the direct page register. when a certain value equal to or more than ff01 16 is set to the direct page register, the direct page area is specified to an area which extends banks 0 16 and 1 16 . when the contents of low-order 8 bits of the direct page register is cleared to 00 16 , the number of cycles required to generate the address to be accessed is decremented by 1. therefore, efficient access is possible. at reset, this register is cleared to 0000 16. figure 2.1.4 shows a setting example of direct page areas. note: for the div and mpy instructions, the direct page area is accessed with 3 bytes. when accumulator b is used, for each instruction, the number of instruction bytes is incremented by 1. h addressing modes where the direct page register is used are listed below: direct direct ? bit direct ? indexed x direct ? indexed y direct ? indirect direct ? indexed x ? indirect direct ? indirect ? indexed y direct ? indirect long direct ? indirect long ? indexed y direct ? bit ? relative 2.1 central processing unit
central processing unit (cpu) 7733 group users manual 2C7 fig. 2.1.4 setting example of direct page area aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa a a a a a a bank 0 16 bank 1 16 0 16 ff 16 222 16 when dpr = 0000 16 when dpr = 0123 16 123 16 ff10 16 1000f 16 notes 1: 2: when the low-order 8 bits of dpr = ?0 16 ,?the number of cycles required to generate the address to be accessed is decremented by 1. when dpr = ?f01 16 ?or more, the direct page area is specified to the area which extends banks 0 16 and 1 16 . 0 16 ffff 16 10000 16 when dpr = ff10 16 2.1 central processing unit
central processing unit (cpu) 7733 group users manual 2.1 central processing unit 2C8 2.1.9 processor status register (ps) the processor status register consists of 11 bits. figure 2.1.5 shows the structure of the processor status register. b15 b8 b7 b0 b1 b2 b3 b4 b5 b6 b14 b9 b10 b11 b12 b13 processor status register (ps) 0nc z i d x m v 0 ipl 0 0 0 note: ??is always read from bits 11 to 15. fig. 2.1.5 structure of processor status register (1) bit 0: carry flag (c) this flag retains a carry or borrow which occur in the arithmetic logic unit (alu) during an arithmetic or logic operation. this flag is also affected by a shift or rotate instruction. when the bcc or bcs instruction is executed, the program branches according to this flags state. when setting this flag to 1, execute the sec or sep instruction; when clearing this flag to 0, execute the clc or clp instruction. (2) bit 1: zero flag (z) this flag is set to 1 when the result of an arithmetic operation or data transfer is 0 and cleared to 0 when otherwise. when the bne or beq instruction is executed, the program branches according to this flags state. this flag is ignored for an addition and subtraction instructions (the adc and the sbc instructions) in the decimal mode. when setting this flag to 1, execute the sep instruction; when clearing this flag to 0, execute the clp instruction. (3) bit 2: interrupt disable flag (i) this flag disables all maskable interrupts, in other words interrupts other than watchdog timer, the brk instruction, and zero division interrupts. interrupts are disabled when this flag is 1. when an interrupt request is accepted, this flag is automatically set to 1 and disables multiple interrupts. when setting this flag to 1, execute the sei or sep instruction; when clearing this flag to 0, execute the cli or clp instruction. at reset, this flag is set to 1. (4) bit 3: decimal mode flag (d) this flag determines whether addition and subtraction are performed in binary or decimal. binary arithmetic is performed when this flag is 0. when it is 1, decimal arithmetic is performed. at this time, each word is processed as 2- or 4-digit decimal data. (the digits number is determined by the data length flag (m)). decimal adjust is automatically performed. (note that a decimal operation is enabled only in execution of the adc or sbc instruction.) when setting this flag to 1, execute the sep instruction; when clearing this flag to 0, execute the clp instruction. at reset, this flag is cleared to 0.
central processing unit (cpu) 7733 group users manual 2C9 (5) bit 4: index register length flag (x) this flag determines whether index register x or index register y is used as a 16-bit register or an 8-bit register. the register is used as a 16-bit register when this flag is 0 and as an 8-bit register when this flag is 1. when setting this flag to 1, execute the sep instruction; when clearing this flag to 0, execute the clp instruction. at reset, this flag is cleared to 0. note: when data is transferred between registers which are different in bit length, the data is transferred with the bit length of the destination register. but this is not applied to the case where the txa , tya , txb , or tyb instruction is executed. refer to 7700 family software manual for details. (6) bit 5: data length flag (m) this flag determines whether data is used as 16-bit data or 8-bit data. data is used as 16-bit data when this flag is 0 and as 8-bit data when this flag is 1. when setting this flag to 1, execute the sem or sep instruction; when clearing this flag to 0, execute the clm or clp instruction. at reset, this flag is cleared to 0. note: when data is transferred between registers which are different in bit length, the data is transferred with the data length of the destination register. but this is not applied to the case where the txa , tya , txb , or tyb instruction is executed. refer to 7700 family software manual for details. (7) bit 6: overflow flag (v) this flag is valid when addition or subtraction is executed for each word which is processed as signed binary data. if the data length flag (m) is 0, the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between C32768 and +32767 and cleared to 0 in the other cases. if the data length flag (m) is 1, the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between C128 and +127 and cleared to 0 in the other cases. also, the overflow flag is set to 1 when the length of the division result obtained by the div instruction is longer than that of a register where the result is to be stored. when the bvc or bvs instruction is executed, the program branches according to this flags state. this flag is ignored in the decimal mode. when setting this flag to 1, execute the sep instruction; when clearing this flag to 0, execute the clv or clp instruction. (8) bit 7: negative flag (n) this flag is set to 1 when the result of an arithmetic operation or data transfer is negative. (bit 15 of the result is 1 when the data length flag (m) is 0, or bit 7 of the result is 1 when the data length flag (m) is 1.) it is cleared to 0 in the other cases. when the bpl or bmi instruction is executed, the program branches according to this flags state. this flag is ignored in the decimal mode. when setting this flag to 1, execute the sep instruction; when clearing this flag to 0, execute the clp instruction. (9) bits 8 to 10: processor interrupt priority level (ipl) these bits can specify one of levels 0 to 7 as the processor interrupt priority level. an interrupt is enabled when its interrupt priority level, which is set in the interrupt control register, is higher than ipl. when the interrupt request is accepted, the contents of ipl is stored into the stack area and the interrupt priority level of the accepted interrupt is set in ipl. no instruction can directly set or clear each of these bits. when changing these bits, store a desired processor interrupt priority level into the stack area. and then, change the contents of the processor status register by executing the pul or plp instruction. at reset, the contents of ipl is cleared to 000 2. 2.1 central processing unit
central processing unit (cpu) 7733 group users manual 2C10 2.2 bus interface unit the microcomputer has a bus interface unit (biu) between the central processing unit (cpu) and memory ? i/o unit. the bius function and operation are described below. when connecting external devices, refer to chapter 12. connecting external devices, also. 2.2.1 overview transfer operation between the cpu and memory ? i/o unit is always performed via the biu. the biu reads an instruction from the memory before the cpu executes it. when the cpu reads data from the memory ? /o unit, the cpu informs the biu of the address where the data resides. the biu reads the data from the address and pass it to the cpu. a when the cpu writes data to the memory ? i/o unit, the cpu informs the biu of the address where the data resides. the biu writes the data to the address. ? in order to realize operations to a , the biu inputs and outputs bus control signals and controls the buses. figure 2.2.1 shows the buses and bus interface unit (biu). 2.2 bus interface unit
central processing unit (cpu) 7733 group users manual 2C11 2.2 bus interface unit fig. 2.2.1 buses and bus interface unit (biu) m37733mhbxxxfp internal bus d 15 to d 8 central processing unit (cpu) sfr : special function register notes 1: cpu bus, internal bus, and external bus are independent of each other. 2: for details about signals on the external buses, refer to ch apter 12. connecting external devices. internal bus a 23 to a 0 external devices internal control signals cpu bus internal bus internal bus d 7 to d 0 internal memory internal peripheral devices (sfr) external bus a 7 to a 0 a 15 / d 15 to a 8 / d 8 a 23 / d 7 to a 16 / d 0 control signals bus interface unit (biu) bus conversion circuit
central processing unit (cpu) 7733 group users manual 2C12 2.2.2 functions of bus interface unit (biu) the bus interface unit (biu) consists of four registers shown in figure 2.2.2. table 2.2.1 lists each registers function. 2.2 bus interface unit table 2.2.1 each registers function fig. 2.2.2 registers structure of which bus interface unit (biu) consists name program address register instruction queue buffer data address register data buffer functions indicates a store address for an instruction which is next fetched into an instruction queue buffer. temporarily stores an instruction which was fetched. indicates an address for data which is next read or written. temporarily stores data which was read from the memory ? i/o unit by the biu or which is to be written to the memory ? i/o unit by the cpu. pa b23 b0 q 0 b7 b0 q 1 q 2 da b23 b0 db l b0 db h b15 program address register instruction queue buffer data address register data buffer
central processing unit (cpu) 7733 group users manual 2C13 the cpu and buses operate on the basis of different signals ( note ). between the cpu and buses, therefore, data is passed or received via the biu. owing to the bius operation, the cpu can operate at high speed without waiting for the access by the low-speed memory ? i/o unit. when an external device is connected, it is necessary to secure an access time according to the external devices timing specifications. in this case, in order to secure an access time, the biu extends the duration of signals required for the access. note: the cpu operates on the basis of f cpu . the period of f cpu is normally the same as that of f . __ the internal buses operate on the basis of e. the period of e is at least twice that of f . the bius functions are described below. (1) reading out instruction (instruction prefetch) when the cpu does not request to read or write data, that is, when buses are not in use, the biu reads instructions from the memory and stores them in an instruction queue buffer. this is called instruction prefetch. the cpu reads instructions from the instruction queue buffer and executes them. therefore, the cpu can operate at high speed without waiting for the access by the low-speed memory. when the instruction queue buffer becomes empty or stores only 1 byte of an instruction, the biu prefetches a new instruction code. the instruction queue buffer can store instructions up to 3 bytes. the contents of the instruction queue buffer is initialized when a branch or jump instruction is executed and the biu reads a new instruction code from the destination address. if instructions in the instruction queue buffer are insufficient for the cpus request, the biu extends the l-level duration of clock f cpu in order to keep the cpu waiting until the biu fetches the requested number of instructions or more. (2) writing data to memory ? i/o the cpu informs the bius data address register of an address to which data is written and writes the data to the data buffer. the biu outputs the address received from the cpu to the address bus and writes the data in the data buffer to the specified address. while the biu is writing data to the specified address, the cpu advances to the next process without waiting for completion of bius write operation. note that while the biu uses buses for instruction prefetch, the biu keeps the cpu waiting even when the cpu requests to write data. (3) signal input/output for access to external device when accessing external devices, the biu inputs and outputs signals required for the access. (for details, refer to chapter 12. connecting external devices. ) 2.2 bus interface unit
central processing unit (cpu) 7733 group users manual 2C14 2.2.3 operation of bus interface unit (biu) figure 2.2.3 shows the basic operating waveforms of the bus interface unit (biu). when accessing external devices, some signals which are input or output to or from the external are required. for details about these signals, refer to chapter 12. connecting external devices. (1) when fetching an instruction into an instruction queue buffer when an instruction which is next fetched resides at an even address the biu fetches two bytes of the instruction with waveform (a). note that when an external device which is connected by an 8-bit external data bus (byte = h) is accessed, only one byte of the instruction is fetched. when an instruction which is next fetched resides at an odd address the biu fetches only one byte of the instruction with waveform (a). the contents at an even address is not fetched into an instruction queue buffer. (2) when reading or writing data from or to memory ? i/o when accessing 16-bit data which starts from an even address, waveform (a) is applied. the 16- bit data is accessed at a time. when accessing 16-bit data which starts from an odd address, waveform (b) is applied. the 16-bit data is accessed by the 8 bits. invalid data is not fetched into a data buffer. a when accessing 8-bit data at an even address, waveform (a) is applied. data at an odd address is not fetched into a data buffer. ? when accessing 8-bit data at an odd address, waveform (a) is applied. data at an even address is not fetched into a data buffer. for instructions which are affected by the data length flag (m) or index register length flag (x), an operation is applied as follows: ? when m or x = 0, operation or is applied. ? when m or x = 1, operation a or ? is applied. 2.2 bus interface unit
central processing unit (cpu) 7733 group users manual 2C15 e (a) (b) address internal address bus (a 0 to a 23 ) data (even address) internal data bus (d 0 to d 7 ) data (odd address) internal data bus (d 8 to d 15 ) e address (odd address) address (even address) data (even address) data (odd address) invalid data invalid data internal address bus (a 0 to a 23 ) internal data bus (d 0 to d 7 ) internal data bus (d 8 to d 15 ) fig. 2.2.3 basic operating waveforms of bus interface unit (biu) 2.2 bus interface unit
central processing unit (cpu) 7733 group users manual 2C16 2.3 accessible area figure 2.3.1 shows the m37733mhbxxxfps accessible area. although the program counter (pc) consists of 16 bits, it can access the 16-mbyte area at addresses 0 16 to ffffff 16 , combined with the program bank register (pg). for details about access to the external, refer to chapter 12. connecting external devices. the memories and i/o units are allocated in the same accessible area. therefore, operations such as data transfer, arithmetic, and others can be performed with the same instructions. (it is not necessary to distinguish the memories and i/o units.) fig. 2.3.1 m37733mhbxxxfps accessible area 000000 16 000080 16 00ffff 16 010000 16 fe0000 16 ff0000 16 ffffff 16 001000 16 020000 16 000fff 16 00007f 16 ? sfr : special function register represents the memory allocation of internal areas. indicates that nothing is allocated. note: memory allocation of the internal area in bank 0 16 depends on the microcomputers type and settings of the memory allocation selection bits. the above diagram shows the m37733mhbxxxfps accessible area immediately after reset. for the other microcomputers of the 7733 group, refer to section appendix 1. memory allocation of 7733 group. for settings of the memory allocation selection bits, refer to section 2.4 memory allocation . sfr area internal ram area bank 0 16 internal rom area bank 1 16 bank ff 16 bank fe 16 01ffff 16 2.3 accessible area
central processing unit (cpu) 7733 group users manual 2C17 2.3.1 banks the accessible area is divided by the 64 kbytes. this 64-kbyte area is called bank. the high-order 8 bits of an address, which consists of 24 bits, indicate the bank. a bank is specified by the program bank register (pg) or data bank register (dt). each bank can be accessed efficiently by using an addressing mode where the data bank register (dt) is used. at each banks boundary, when an overflow occurs in the program counter (pc), the contents of the program bank register (pg) is incremented by 1; when a borrow occurs in the program counter (pc), the contents of the program bank register (pg) is decremented by 1. accordingly, when normally programming, it is not necessary to give consideration to bank boundaries. 2.3.2 direct page a 256-byte area specified by the direct page register (dpr) is called direct page. when setting a direct page, set the base address (the lowest address) of an area which is to be specified as a direct page to the direct page register (dpr). (refer to section 2.1.8 direct page register (dpr). ) by using a direct page addressing mode, a direct page can be accessed with less instruction cycles. 2.3 accessible area
central processing unit (cpu) 7733 group users manual 2C18 2.4 memory allocation 2.4 memory allocation the internal areas memory allocation is described below. for the external area, refer to section 2.5 processor modes. 2.4.1 memory allocation in internal area sfr (special function register), internal ram, and internal rom are allocated in the internal area. (1) sfr (special function register) area registers required for setting internal peripheral devices are allocated to addresses 0 16 to 7f 16 . this area is called sfr (special function register) area. figure 2.4.4 shows the sfr areas memory map. for each register in the sfr area, refer to the corresponding functional description. for the state of the sfr area immediately after reset, refer to section 13.1.2 state of cpu, sfr area and internal ram area. (2) internal ram area in the m37733mhbxxxfp, a 3968-byte static ram is allocated to addresses 80 16 to fff 16 ( note ). the internal ram area is used as a data store area and as a stack area. therefore, it is necessary to give careful consideration to nesting levels in subroutines and multiple interrupts levels not to destroy necessary data. (3) internal rom area in the m37733mhbxxxfp, a 124-kbyte mask rom is allocated to addresses 1000 16 to 1ffff 16 immediately after reset ( note ). the internal roms size and area can be changed by the memory allocation selection bits (bits 0 to 2 at address 63 16 ). figure 2.4.1 shows the structure of the memory allocation control register and its setting method. figures 2.4.2 and 2.4.3 show the m37733mhbxxxfps memory map. (refer to section appendix 9. q & a. ) vector addresses for reset and interrupts (interrupt vector table) are allocated to addresses ffd6 16 to ffff 16 in the internal rom. in the microprocessor mode, where the internal rom area is inhibited from use, the rom must be allocated to addresses ffd6 16 to ffff 16 . note : for the other microcomputers of the 7733 group, refer to section appendix 1. memory allocation of 7733 group .
central processing unit (cpu) 7733 group users manual 2C19 2.4 memory allocation fig. 2.4.1 structure of memory allocation control register and its setting method rom size rom size 3 4 7 to 5 0 0 not implemented. notes 1: the case where value ?5 16 ?is written in of the procedure listed below is not included. 2: when changing these bits, this change must be performed in an area which is internal rom area before and after this change, for example addresses 00c000 16 to 00ffff 16 . also, when changing these bits, be sure to follow the procedure listed below. 3: this figure is applied only to the m37733mhbxxxfp. for the other microcoputers, please refer to the latest datasheets on the english document cd-rom or our web site. bit bit name functions at reset rw 0 1 2 memory allocation selection bits (notes 1 and 2) 0 0 0 0: 124 kbytes, 3968 bytes 0 0 1: 120 kbytes, 3968 bytes 0 1 0: 60 kbytes, 2048 bytes 0 1 1: do not select. 1 0 0: 32 kbytes, 2048 bytes 1 0 1: 16 kbytes, 2048 bytes 1 1 0: 96 kbytes, 3968 bytes 1 1 1: do not select. 0 0 b2b1b0 memory allocation control register (address 63 16 ) (note 3) b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw rw 0 rw un- defined | note: when changing bits 2 to 0, be sure to follow this procedure. procedure by using the ldm instruction, write value ?5 16 ?to address 63 16 . (by this, writing to the memory allocation selection bits is enabled.) by using the ldm instruction, write value ?0000xxx 2 ?to address 63 16 . (values of b2, b1, and b0 shown in the above figure) writing is performed by the next instruction. must be fixed to ?.? (note 1)
central processing unit (cpu) 7733 group users manual 2C20 fig. 2.4.2 m37733mhbxxxfps memory map (1) 01ffff 16 ff0000 16 sfr area internal ram area 3968 bytes 000000 16 00007f 16 000080 16 000fff 16 ffffff 16 bank 0 16 bank 1 16 bank ff 16 internal rom area 60 kbytes internal rom area 64 kbytes 001000 16 00ffff 16 010000 16 bank 2 16 002000 16 000000 16 00007f 16 000080 16 000fff 16 (4 kbytes) 00ffff 16 010000 16 01ffff 16 ffffff 16 000000 16 00007f 16 a-d/uart2 trans./rece. uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide reset 00ffd6 16 00fffe 16 interrupt vector table sfr area internal ram area 3968 bytes internal rom area 56 kbytes internal rom area 64k bytes peripheral device control registers (sfr) ?memory allocation selection bits (b2, b1, b0)=(0, 0, 0) ?rom size: 124 kbytes ?ram size: 3.9 kbytes ?memory allocation selection bits (b2, b1, b0)=(0, 0, 1) ?rom size: 120 kbytes ?ram size: 3.9 kbytes uart1 transmission uart0 transmission : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: banks 10 16 to ff 16 cannot be accessed in the 7735 group and in external bus mode b of the 7736 group. (refer to section ?ppendix 1 in part 2. ) refer to appendix 2. 02ffff 16 020000 16 2.4 memory allocation
central processing unit (cpu) 7733 group users manual 2C21 2.4 memory allocation fig. 2.4.3 m37733mhbxxxfps memory map (2) 00ffff 16 010000 16 uart1 transmission 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 001000 16 000000 16 00007f 16 000080 16 00087f 16 00ffff 16 010000 16 ffffff 16 000000 16 reset 00007f 16 00ffd6 16 00fffe 16 a-d/uart2 trans./rece. 020000 16 008000 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 60 kbytes bank 2 16 (29.9 kbytes) uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide interrupt vector table sfr area internal ram area 2048 bytes peripheral device control registers (sfr) : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode ?memory allocation selection bits (b2, b1, b0)=(0, 1, 0) ?rom size: 60 kbytes ?ram size: 2048 bytes ?memory allocation selection bits (b2, b1, b0)=(1, 0, 0) ?rom size: 32 kbytes ?ram size: 2048 bytes (1.9 kbytes) uart0 transmission refer to appendix 2. 02ffff 16 notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: banks 10 16 to ff 16 cannot be accessed in the 7735 group and in external bus mode b of the 7736 group. internal rom area 32 kbytes
central processing unit (cpu) 7733 group users manual 2C22 fig. 2.4.4 m37733mhbxxxfps memory map (3) 2.4 memory allocation 00ffff 16 010000 16 020000 16 uart1 transmission 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 00c000 16 000000 16 00007f 16 000080 16 000fff 16 00ffff 16 010000 16 ffffff 16 000000 16 reset 00007f 16 00ffd6 16 00fffe 16 a-d/uart2 trans./rece. 008000 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 16 kbytes bank 2 16 (28 kbytes) uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide interrupt vector table sfr area internal ram area 3968 bytes peripheral device control registers (sfr) : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode ?memory allocation selection bits (b2, b1, b0)=(1, 0, 1) ?rom size: 16 kbytes ?ram size: 2048 bytes ?memory allocation selection bits (b2, b1, b0)=(1, 1, 0) ?rom size: 96 kbytes ?ram size: 3968 bytes (45.9 kbytes) uart0 transmission refer to appendix 2. 02ffff 16 notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: banks 10 16 to ff 16 cannot be accessed in the 7735 group and in external bus mode b of the 7736 group. internal rom area 32 kbytes 001000 16 internal rom area 64 kbytes 01ffff 16
central processing unit (cpu) 7733 group user s manual 2 C 23 2.4 memory allocation fig. 2.4.5 sfr area s memory map uart 0 transmission interrupt control register uart 1 transmission interrupt control register int 2 /key input interrupt control register port p1 direction register uart 0 transmit/receive mode register uart 0 baud rate register (brg0) uart 0 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 0 transmission buffer register uart 1 transmit/receive control register 0 uart 1 transmit/receive mode register uart 1 baud rate register (brg1) uart 1 transmit/receive control register 1 uart 0 receive buffer register uart 1 transmission buffer register uart 1 receive buffer register port p0 register a-d register 0 a-d register 2 port p1 register port p0 direction register port p2 register port p3 register port p4 register port p5 register port p6 register port p7 register port p8 register a-d control register 0 a-d control register 1 a-d register 1 a-d register 3 a-d register 4 a-d register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002a 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 00000b 00000c 00000d 00000e 00000f 00000a 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f 00004b 00004c 00004d 00004e 00004f 00004a 000044 address (hexadecimal notation) address (hexadecimal notation) timer a1 register timer a4 register timer a2 register timer a3 register timer b0 register timer b1 register timer b2 register count start flag one-shot start flag up-down flag timer a0 register timer a0 mode register timer a1 mode register timer a2 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 watchdog timer register watchdog timer frequency selection flag a-d/uart2 trans./rece. interrupt control register uart 0 receive interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register processor mode register 1 oscillation circuit control register 1 serial transmit control register port function control register oscillation circuit control register 0 timer a3 mode register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register reserved area (note) a-d register 6 a-d register 7 uart2 transmit/receive mode register uart2 baud rate register (brg2) uart2 transmission buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register reserved area (note) note: writing to reserved area is disabled. reserved area (note) memory allocation control register a-d control register 1
central processing unit (cpu) 7733 group user s manual 2 24 2.5 processor modes the m37733mhbxxxfp can operate in the following three proces sor modes: single-ch ip mode, memory expansion mode, and microprocessor mode. in the m37733mhbxxx fp, some pins funct ions, memory allocation, and accessible area differ according to processo r modes. these diffe rences according to processor modes are described below. figure 2.5.1 shows the memory map in each processor m ode. 2.5 processor modes 000000 16 01ffff 16 000080 16 020000 16 ffffff 16 000fff 16 001000 16 notes 1: represents external memory area. by accessing this area, an external device connected to the m37733mhbxxxfp can be accessed. this is applied when the contents of memory allocation sele ction bits (bits 2 to 0 at address 63 16 ) = 000 2 . for the 7733 group s microcomputers other than the m37733mhb xxxfp, refer to section appendix 1. memory allocation of 7733 group. sfr area internal rom area (note 2) single-chip mode internal ram area sfr area memory expansion mode sfr area microprocessor mode internal ram area internal ram area internal rom area (note 2) fig. 2.5.1 memory map in each processor mode (m37733mhbxxxfp ) 2: 3:
central processing unit (cpu) 7733 group user s manual 2 C 25 2.5.1 single-chip mode when not using an external device, this mode is used. in thi s mode, ports p0 to p8 function as programmable i/o ports. (when using internal peripheral devices, they fun ction as i/o pins.) only the internal area (sfr, internal ram, and internal rom) can be accessed. _ output of e can be stopped by software. (refer to section 12.1 signals required for accessing external devices. ) 2.5.2 memory expansion and microprocessor modes when connecting an external device, these modes are used. in these modes, an external device can be connected to an arbitrary area in the 16-mbyte accessible ar ea. for access to an external device, refer to chapter 12. connecting external devices. the memory expansion and microprocessor modes have the same functions except for the followings: in the microprocessor mode, access to the internal rom area is forcibly disabled. this area is handled as the external area. in the microprocessor mode, port p4 2 functions as a clock f 1 output pin. ( note ) in the memory expansion and microprocessor modes, pins p0 to p3, p4 0 , and p4 1 function as i/o pins for signals required for access to an external device. therefore , these pins cannot be used as programmable i/o ports. if an external device is connected to a certain area which i s allocated to the internal area, when this area is read, data in the internal area is fetched into the centr al processing unit (biu) but data in the external area is not fetched; when data is written to this area, the data is written to the internal area and signals are output to the external at the same timing as writing to the internal area. note : output of clock f 1 can be stopped by software. (for details, refer to section 12.1 signals required for accessing external devices. ) figure 2.5.2 shows the pin configuration in each processor m ode. table 2.5.1 lists the relationship between processor modes and functions of p0 to p4. for each pin s function, refer to section 1.3 pin description, chapters 3. programmable i/o ports to 9. a-d converter and 12. connecting external devices. 2.5 processor modes
central processing unit (cpu) 7733 group user s manual 2 C 26 2.5 processor modes fig. 2.5.2 pin configuration in each processor mode (top vie w) a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 r/w bhe ale hlda v ss e x out x in reset cnv ss byt e hold p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 /d 8 a 9 /d 9 a 10 /d 10 p7 0 /an 0 p6 7 /tb2 in / f sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 14 3 25 p2 4 p2 5 p2 6 p2 7 p3 0 p3 1 p3 2 p3 3 v ss e x out x in reset cnv ss ] 1 byt e ] 1 p4 0 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /t x d 2 p7 4 /an 4 /r x d 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 p1 3 p1 4 p1 5 p1 6 p1 7 p2 0 p2 1 p2 2 p2 3 43 42 41 m37733mhbxxxfp 22 23 24 p4 1 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / f 1 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 p0 1 p0 2 p0 3 p0 4 p0 5 p0 6 p0 7 p1 0 p1 1 p1 2 p7 0 /an 0 p6 7 /tb2 in / f sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 1 4 3 2 5 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /t x d 2 p7 4 /an 4 /r x d 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 43 42 41 m37733mhbxxxfp 22 23 24 rdy p4 7 p4 6 p4 5 p4 4 p4 3 ] 2 p4 2 / f 1 : these pins functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. ] 1 connect this pin to vss in the single-chip mode. ] 2 f 1 in the microprocessor mode : these pins functions in the single-chip mode differ from those in the memory expansion or microprocessor mode.
in the memory expansion mode, this pin functions as a progra mmable i/o port. furthermore, it can be switched to be a clo ck the above table indicates the change of pin functions owing to the switching of the processor mode. for each signal s i/o timing in the memory expantion or micr oprocessor mode, refer to chapters 12. connecting external devices. central processing unit (cpu) 7733 group user s manual 2 27 table 2.5.1 relationship between processor modes and functio ns of p0 to p4 p3 1 p3 2 p3 0 p3 3 p4 7 to p4 3 p4 1 p4 2 p4 0 p0 p1 hlda a 15 to a 8 d(odd) p3 p2 p4 a 7 to a 0 a 15 to a 8 d(odd): data at odd address a 23 to a 16 d(even) d(even): data at even address a 23 to a 16 d d: data ale p rdy hold f 1 ( note 2 ) bhe r/ w p p p p p notes 1: pin p4 2 can also function as a clock f 1 output pin. (refer to chapter 12. connecting external devices. ) f 1 output pin when selected by software. in the microprocessor mode, this pin is affected by the signal output disable sel ection bit (bit 6 at address 6c 16 ). (refer to chapter ) 3: 12. connecting external devices and 15. electrical characteristics. pin name single-chip mode memory expansion and microprocessor modes processor mode n when external data bus is 16 bits wide (byte = l ) n when external data bus is 8 bits wide (byte = h ) n when external data bus is 16 bits wide (byte = l ) n when external data bus is 8 bits wide (byte = h ) p: functions as a programmable i/o port. p: functions as a programmable i/o port. p: functions as a programmable i/o port. p: functions as a programmable i/o port. p: functions as a programmable i/o port. p: functions as a programmable i/o port. ( note 1 ) 2.5 processor modes 2:
central processing unit (cpu) 7733 group user s manual 2 C 28 2.5.3 selection of processor mode a processor mode can be selected by setting a voltage applie d to pin cnv ss and the processor mode bits (bits 1 and 0 at address 5e 16 ). l when v ss level is applied to pin cnv ss after reset, the microcomputer starts operating in the singl e-chip mode. after the microcomputer starts operating, the processor mode can be switched by the process or mode bits. when the contents of the processor mode bits = 01 2 , the memory expansion mode is selected; when the contents of these bits = 10 2 , the microprocessor mode is selected. after the processor mo de bits are set, the processor _ mode is actually switched at the rising edge of signal e . figure 2.5.3 shows the pin function switch timing when the processor mode is switched from the single-c hip mode to the memory expansion or microprocessor mode by setting the processor mode bits. note that, when the processor mode is switched during the program execution, the contents of the i nstruction queue buffer is not initialized. (refer to section appendix 9. q & a. ) l when v cc level is applied to pin cnv ss after reset, the microcomputer starts operating in the micro processor mode. in this case, the microcomputer cannot operate in the other modes. (fix the processor mode b its to 10 2 . ) table 2.5.2 lists the method of selecting the processor mode . figure 2.5.4 shows the structure of the processor mode register 0. p0 7 e external address bus a 7 writing to the processor mode bits programmable i/o port p0 7 note: functions of pins p0 0 to p0 6 , p1 to p3, p4 0 to p4 2 are switched at the timing shown above. function of pin p4 2 is, however, switched only when the processor mode is switc hed to microprocessor mode. fig. 2.5.3 pin function switch timing 2.5 processor modes
represents that bits 2 to 7 are not used for selecting a pro cessor mode. central processing unit (cpu) 7733 group user s manual 2 29 table 2.5.2 method of selecting processor mode 2.5 processor modes processor mode single-chip mode memory expansion mode microprocessor mode pin cnv ss s level v ss (0 v) ( note 1 ) v ss (0 v) ( note 1 ) v ss (0 v) ( note 1 ) v cc (5 v) ( note 2 ) processor mode bits b1 0 0 1 b0 0 1 0 notes 1: the microcomputer starts operating in the single-chip mode after reset. by setting the processor mode bits, the processor mode of the microcomputer can be sw itched from the single-chip mode to the other modes. 2: the microcomputer starts operating in the microprocessor mo de after reset. the microcomputer cannot operate in the other modes. accordingly, so fix the p rocessor mode bits (bits 1 and 0 at address 5e 16 ) to 10 2 . fig. 2.5.4 structure of processor mode register 0 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits wait bit software reset bit must be fixed to 0. clock f 1 output selection bit (note 2) 0 0 0 0 0 0 0 0: single-chip mode 0 1: memory expansion mode 1 0: microprocessor mode 1 1: do not select. 0: software wait is inserted when accessing external area. 1: no software wait is inserted when accessing external area. microcomputer is reset by setting this bit to 1. this bit is 0 at reading. 0 0: 7 cycles of f 0 1: 4 cycles of f 1 0: 2 cycles of f 1 1: do not select. 0: clock f 1 output is disabled. (p4 2 functions as a 1: clock f 1 output is enabled. 2 functions as a clock f 1 output pin.) 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) (note 1) notes 1: when the vcc-level voltage is applied to pin cnvss, this bit is set to 1 after reset. (when read, this bit is always 0. ) 2: this bit is ignored in the microprocessor mode. (it may be 0 or 1. ) 3: b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw wo rw rw rw rw interrupt priority detection time selection bits (port p4 2 programmable i/o port.)
central processing unit (cpu) 7733 group user s manual 2 C 30 [precautions on selecting processor mode] 1. the external rom version can operate only in the micropro cessor mode. therefore, be sure to set as follows: ? connect pin cnvss to vcc. ? fix the processor mode bits (b1, b0) to 10 2 . 2.5 processor modes
chapter 3 chapter 3 programmable i/o ports 3.1 programmable i/o ports 3.2 port peripheral circuits 3.3 pullup function 3.4 internal peripheral devices i/o functions (ports p4 2 and p5 to p8)
7733 group users manual 3C2 programmable i/o ports functions of all ports in the single-chip mode and that of ports p4 3 to p4 7 and p5 to p8 in the memory expansion and the microprocessor modes are described below. for more information about ports p0 to p4, whose functions depend on the processor mode, refer to section 2.5 processor modes and chapter 12. connecting external devices. 3.1 programmable i/o ports the 7733 group has 68 programmable i/o ports (p0 to p8). each of ports p0 to p8 has a port direction register and a port register in the sfr area. each input-only port has a port register in the sfr area. figure 3.1.1 shows the memory map of port direction registers and port registers. note that ports p4 2 and p5 to p8 also function as i/o pins for internal peripheral devices. for details, refer to section 3.4 internal peripheral devices i/o functions and the corresponding functional description. 3.1 programmable i/o ports fig. 3.1.1 memory map of port direction registers and port registers port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p8 direction register 8 16 9 16 a 16 b 16 c 16 d 16 e 16 f 16 10 16 11 16 12 16 13 16 14 16 addresses port p0 register port p1 register port p0 direction register port p1 direction register port p2 register port p3 register port p2 direction register port p3 direction register 2 16 3 16 4 16 5 16 6 16 7 16
7733 group users manual 3C3 programmable i/o ports 3.1.1 port pi direction register this register determines the direction of programmable i/o ports. each bit of this register corresponds to one specified pin. figure 3.1.2 shows the structure of the port pi (i = 0 to 8) direction register. 3.1 programmable i/o ports fig. 3.1.2 structure of port pi (i = 0 to 8) direction register bit bit name functions 0: input mode (the port functions as an input port.) 1: output mode (the port functions as an output port.) port pi direction register (i = 0 to 8) (addresses 4 16 ,5 16 ,8 16 ,9 16 ,c 16 ,d 16 ,10 16 ,11 16 ,14 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw note: writing to bits 4 to 7 of the port p3 direction register is invalid and these bits are fixed to ?? when they are read. 0 port pi 0 direction selection bit 0 rw 1 port pi 1 direction selection bit 0 rw 2 port pi 2 direction selection bit 0 rw 3 port pi 3 direction selection bit 0 rw 4 port pi 4 direction selection bit 0 rw 5 port pi 5 direction selection bit 0 rw 6 port pi 6 direction selection bit 0 rw 7 port pi 7 direction selection bit 0 rw pi 7 b1 b2 b3 b4 b5 b6 b7 bit corresponding pin pi 6 pi 5 pi 4 pi 3 pi 2 pi 1 pi 0 b0
7733 group users manual 3C4 programmable i/o ports 3.1.2 port pi register data is input from or output to an external device by writing/reading data to/from a port register. a port register consists of a port latch, which holds the output data, and a circuit, which reads the pin state. each bit of the port register corresponds to one specified pin. figure 3.1.3 shows the structure of the port pi (i = 0 to 8) register. (1) how to output data from programmable i/o port set the corresponding bit of the port direction register to the output mode. write data to the corresponding bit of the port register, and then the data is written into the port latch. a data set in the port latch is output. when a bit of a port register which corresponds to a port set for the output mode is read out, the contents of the port latch, instead of pin state, is read out. accordingly, output data can correctly be read out without influence of external load, etc. (refer to figures 3.2.1 and 3.2.2 ) (2) how to input data from programmable i/o port set the corresponding bit of the port direction register to the input mode. the pin enters a floating state. a when reading the corresponding bit of the port register in state , data input from the pin can be read in. when data is written to a port register which corresponds to a port set for the input mode, the data is written only into the port latch and not output to the external devices. pins retain a floating state. 3.1 programmable i/o ports
7733 group users manual 3C5 programmable i/o ports 3.1 programmable i/o ports fig. 3.1.3 structure of port pi (i = 0 to 8) register data is input from or output to a pin by reading from or writing to the corresponding bit. port pi register (i = 0 to 8) (addresses 2 16 ,3 16 ,6 16 ,7 16 ,a 16 ,b 16 ,e 16 ,f 16 ,12 16 ) b1 b0 b2 b3 b4 b5 b6 b7 note: writing to bits 4 to 7 of the port p3 register is invalid and these bits are fixed to ??when they are read. 0: ??level 1: ??level 7 port pi 7 ? pin undefined rw bit bit name functions at reset rw 0 port pi 0 ? pin rw undefined 1 port pi 1 ? pin rw undefined 2 port pi 2 ? pin rw undefined 3 port pi 3 ? pin rw undefined 4 port pi 4 ? pin rw undefined 5 port pi 5 ? pin rw undefined 6 port pi 6 ? pin rw undefined
7733 group user? manual 3? programmable i/o ports 3.2 port peripheral circuits figures 3.2.1 and 3.2.2 show the port peripheral circuits. 3.2 port peripheral circuits fig. 3.2.1 port peripheral circuits (1) ?ports p5 5 /ta2 in /ki 1 , p5 7 /ta3 in /ki 3 , p6 2 /int 0 to p6 4 /int 2 data bus pull-up selection pull-up transistor ?ports p5 4 /ta2 out /ki 0, p5 6 /ta3 out /ki 2 ? output ports p5 0 /ta0 out , p5 2 /ta1 out , p6 0 /ta4 out , p7 5 /an 5 /ad trg /txd 2 , p8 2 /rxd 0 /clks 0 (inside dotted-line included, and shaded area not included) ?ports p8 3 /txd 0 , p8 7 /txd 1 (inside dotted-line not included, and shaded area included) notes 1: valid only when used as pin txdj for serial i/o. 2: analog input is present only in port p7 5 . n-channel open-drain selection (note 1) analog input (note 2) port p4 2 / 1 (inside dotted-line not included, and shaded area not inclu ded) ?ports p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7, p3 0 to p3 3 , p4 3 to p4 6 (inside dotted-line not included) ports p4 0 /hold, p4 1 /rdy, p4 7 , p5 1 /ta0 in , p5 3 /ta1 in , p6 1 /ta4 in , p6 5 /tb0 in to p6 7 /tb2 in / f sub , p8 6 /rxd 1 (inside dotted-line included) data bus data bus data bus port latch pull-up selection output pull-up transistor ? port direction register port latch port direction register port latch port direction register port latch port direction register
7733 group users manual 3C7 programmable i/o ports fig. 3.2.2 port peripheral circuits (2) 3.2 port peripheral circuits ?e ?ports p7 3 /an 3 /clk 2, p8 0 /cts 0 /rts 0 /clks 1 , p8 1 /clk 0 , p8 4 /cts 1 /rts 1 , p8 5 /clk 1 data bus aa aa output ? (note 2) analog input ?ports p7 0 /an 0 , p7 1 /an 1 , p7 6 /an 6 /x cout , p7 7 /an 7 /x cin (inside dotted-line not included) ports p7 2 /an 2 /cts 2 , p7 4 /an 4 /rxd 2 (inside dotted-line included) analog input (note 1) sub-clock oscillation circuit note 1: the sub-clock oscillation circuit is present only in ports p7 6 and p7 7 note 2: analog input is present only in port p7 3 ? data bus port latch port direction register port latch port direction register
7733 group users manual 3C8 programmable i/o ports 3.3 pull-up function ___ ___ 3.3.1 pull-up function for ports p5 4 to p5 7 ( ki 0 to ki 3 ) ___ ___ ports p5 4 to p5 7 ( ki 0 to ki 3 ) can be pulled high by setting the port p5 pull-up selection bit (bit 6 at address 6d 16 ). figure 3.3.1 shows the structure of the port function control register. when pulling ports p5 4 to p5 7 high, clear bits 4 to 7 at address d 16 (port p5 direction register) to 0. ____ ____ 3.3.2 pull-up function for ports p6 2 to p6 4 ( int 0 to int 2 ) ____ ____ ports p6 2 and p6 3 ( int 0 and int 1 ) can be pulled high by setting the port p6 pull-up selection bit 0 (bit 3 ____ at address 6d 16 ). port p6 4 ( int 2 ) can be pulled high by setting the port p6 pull-up selection bit 1 (bit 5 at address 6d 16 ). figure 3.3.1 shows the structure of the port function control register. when pulling ports p6 2 to p6 4 high, clear bits 2 to 4 at address 10 16 (port p6 direction register) to 0. 3.3 pull-up function
7733 group user? manual 3? programmable i/o por ts 3.3 pull-up function fig. 3.3.1 structure of port function control register bit functions b7 b6 b5 b4 b3 b2 b1 b0 port function control register (address 6d 16 ) bit name 0: pins p0 to p3 are used for the external bus output. 1: pins p0 to p3 are used for the port output. 0 standby state selection bit 1 sub-clock output selection bit/ timer b2 clock source selection bit 0: no internal connection 1: internal connection with timer b2 2 timer b1 internal connect selection bit 3 port p6 pull-up selection bit 0 0: no pull-up for pins p5 4 /ta2 out /ki 0 to p5 7 /ta3 in /ki 3 1: with pull-up for pins p5 4 /ta2 out /ki 0 to p5 7 /ta3 in /ki 3 6 port p5 pull-up selection bit 7 key input interrupt selection bit 0: int 2 interrupt 1: key input interrupt 5 port p6 pull-up selection bit 1 4 must be fixed to ?. at reset rw rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 0 ?ort-x c selection bit ] = ?? (when the sub clock is not used) timer b2 (event counter mode) clock source selection (note 1) 0: tb2 in input (event counter mode) 1: main clock divided by 32 (clock timer) ?ort-x c selection bit = ?? (when the sub clock is used) sub-clock output selection 0: pin p6 7 /tb2 in / f sub functions as a programmable i/o port. 1: sub clock f sub is output from pin p6 7 /tb2 in / f sub . (note 2) notes 1: when the port-xc selection bit = ??and timer b2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is in v 2: when timer b1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 2, 4, and 7 are not used f or the pull-up function. ?ey input interrupt selection bit = ? 0: no pull-up for pin p6 4 /int 2 1: with pull-up for pin p6 4 /int 2 ?ey input interrupt selection bit = ? 0: pin p6 4 /int 2 is a port with no pull-up. 1: pin p6 4 /int 2 is an input pin with pull-up 0: no pull-up for pins p6 2 /int 0 and p6 3 /int 1 1: with pull-up for pins p6 2 /int 0 and p6 3 /int 1 port-xc selection bit ] : bit 4 of the oscillation circuit control register 0 (addr ess 6c 16 ) and is used for the key input interrupt. valid.
7733 group users manual 3C10 programmable i/o ports 3.4 internal peripheral devices i/o functions (ports p4 2 and p5 to p8) ports p4 2 and p5 to p8 also function as i/o pins for the internal peripheral devices. table 3.4.1 lists correspondence between each port and internal peripheral devices i/o pin. for internal peripheral devices i/o functions, refer to the corresponding functional description. for the clock f 1 output pin, refer to chapter 12. connecting external devices. for the sub-clock oscillation circuits i/o pins, refer to chapter 14. clock generating circuit. 3.4 internal peripheral devices i/o functions (ports p4 2 and p5 to p8) table 3.4.1 correspondence between each port and internal peripheral devices i/o pin port p4 2 p5 0 to p5 3 p5 4 to p5 7 p6 0 , p6 1 p6 2 to p6 4 p6 5 , p6 6 p6 7 p7 0 , p7 1 p7 2 to p7 5 p7 6 , p7 7 p8 internal peripheral devices i/o pin clock f 1 output pin timer as i/o pins timer as i/o pins/key input interrupt functions input pins timer as i/o pins input pins for external interrupts timer bs input pins timer bs input pin/clock f sub output pin a-d converters input pins a-d converters input pins/i/o pins for serial i/o sub-clock oscillation circuits i/o pins/a-d converters input pins i/o pins for serial i/o
chapter 4 chapter 4 interrupts 4.1 overview 4.2 interrupt sources 4.3 interrupt control 4.4 interrupt priority level 4.5 interrupt priority level detection circuit 4.6 interrupt priority level detection time 4.7 how interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) 4.8 return from interrupt routine 4.9 multiple interrupts ____ 4.10 external interrupts ( inti interrupt) 4.11 precautions for interrupts
7733 group user's manual interrupts 4C2 interrupt routine interrupt request is accepted. processing is resumed. processing is suspended. returns to original routine. rti instruction interrupt processing routine in progress branches to start address of interrupt routine. the 7733 group provides 19 interrupt sources to generate interrupt requests. 4.1 overview figure 4.1.1 shows how interrupts are processed. when an interrupt request is accepted, a program branches to the start address of an interrupt routine which is set in the interrupt vector table (addresses ffd6 16 to ffff 16 ). set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table. 4.1 overview fig. 4.1.1 how interrupts are processed
7733 group user's manual 4C3 interrupts h [s] is the initial address that the stack pointer (s) indicates when an interrupt request is accepted. s? contents is ?s] ?5?after all of the above registers are pushed. address [s] ?4 [s] ?3 [s] ?2 [s] ?1 [s] processor status register? low-order byte (ps l ) stack area [s] ?5 processor status register? high-order byte (ps h ) program counter? low-order byte (pc l ) program counter? high-order byte (pc h ) program bank register (pg) when an interrupt request is accepted, the following registers contents immediately before acceptance of an interrupt request are automatically pushed onto the stack area , , and a in that order: program bank register (pg) program counter (pc l , pc h ) a processor status register (ps l , ps h ) figure 4.1.2 shows the state of the stack area immediately before the program branches to an interrupt routine. at the end of the interrupt routine, execute the rti instruction, which is an instruction for returning to the routine that was executed before acceptance of an interrupt request. by executing the rti instruction, the above registers contents, which were pushed onto the stack area, are popped a , , and in that order. then, execution of the suspended routine is resumed from where it left off. when an interrupt request is accepted and the rti instruction is executed, above registers ( to a ) are automatically pushed and popped. for other registers whose contents are necessary, be sure to push and pop them by software. 4.1 overview fig. 4.1.2 state of stack area immediately before program branches to interrupt routine
7733 group user's manual interrupts 4C4 low-order address 00fffe 16 00fffc 16 00fffa 16 00fff8 16 00fff6 16 00fff4 16 00fff2 16 00fff0 16 00ffee 16 00ffec 16 00ffea 16 00ffe8 16 00ffe6 16 00ffe4 16 00ffe2 16 00ffe0 16 00ffde 16 00ffdc 16 00ffda 16 00ffd8 16 00ffd6 16 remarks non-maskable non-maskable software interrupt non-maskable software interrupt not used usually non-maskable interrupt external interrupt by signal input from pin int 0 external interrupt by signal input from pin int 1 external interrupt by signal input from pin int 2 or by key input internal interrupt from timer a0 internal interrupt from timer a1 internal interrupt from timer a2 internal interrupt from timer a3 internal interrupt from timer a4 internal interrupt from timer b0 internal interrupt from timer b1 internal interrupt from timer b2 internal interrupt from uart0 internal interrupt from uart1 internal interrupt from a-d converter or uart2 interrupt source reset zero division brk instruction ____ dbc ( note 1 ) watchdog timer int 0 int 1 int 2 /key input ( note 2 ) timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 uart0 reception uart0 transmission uart1 reception uart1 transmission a-d/uart2 trans./ /rece. (note 3) high-order address 00ffff 16 00fffd 16 00fffb 16 00fff9 16 00fff7 16 00fff5 16 00fff3 16 00fff1 16 00ffef 16 00ffed 16 00ffeb 16 00ffe9 16 00ffe7 16 00ffe5 16 00ffe3 16 00ffe1 16 00ffdf 16 00ffdd 16 00ffdb 16 00ffd9 16 00ffd7 16 4.2 interrupt sources table 4.2.1 lists interrupt sources and their vector addresses. when programming, set the start address of each interrupt routine to the vector addresses listed below. 4.2 interrupt sources interrupt vector addresses table 4.2.1 interrupt sources and interrupt vector addresses notes 1: this is only for debugger control and is not used usually. 2: when the key input interrupt selection bit (bit 7 at address 6d 16 ) = 1, the key input interrupt function is selected. for details, refer to chapter 5 key input interrupt function. 3: the a-d conversion interrupt and the uart2 transmission/reception interrupt share the same interrupt vector addresses and interrupt control register. by setting the serial i/o mode selection bits (bits 0 to 2 at address 64 16 ), the a-d conversion interrupt or uart2 transmission/reception interrupt is selected.
7733 group user's manual 4C5 interrupts table 4.2.2 lists occurrence conditions of internal interrupt requests, which occur because of internal operations. 4.2 interrupt sources table 4.2.2 occurrence conditions of internal interrupt requests interrupt zero division interrupt brk instruction interrupt watchdog timer interrupt timer ai interrupt (i = 0 to 4) timer bi interrupt (i = 0 to 2) uarti reception interrupt (i = 0,1) uarti transmission interrupt (i = 0,1) uart2 transmission /reception interrupt a-d conversion interrupt occurrence conditions of interrupt requests occurs when divider is 0 in execution of div instruction (division instruction). (refer to 7700 family software manual. ) occurs when the brk instruction is executed. (refer to 7700 family software manual. ) occurs when the most significant bit of the watchdog timer becomes 0. (refer to chapter 10 watchdog timer. ) occurrence condition depends on timer ais operating modes. (refer to chapter 6 timer a. ) occurrence condition depends on timer bis operating modes. (refer to chapter 7 timer b. ) occurs at serial data reception. (refer to chapter 8 serial i/o. ) occurs at serial data transmission. (refer to chapter 8 serial i/o. ) occurs at serial data transmission/reception. (refer to chapter 8 serial i/o. ) occurs when a-d conversion is completed. (refer to chapter 9 a-d converter. ) for external interrupts, refer to section 4.10 external interrupts. for the key input interrupt, refer to chapter 5 key input interrupt function.
7733 group user's manual interrupts 4C6 a-d / uart2 trans./rece. interrupt control register uart0 transmission interrupt control register uart0 receive interrupt control register uart1 transmission interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 / key input interrupt control register address 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 4.3 interrupt control maskable interrupts are enabled or disabled by setting the following: l interrupt request bit l interrupt priority level selection bits l processor interrupt priority level (ipl) l interrupt disable flag (i) the interrupt disable flag (i) and processor interrupt priority level (ipl) are allocated to the processor status register (ps). an interrupt request bit and the interrupt priority level selection bits are allocated to the interrupt control register for the corresponding interrupt. figure 4.3.1 shows the memory map of interrupt control registers and figure 4.3.2 shows their structures. l maskable interrupts : by software, acceptance of these interrupts requests can be disabled. l non-maskable interrupts (zero division, brk instruction, and watchdog timer interrupts) : when an interrupt request occurs, it is certain to be accepted. they do not have interrupt control registers and are not affected by the interrupt disable flag (i). 4.3 interrupt control fig. 4.3.1 interrupt control registers memory map
7733 group user's manual 4? interrupts 4.3 interrupt control fig. 4.3.2 interrupt control registers?structures int 0 , int 1 , and int 2 /key input interrupt control registers (addresses 7d 16 to 7f 16 ) b2b1b0 0 0 0: level 0 (interrupt is disabled.) 0 0 1: level 1 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 rw 0 a-d / uart2 trans./rece., uart0 and 1 transmission, uart0 and 1 receive, timers a0 to a4, timers b0 to b2 interrupt control registers (addresses 70 16 to 7c 16 ) b7 b6 b5 b4 b3 b2 b1 b0 bit bit name functions at reset rw 0 2 3 4 5 6 7 1 b2b1b0 0 0 0 : level 0 (interrupt is disabled.) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 0 not implemented. 0 0 interrupt priority level selection bits interrupt request bit 0 un- defined 0: no interrupt request has occurred. 1: interrupt request has occurred. 0: interrupt request bit is set to ??at ? level when level sense is selected; this bit is set to ? at falling edge when edge sense is selected. 1: interrupt request bit is set to ??at ?? level when level sense is selected; this bit is set to ? at rising edge when level sense is selected. b7 b6 b5 b4 b3 b2 b1 b0 bit bit name functions rw 0 2 3 1 rw 0 rw 0 interrupt priority level selection bits interrupt request bit (note) 0: no interrupt request has occurred. 1: interrupt request has occurred. 0 rw 4 5 polarity selection bit level sense/edge sense selection bit 0: edge sense 1: level sense rw 0 0 at reset 6 7 un- defined not implemented. note: the interrupt request bits of int 0 to int 2 /key input interrupts are ignored when the level sense is se lected. rw rw rw rw rw rw
7733 group user's manual interrupts 4C8 4.3.1 interrupt disable flag (i) this flag can disable all maskable interrupts. when this flag is set to 1, all maskable interrupts are disabled; when this flag is cleared to 0, all maskable interrupts are enabled. because this flag is set to 1 at reset, clear this flag to 0 when enabling interrupts. this flag is allocated to the processor status register (ps). 4.3.2 interrupt request bit when an interrupt request occurs, this bit is set to 1. and then, this bit remains set to 1 until the interrupt request is accepted; this bit is cleared to 0 when the interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software, also. ____ ____ note that when an int i interrupt is used with the level sense selected, the int i interrupt request bit (i = 0 to 2) is ignored. 4.3.3 interrupt priority level selection bits and processor interrupt priority level (ipl) the interrupt priority level selection bits are used to set the priority level of an interrupt. when an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (ipl). only when the comparison result satisfies the following relationship, the interrupt request is enabled. therefore, by setting the interrupt priority level to 0, the interrupt can be disabled. the processor interrupt priority level (ipl) is allocated to the processor status register (ps). interrupt priority level > processor interrupt priority level (ipl) table 4.3.1 lists the settings of interrupt priority levels. table 4.3.2 lists the relationship between the ipls contents and enabled interrupt priority levels. the interrupt disable flag (i), interrupt request bit, interrupt priority level selection bits, and processor interrupt priority level (ipl) are independent of each other; they do not affect each other. interrupt requests are accepted only when the following conditions are satisfied. l interrupt disable flag (i) = 0 l interrupt request bit = 1 l interrupt priority level > processor interrupt priority level (ipl) 4.3 interrupt control
7733 group user's manual 4C9 interrupts b2 0 0 0 0 1 1 1 1 priority table 4.3.1 settings of interrupt priority levels interrupt priority level selection bits interrupt priority level low high ipl 2 0 0 0 0 1 1 1 1 enabled interrupt priority levels level 1 and above levels level 2 and above levels level 3 and above levels level 4 and above levels level 5 and above levels levels 6 and 7 level 7 only all maskable interrupts are disabled. ipl 1 0 0 1 1 0 0 1 1 ipl 0 0 1 0 1 0 1 0 1 table 4.3.2 relationship between ipls contents and enabled interrupt priority levels ipl 0 : bit 8 in the processor status register (ps) ipl 1 : bit 9 in the processor status register (ps) ipl 2 : bit 10 in the processor status register (ps) 4.3 interrupt control b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 level 0 (interrupt is disabled.) level 1 level 2 level 3 level 4 level 5 level 6 level 7
7733 group user's manual interrupts 4C10 4.4 interrupt priority level when the interrupt disable flag (i) = 0 (in other words, w hen interrupts are enabled), if multiple interrupt requests reside at the same sampling timing, where the prese nce of an interrupt request is checked, these requests are accepted in order of priority levels. in this c ase, an interrupt request which has the highest priority is accepted first. for 16 interrupt sources other than software interrupts (the zero division and brk instruction) and a watchdog timer interrupt, an arbitrary priority level can be set by specifying the interrupt priority level selection bits. note that the priority level for reset (hand led as an interrupt which has the highest priority) or a watchdog timer interrupt is set by hardware. figure 4.4 .1 shows the interrupt priority level set by hardware. note that software interrupts are not affected by the interr upt priority level. when the zero division or brk instruction is executed, a program branches to an interrupt routine. 4.4 interrupt priority level fig. 4.4.1 interrupt priority level set by hardware watchdog timer interrupt reset inside of dotted-line, an arbitrary priority level can be se t. high low interrupt priority level 16 interrupt sources other than software interrupts and watchdog timer interrupt
7733 group user's manual 4C11 interrupts a-d/uart2 trans. / rece. uart1 transmission uart1 reception uart0 transmission uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 ipl processor interrupt priority level interrupt with the highest priority interrupt disable flag (i) watchdog timer interrupt reset interrupt request is accepted. interrupt priority level of each interrupt level 0 (initial value) interrupt priority level of each interrupt 4.5 interrupt priority level detection circuit the interrupt priority level detection circuit is used to select an interrupt with the highest priority from multiple interrupts which reside at the same sampling timing. figure 4.5.1 shows the interrupt priority level detection circuit. 4.5 interrupt priority level detection circuit fig. 4.5.1 interrupt priority level detection circuit
7733 group user's manual interrupts 4C12 figure 4.5.2 shows the operation of the interrupt priority detection circuit. the interrupt priority level of a requested interrupt (y in figure 4.5.2) is compared with the priority level which is sent from the preceding comparator (x in figure 4.5.2), and then the interrupt with the higher priority level is sent to the next comparator (z in figure 4.5.2). (initial value of x is 0.) for an interrupt which is not requested, the comparison is not performed and the priority level which is sent from the preceding comparator is forwarded to the next comparator as it is. after comparison, if the two priority levels are the same, the priority level which is sent from the preceding comparator is forwarded to the next comparator. therefore, if the same priority is set by software, the interrupt priority levels are handled as follows: a-d conversion > uart2 transmission/reception > uart1 transmission > uart1 reception > uart0 transmission > uart0 reception > timer b2 > timer b1 > timer b0 > timer a4 > timer a3 > timer a2 > timer a1 > ____ ____ ____ timer a0 > int 2 /key input > int 1 > int 0 by the above comparison, among the multiple interrupt requests which reside at the same sampling timing, one request with the highest priority level is detected. and then, the highest priority level detected by the above comparison is compared with the processor interrupt priority level (ipl). when this interrupt priority level is higher than the processor interrupt priority level (ipl) and the interrupt disable flag (i) = 0, the corresponding interrupt request is accepted. an interrupt request which is not accepted at this time is held until it is accepted or the corresponding interrupt request bit is cleared to 0 by software ( clb instruction). the interrupt priority level is detected synchronously with the cpus op-code fetch cycle. however, when an op-code fetch cycle starts during the interrupt priority detection, a new interrupt priority detection does not start. (refer to figure 4.6.1 ) because the interrupt request bits state and interrupt priority level are latched during interrupt priority detection, if they change, the interrupt priority detection is performed for the previous state before the change occurred. 4.5 interrupt priority level detection circuit fig. 4.5.2 interrupt priority level detection model y x z comparison of priority level l when x 3 y, z = x l when x < y, z = y interrupt source y x : priority level which is sent from the preceding comparator (highest priority at this time) y : priority level of interrupt source y z : highest priority at this time time comparator
7733 group user's manual 4C13 interrupts (2) interrupt priority level detection time ? op-code fetch cycle sampling pulse (a) 7 cycles (b) 4 cycles (c) 2 cycles interrupt priority level detection time (note) note: this pulse resides when ? cycles of ? ? is selected. b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 1 1 0 1 1 processor mode register 0 (address 5e 16 ) processor mode bits wait bit software reset bit must be fixed to ?. clock ? 1 output selection bit 7 cycles of clock ? [(a) shown below] 4 cycles of clock ? [(b) shown below] 2 cycles of clock ? [(c) shown below] interrupt priority detection time selection bits do not select. (1) interrupt priority detection time selection bits b5, b4 4.6 interrupt priority level detection time when the interrupt priority level detection time has passed after sampling starts, an interrupt request is accepted. the interrupt priority level detection time can be selected by software. figure 4.6.1 shows the interrupt priority level detection time. usually, select 2 cycles of f as the interrupt priority level detection time. 4.6 interrupt priority level detection time fig. 4.6.1 interrupt priority level detection time
7733 group user's manual interrupts 4C14 @ @ : interrupt priority level detection time interrupt request is generated. interrupt request is accepted. instruction 1 instruction 2 intack sequence instructions in interrupt routine interrupt response time time @ time from when an interrupt request occurs until the instruction execution which is in progress at that time is completed. time from when execution of an instruction next to begins (note) until the instruction execution which is in progress at completion of interrupt priority level detection. note : at this time, detection of interrupt priority level begins. a time required to execute the intack sequence (13 cycles of ? at the shortest) a 4.7 how interrupts are processed (from acceptance of interrupt request until execution of interrupt routine) how interrupts are processed from accepting of an interrupt request until execution of the interrupt routine is described below. when an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt is cleared to 0. and then, execution of an interrupt routine begins at the cycle immediately after the instruction execution which was in progress at acceptance of the interrupt request is completed. figure 4.7.1 shows how interrupts are processed from acceptance of an interrupt request until execution of the interrupt routine. when the instruction execution which was in progress at acceptance of the interrupt request is completed, the intack (interrupt acknowledge) sequence is executed and the program branches to the start address of the interrupt routine allocated in addresses 0 16 to ffff 16 . in the intack sequence, the following procedure is automatically performed in this order. the contents of the program bank register (pg) immediately before the intack sequence is pushed onto the stack. the contents of the program counter (pc) immediately before the intack sequence is pushed onto the stack. a the contents of the processor status register (ps) immediately before the intack sequence is pushed onto the stack. ? the interrupt disable flag (i) is set to 1. ? the interrupt priority level of the accepted interrupt is set to ipl. ? the contents of the program bank register (pg) is cleared to 00 16 and the contents of the interrupt vector address is set into the program counter (pc). the intack sequence requires at least 13 cycles of f . figure 4.7.2 shows the intack sequences timing. after the intack sequence is completed, the instruction execution begins at the start address of an interrupt routine. 4.7 how interrupts are processed fig. 4.7.1 how interrupts are processed from acceptance of interrupt request until execution of interrupt routine
7733 group user's manual 4C15 interrupts intack sequence : cpu? standard clock : high-order 8 bits of cpu address bus : middle-order 8 bits of cpu address bus : low-order 8 bits of cpu address bus : data bus for cpu? odd address : data bus for cpu? even address l when stack pointer (s)? contens is even ? cpu a p a h a l d h d l pg pc h 00 00 00 00 00 00 00 00 00 00 ff 16 ad h pc h ps h pc l pg ps l ad h ad l pc l 00 55 16 d h a p a h interrupt disable flag (i) ? ? cpu d l a l ad l 00 ([s]?) h ([s]?) h ([s]?) h ([s]?) h ([s]?) h ([s]?) h [s] h ([s]?) l ([s]?) l ([s]?) l ([s]?) l ([s]?) l ([s]?) l [s] l op-code op-code ff 16 55 16 [s] 55 16 ad h ad l : contents of stack pointer (s) : low-order 8 bits of vector address : contents of vector address (high-order address) : contents of vector address (low-order address) : not used fig. 4.7.2 intack sequences timing table 4.7.1 change in ipl at acceptance of interrupt request change in ipl level 0 (000 2 ) is set. level 7 (111 2 ) is set. not changed not changed accepted interrupts priority level is set. interrupt source reset watchdog timer interrupt zero division interrupt brk instruction interrupt other interrupts 4.7 how interrupts are processed 4.7.1 change in ipl at acceptance of interrupt request when an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set to the processor interrupt priority level (ipl). this operation makes the processing for multiple interrupts easy. (refer to section 4.9 multiple interrupts. at reset or when a watchdog timer interrupt or software interrupt is accepted, a value listed in table 4.7.1 is set into ipl.
7733 group user's manual interrupts 4C16 pushed in 3 times a pushes 16 bits at a time. pushes 16 bits at a time. (1) when stack pointer (s)? contents is even processor status register? low-order byte (ps l ) processor status register? high-order byte (ps h ) program counter? low-order byte (pc l ) program counter? high-order byte (pc h ) program bank register (pg) address s? (even) s? (odd) s? (even) s? (odd) s (even) order for push s? (odd) processor status register? low-order byte (ps l ) processor status register? high-order byte (ps h ) program counter? low-order byte (pc l ) program counter? high-order byte (pc h ) program bank register (pg) address s? (odd) s? (even) s? (odd) s? (even) s (odd) a ? ? (2) stack pointer (s)? contents is odd pushes by the 8 bits. order for push pushed in 5 times s? (even) h ??is the initial address that the stack pointer (s) indicates when an interrupt request is accepted. s? contents is ???after the above registers are pushed. 4.7.2 how to push registers the way to push registers depends on whether the stack pointer (s)s contents at interrupt request acceptance is even or odd. when the stack pointer (s)s contents is even, each of the program counter (pc)s contents and processor status register (ps)s contents is simultaneously pushed by the 16 bits. when the stack pointer (s)s contents is odd, each of these registers is pushed by the 8 bits. figure 4.7.3 shows how the registers are pushed. in the intack sequence, only the contents of the program bank register (pg), program counter (pc), and processor status register (ps) are pushed onto the stack area. make sure to push other necessary registers by software at the beginning of an interrupt routine. by executing the psh instruction, all cpu registers other than the stack pointer can be pushed. 4.7 how interrupts are processed fig. 4.7.3. how registers are pushed
7733 group user's manual 4C17 interrupts 4.8 return from interrupt routine when the rti instruction is executed at the end of an interrupt routine, the contents of the program bank register (pg), program counter (pc), and processor status register (ps) which were pushed onto the stack area immediately before the intack sequence are automatically pulled. and then, a program returns to the original routine and the suspended process is resumed. before the rti instruction is executed, by executing the pul instruction or others, make sure to pull registers which were pushed by software in an interrupt routine. make sure that the data length and register length for the pull operation are equal to those for the push operation. 4.9 multiple interrupts when a program branches to an interrupt routine, the following occurs: l interrupt disable flag (i) = 1 (interrupts are disabled.) l interrupt request bit of accepted interrupt = 0 l processor interrupt priority level (ipl) = interrupt priority level of accepted interrupt therefore, as long as the ipl remains unchanged, by clearing the interrupt disable flag (i) to 0 in an interrupt routine, an interrupt request whose priority level is higher than the priority level of the interrupt which is in progress can be accepted. in this way, multiple interrupts are processed. figure 4.9.1 shows how multiple interrupts are processed. an interrupt request which is not accepted because its priority level is lower is held. when the rti instruction is executed, the interrupt priority level of the routine which was in progress at acceptance of an interrupt request is pulled to the ipl. therefore, if the following relationship is satisfied when interrupt priority level detection is performed next, the held interrupt request is accepted. held interrupt requests priority level > processor interrupt priority level (ipl) which is pulled 4.8 return from interrupt routine, 4.9 multiple interrupts
7733 group user's manual interrupts 4C18 main routine reset i = 1 ipl = 0 i = 0 interrupt 1 i = 1 ipl = 3 i = 0 i = 1 ipl = 5 rti i = 0 ipl = 3 rti i = 0 ipl = 0 i = 1 ipl = 2 rti i = 0 ipl = 0 interrupt 1 interrupt priority level = 3 cannot be accepted because its priority level is low. interrupt request generated nesting time : automatically be set. : must be set by software. i : interrupt disable flag ipl : processor interrupt priority level multiple interrupts interrupt 2 interrupt priority level = 5 interrupt 3 interrupt priority level = 2 interrupt 2 interrupt 3 interrupt 3 instruction in main routine is not executed. fig. 4.9.1 how multiple interrupts are processed 4.9 multiple interrupts
7733 group user's manual 4C19 interrupts ____ 4.10 external interrupts ( int i interrupt) ____ an external interrupt request occurs by input signal from pi n int i (i = 0 to 2). the occurrence condition of an external interrupt request can be selected by the level s ense/edge sense selection bit and the polarity selection bit (bits 5 and 4 at addresses 7d 16 to 7f 16 ) shown in figure 4.10.2. table 4.10.1 lists the ____ occurrence condition of int i interrupt request. ____ ____ when using pins p6 2 / int 0 to p6 4 / int 2 as external interrupt input pins, set their corresponding b its at address 10 16 (port p6 direction register) to 0. (refer to figure 4.10.1. ) these pins can be pulled high by ____ ____ software. (refer to section 3.3 pull-up function of p6 2 to p6 4 pins ( int 0 to int 2 ). ____ the int 2 interrupt is invalid when the key input interrupt selection bit (bit 7 at address 6d 16 ) = 1. (refer ____ to chapter 5 key input interrupt function. ) when using the int 2 interrupt function, clear the key input interrupt selection bit to 0. ____ a signal which is input to pin int i requires a h/l-level duration of 250 ns or more indepen dent of the system clock frequency (note 1) . ____ ____ note that even when pins p6 2 / int 0 to p6 4 / int 2 are used as external interrupt input pins, these pins stat e can be read in by reading bits 2 to 4 at address e 16 (port p6 register). note 1: when the falling edge or l level is selected as the interr upt occurrence condition, make sure that l-level duration must be at least 250 ns: when the rising edge or h level is selected as the interrupt occurrence condition, make sure that h-level dur ation must be at least 250 ns. ____ 4.10 external interrupts ( int i interrupt) ____ table 4.10.1 occurrence condition of int i interrupt request b5 (note 2) 0 0 1 1 b4 (note 2) 0 1 0 1 ____ ____ note 2: b5 and b4 represent bits 5 and 4 of the int 0 to int 2 /key input interrupt control register. (refer to figure 4.10.2. ) ____ ____ in an int i interrupt, pin int i s state is always checked, and then an interrupt request is generated ____ ____ according to the state. therefore, when an int i interrupt is not used, clear the int i interrupts priority level to 0. ____ int i interrupt request occurrence condition ____ occurs at the falling edge of an input signal to pin int i (edge sense). ____ occurs at the rising edge of an input signal to pin int i (edge sense). ____ occurs when pin int i is at h level (level sense). ____ occurs when pin int i is at l level (level sense).
7733 group user's manual interrupts 4?0 ____ 4.10 external interrupts ( int i interrupt) fig. 4.10.1 correspondence between port p6 direction registe r and input pins for external interrupts ____ ____ fig. 4.10.2 int 0 to int 2 interrupt control register? structure bit 7 pin tb2 in 6 pin tb1 in 5 pin tb0 in 4 pin int 2 /key input 3 pin int 1 2 pin int 0 1 pin ta4 in 0 pin ta4 out at reset 0 0 0 0 0 0 0 0 rw rw functions b7 b6 b5 b4 b3 b2 b1 b0 port p6 direction register (address 10 16 ) 0 : input mode 1 : output mode when using a pin as an input pin for an external interrupt, clear the corresponding bit to ?. represents that bits 0, 1 and bits 5 to 7 are not used for e xternal interrupts. rw rw rw rw rw rw rw corresponding pin? name int 0 , int 1 , and int 2 /key input interrupt control registers (addresses 7d 16 to 7f 16 ) b2b1b0 0 0 0: level 0 (interrupt is disabled.) 0 0 1: level 1 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 rw 0 0: interrupt request bit is set to ??at ? level when level sense is selected; this bit is set to ? at falling edge when edge sense is selected. 1: interrupt request bit is set to ??at ?? level when level sense is selected; this bit is set to ? at rising edge when level sense is selected. b7 b6 b5 b4 b3 b2 b1 b0 bit bit name functions rw 0 2 3 1 rw 0 rw 0 interrupt priority level selection bits interrupt request bit (note) 0: no interrupt request has occurred. 1: interrupt request has occurred. 0 rw 4 5 polarity selection bit level sense/edge sense selection bit 0: edge sense 1: level sense rw 0 0 at reset 6 7 un- defined not implemented. note: the interrupt request bits of int 0 to int 2 /key input interrupts are ignored when the level sense is se lected. rw rw
7733 group user's manual 4C21 interrupts ____ 4.10.1 inti interrupt request bits function (1) functions when edge sense is selected by clearing the level sense/edge sense selection bit to 0, the edge sense is selected. (refer to figure 4.10.3. ) the interrupt request bit has the same functions as those fo r the interrupt request bit of internal interrupts. when an interrupt occurs, the interrupt request bit is set t o 1 and retains this state until the interrupt request is accepted. when the interrupt request bit is cleared to 0 by software, an interrupt request is cancelled; when the interrupt request bit is set to 1 by software, an inte rrupt request can be generated. (2) functions when level sense is selected by setting the level sense/edge sense selection bit to 1, the level sense is selected. (refer to figure 4.10.3. ) ____ the i nterrupt request bit is ignored. in this case, interrupt req uests occur sequentially while pin int i ____ is at the valid level ] 1 ; when pin int i s level changes to the invalid level ] 2 with the interrupt request not accepted, the interrupt request is not held. (refer to figure 4.10.4. ) valid level ] 1 : the level selected by the polarity selection bit (bit 4 at addresses 7d16 to 7f16) invalid level ] 2 : the reverse level to valid level ____ 4.10 external interrupts ( int i interrupt) ____ fig. 4.10.3 int i interrupt request ____ fig. 4.10.4 re-occurrence of int i interrupt request when level sense is selected pin int i edge detection circuit interrupt request level sense/edge sense selection bit 0 1 data bus interrupt request bit level sense edge sense 1st interrupt routine pin int i s level valid invalid main routine interrupt request is accepted. return to main routine 2nd interrupt routine 3rd interrupt routine main routine
7733 group user's manual interrupts 4?2 ____ 4.10.2 how to switch inti interrupt request occurrence condi tion ____ the way to switch the int i interrupt request occurrence condition from the level sense to the edge sense is shown in figure 4.10.5 (1). the way to switch the polarity is shown in figure 4.10.5 (2) . ____ 4.10 external interrupts ( int i interrupt) ____ fig. 4.10.5 how to switch int i interrupt request occurrence condition set interrupt priority level to 0. ( int i interrupt is disabled. ) clear the level sense/edge sense selection bit to ?. ( edge sense selected ) clear the interrupt request bit to ?. set the interrupt priority level to one of levels 1 to 7 . ( int i interrupt request is acceptable. ) clear the interrupt request bit to ?. set interrupt priority level to 0. ( int i interrupt is disabled. ) set the polarity selection bit. set the interrupt priority level to one of levels 1 to 7. ( int i interrupt request is acceptable. ) (2) how to switch the polarity (1) how to switch the int i interrupt request occurrence condition from level sense to edge sense
7733 group user's manual 4C23 interrupts ; the write instruction for the interrupt priority level selection bits ; the nop instruction is inserted (note) ; ; ; the write instruction for the interrupt priority level selection bits note: other instructions whose cycle number corresponds to that of the nop instruction (other than the write instructions for address 7x 16 ) can be inserted. for number of the nop instructions which are to be inserted, refer to table 4.11.1. : ldm .b #0xh, 007xh nop nop nop ldm .b #0xh, 007xh 4.11 precautions for interrupts when the contents of the interrupt priority level selection bits (bits 0 to 2 at addresses 70 16 to 7f 16 ) is changed, 2 to 7 cycles of f are required. therefore, when the interrupt priority level of the same interrupt source is changed twice or more in a very short time, which consists of a few instructions, it is necessary to secure the required time by software. figure 4.11.1 shows an program example to secure the time required for the change of an interrupt priority level. note that the time required for the change depends on the contents of the interrupt priority level selection bits (bits 4 and 5 at address 5e 16 ). table 4.11.1 lists the correspondence between the number of instructions inserted in a program example and the interrupt priority level selection bits. (refer to figure 4.11.1, also.) 4.11 precautions for interrupts table 4.11.1 correspondence between number of instructions to be inserted in figure 4.11.1 and interrupt priority detection time selection bits interrupt priority detection time selection bits (note) b4 0 1 0 1 b5 0 0 1 1 time required for change of interrupt priority level number of inserted nop instruction 7 cycles of f 4 cycles of f 2 cycles of f 4 or more 2 or more 1 or more set as follows, if possible: [b5 = 1, b4 = 0] fig. 4.11.1 program example to secure time required for change of interrupt priority level do not select.
7733 group user's manual interrupts 4C24 4.11 precautions for interrupts memo
chapter 5 chapter 5 key input interrupt function 5.1 overview 5.2 block description 5.3 initial setting example for related registers
key input interrupt function 7733 group users manual 5C2 ki 2 ki 1 ki 0 p6 4 /int 2 p6 3 p6 2 p6 1 p6 0 key matrix m37733mhbxxxfp ki 3 the key input interrupt function is used to generate an interrupt request when one of the input levels of four or five pins falls. by using this function when terminating the stop or wait mode, the key-on wakeup can be realized. for the way to terminate the stop or wait mode, refer to section 17.4 power saving. for the stop and wait modes, refer to chapter 11. stop and wait modes. 5.1 overview ___ ___ a key input interrupt request occurs when one of the input levels of pins ki 0 to ki 3 falls. therefore, by configuring an external key matrix shown in figure 5.1.1, an interrupt request can be generated only by ___ ___ pushing a key. pins ki 0 to ki 3 can be pulled high by software and the same function can also be selected ___ ___ for port p6 4 . therefore, when using the key input interrupt function, whether to use four pins (pins ki 0 to ki 3 ) ___ ___ or five pins (pins ki 0 to ki 3 and p6 4 ) can be selected. ____ the key input interrupt and the int 2 interrupt share the same interrupt vector addresses and interrupt control register. 5.1 overview fig. 5.1.1 key matrix example when key input interrupt function is used
key input interrupt function 7733 group users manual 5C3 b7 b6 b5 b4 b3 b2 b1 b0 port p5 direction register (address d 16 ) 0 00 0 b7 b6 b5 b4 b3 b2 b1 b0 port p6 direction register (address 10 16 ) 0 0: must be set to ?. 0: must be set to ?. int 2 /key input interrupt control register interrupt control register p6 4 / int 2 p5 7 / ki 3 p5 5 / ki 1 p5 6 / ki 2 p5 4 / ki 0 int 2 /key input interrupt request key input interrupt selection bit (address 7f 16 ) when key input interrupt is selected, it is necessary to select edge sense which uses falling edge. pull?p transistor port p5 pull-up selection bit port p5 7 direction register 0 1 pull?p transistor pull?p transistor pull?p transistor port p6 pull-up selection bit 1 port p6 4 direction register 0 1 port p6 pull-up selection bit 1 5.2 block description figure 5.2.1 shows the block diagram for the key input interrupt function. 5.2 block description fig. 5.2.1 block diagram for key input interrupt function ___ ___ ____ 5.2.1 pins ki 0 to ki 3 and p6 4 / int 2 when the key input interrupt function is selected, pins p5 4 to p5 7 become input pins for the key input ___ ___ interrupt ( ki 0 to ki 3 ). when selecting the key input interrupt function, clear all of bits 4 to 7 at address d 16 (port p5 direction register) to 0. ___ ___ when bits 4 to 7 at address b 16 (port p5 register) are read out, the status of pins ki 0 to ki 3 can be read ____ in. when using pin p6 4 / int 2 as an input pin for the key input interrupt, set both of bits 5 and 7 at address 6d 16 to 1 and bit 4 at address 10 16 (port p6 direction register) to 0. when bit 4 at address e6 16 (port ____ p6 register) is read out, the status of pin p6 4 / int 2 can be read in. fig. 5.2.2 port p5 and p6 direction registers when key input interrupt function is selected
key input interrupt function 7733 group users manual 5C4 bit functions b7 b6 b5 b4 b3 b2 b1 b0 port function control register (address 6d 16 ) bit name 0: pins p0 to p3 are used for the external bus output. 1: pins p0 to p3 are used for the port output. 0 standby state selection bit 1 sub-clock output selection bit/ timer b2 clock source selection bit 0: no internal connection 1: internal connection with timer b2 2 timer b1 internal connect selection bit 3 port p6 pull-up selection bit 0 0: no pull-up for pins p5 4 /ta2 out /ki 0 to p5 7 /ta3 in /ki 3 1: with pull-up for pins p5 4 /ta2 out /ki 0 to p5 7 /ta3 in /ki 3 6 port p5 pull-up selection bit 7 key input interrupt selection bit 0: int 2 interrupt 1: key input interrupt 5 port p6 pull-up selection bit 1 4 must be fixed to 0. at reset rw rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 0 ?port-x c selection bit ] = 0 (when the sub clock is not used) timer b2 (event counter mode) clock source selection (note 1) 0: tb2 in input (event counter mode) 1: main clock divided by 32 (clock timer) ?port-x c selection bit = 1 (when the sub clock is used) sub-clock output selection 0: pin p6 7 /tb2 in / f sub functions as a programmable i/o port. 1: sub clock f sub is output from pin p6 7 /tb2 in / f sub . (note 2) notes 1: when the port-xc selection bit = 0 and timer b2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: when timer b1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 4 are not used for the key input interrupt function. ?key input interrupt selection bit = 0 0: no pull-up for pin p6 4 /int 2 1: with pull-up for pin p6 4 /int 2 ?key input interrupt selection bit = 1 0: pin p6 4 /int 2 is a port with no pull-up. 1: pin p6 4 /int 2 is an input pin with pull-up and is used for the key input interrupt. 0: no pull-up for pins p6 2 /int 0 and p6 3 /int 1 1: with pull-up for pins p6 2 /int 0 and p6 3 /int 1 port-xc selection bit ] : bit 4 of the oscillation circuit control register 0 (addr ess 6c 16 ) 5.2.2 port function control register figure 5.2.3 shows the structure of the port function contro l register. 5.2 block description fig. 5.2.3 structure of port function control register
key input interrupt function 7733 group users manual 5C5 (1) port p6 pull-up selection bit (bit 5) ____ when using pin p6 4 / int 2 as an input pin for the key input interrupt, set this bit t o 1. when this bit ____ is set to 1, pin p6 4 / int 2 is pulled high. (2) port p5 pull-up selection bit (bit 6) ___ ___ this is a bit to pull pins ki 0 to ki 3 high. when configuring a key matrix, there is no need to co nnect ___ ___ pull-up transistors externally if this bit is set to 1, in other words, if pins ki 0 to ki 3 are set to be pulled high. (3) key input interrupt selection bit (bit 7) this is a bit to select the key input interrupt function. ____ the key input interrupt and the int 2 interrupt share the same interrupt vector addresses and int errupt control register. when this bit is set to 1, the key inpu t interrupt function is selected. when this bit ____ = 1 and bit 5 (port p6 pull-up selection bit) = 0, pin p 6 4 / int 2 is a programmable i/o port. (at this ____ time, the int 2 interrupt cannot be used.) when both of this bit and bit 5 (port p6 pull-up selection bit ____ 1) are 1, pin p6 4 / int 2 can be used for the key input interrupt. 5.2 block description
key input interrupt function 7733 group users manual 5C6 b7 b6 b5 b4 b3 b2 b1 b0 int 2 /key input interrupt control register (address 7f 16 ) bit 4 must be fixed to 0. 3 interrupt request bit 2 1 0 interrupt priority level selection bits bit name at reset undefined 0 0 0 0 0 0 rw functions 0 0 0: level 0 (interrupt is disabled.) 0 0 1: level 1 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 b2 b1 b0 0: no interrupt request has occurred. 1: interrupt request has occurred. 5 7 6 not implemented. 00 undefined rw rw rw rw rw rw C C 5.2.3 interrupt function ____ the key input interrupt and the int 2 interrupt share the same interrupt vector addresses and int errupt ____ control register. specify addresses fff0 16 and fff1 16 (in other words, the vector addresses for the int 2 / ____ key input interrupt) as the interrupt vector addresses; spec ify the int 2 /key input interrupt control register ____ (address 7f 16 ) as the interrupt control register. figure 5.2.4 shows the structure of the int 2 /key input interrupt control register when the key input interrupt func tion is selected. ____ the operation at accepting a key input interrupt request is the same as that at accepting an int 2 interrupt request. 5.2 block description ____ fig. 5.2.4 structure of int 2 /key input interrupt control register when key input interru pt function is selected
key input interrupt function 7733 group users manual 5C7 setting of interrupt priority level b0 int 2 /key input interrupt control register (address 7f 16 ) b7 0 00 interrupt priority level selection bits one of levels 1 to 7 must be set. interrupt request bit h in order to enable the key input interrupt, the interrupt disable flag (i) must be set to ??and the processor interrupt priority level (ipl) must be a value smaller than the int 2 /key input interrupt? priority level. (refer to chapter ?. interrupts. ) b0 selection of the key input interrupt function selection of the key input interrupt function pull-up selection for pins ki 0 to ki 3 port function control register (address 6d 16 ) 0: no pull-up 1: pull-up port p5 pull-up selection bit b7 10 0: port p6 4 is a programmable i/o port with no pull-up. 1: port p6 4 is an input pin with pull-up and is used for the key input interrupt. port p6 pull-up selection bit 1 setting of port p5 and p6 direction registers b7 b0 port p5 direction register (address d 16 ) p5 4 to p5 7 are set to the input mode. (must be set to ?000.? 0 0 0 0 b7 b0 port p6 direction register (address 10 16 ) when setting p6 4 as an input pin for the key input interrupt, set this bit to ?. 0 5.3 initial setting example for related registers figure 5.3.1 shows an initial setting example for registers related to the key input interrupt function. fig. 5.3.1 initial setting example for registers related to key input interrupt function 5.3 initial setting example for related registers
key input interrupt function 7733 group users manual 5C8 5.3 initial setting example for related registers memo
chapter 6 chapter 6 timer a 6.1 overview 6.2 block description 6.3 timer mode 6.4 event counter mode 6.5 one-shot pulse mode 6.6 pulse width modulation (pwm) mode
timer a 7733 group users manual 6C2 6.1 overview timer a is used mainly for output to the external. it consists of five counters (timers a0 to a4), and each has a 16-bit reload function. timers a0 to a4 operate independently of each other. timer ai (i = 0 to 4) has four operating modes listed below. except for the event counter mode, timers a0 to a4 all have the same functions. n timer mode timer a counts a count source internally generated, and the following functions can be used: l gate function l pulse output function n event counter mode timer a counts an external signal, and the following functions can be used: l free-run count function (timers a2, a3, and a4) l pulse output function l two-phase pulse signal processing function (timers a2, a3, and a4) n one-shot pulse mode timer a outputs a pulse which has an arbitrary width once. n pulse width modulation (pwm) mode timer a outputs pulses which have an arbitrary width in succession and functions as one of the following pulse width modulators: l 16-bit pulse width modulator l 8-bit pulse width modulator 6.1 overview
timera1 timer a 7733 group users manual 6C3 6.2 block description figure 6.2.1 shows the timer a block diagram. registers rela ted to timer a are described below. fig. 6.2.1 timer a block diagram 6.2 block description data bus (odd) data bus (even) f 2 f 16 f 64 f 512 clock source selection ?timer mode ?one-shot pulse mode ?pwm mode polarity switching timer mode (gate function) event counter mode external trigger count start flag countdown up-down flag (low-order 8 bits) (high-order 8 bits) timer ai reload register (16) timer ai counter (16) timer ai interrupt request bit countup/countdown switching countdown is selected when not in the event counter mode. toggle f.f. pulse output function selection bit tai in (i = 0 to 4) tai out (i = 0 to 4) clocks f2 , f16 , f64 , and f512 : refer to chapter 14. clock generating circuit. ( address 40 16 ) ( address 44 16 ) timera0 47 16 46 16 49 16 48 16 timera2 4b 16 4a 16 timera3 4d 16 4c 16 timera4 4f 16 4e 16 addresses
timer a 7733 group users manual 6C4 timer ai register high-order byte low-order byte timer a0 register address 47 16 address 46 16 timer a1 register address 49 16 address 48 16 timer a2 register address 4b 16 address 4a 16 timer a3 register address 4d 16 address 4c 16 timer a4 register address 4f 16 address 4e 16 6.2.1 counter and reload register (timer ai register) each of timer ai counter and its reload register consists of 16 bits. the counter performs countdown each time a count source is input. in the event counter mode, it can also function as an up-counter. the reload register is used to memorize the initial value of a counter. when an underflow/overflow occurs in the counter, the reload registers contents is reloaded into the counter. however, when the free-run count function is used, the reload registers contents is not reloaded into the counter. values are set to the counter and reload register by writing the values to the timer ai register. table 6.2.1 lists the memory allocation of the timer ai register. a value written into the timer ai register while counting is stopped is set to the counter and reload register. a value written into the timer ai register while counting is in progress is set only to the reload register. in this case, the reload registers updated contents is transferred to the counter at the next reload time. a value obtained by reading out the timer ai register depends on the operating mode. table 6.2.2 lists reading and writing from and to the timer ai register. table 6.2.1 memory allocation of timer ai register table 6.2.2 reading and writing from and to timer ai register write written only to the reload register. written to both of the counter and reload register. 6.2 block description note: at reset, the contents of the timer ai register is undefined. operating mode timer mode event counter mode one-shot pulse mode pulse width modulation (pwm) mode read counter value is read out. ( note 1 ) undefined value is read out. notes 1: also refer to precautions in timer mode and precautions in event counter mode. 2: perform reading or writing by the 16 bits.
timer a 7733 group users manual 6C5 6.2.2 count start flag this register is used to start or stop counting. each bit of this register corresponds to each timer, respectively. figure 6.2.2 shows the structure of the count start flag. 6.2 block description fig. 6.2.2 structure of count start flag bit 7 timer b2 count start flag 6 timer b1 count start flag 5 timer b0 count start flag 4 timer a4 count start flag 3 timer a3 count start flag 2 timer a2 count start flag 1 timer a1 count start flag 0 timer a0 count start flag bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 count start flag (address 40 16 ) 0: counting is stopped. 1: counting is started. represents that bits 7 to 5 are not used for timer a. rw rw rw rw rw rw rw rw
timer a 7733 group users manual 6C6 6.2.3 timer ai mode register figure 6.2.3 shows the structure of the timer ai mode regist er. the operating mode selection bits are used to select an operating mode of timer ai. bits 7 to 2 have di fferent functions according to the operating mode. these bits are described in a section of each operatin g mode. 6.2 block description fig. 6.2.3 structure of timer ai mode register bit 7 5 4 3 1 bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0: timer mode 0 1: event counter mode 1 0: one-shot pulse mode 1 1: pulse width modulation (pwm) mode b1 b0 2 these bits have different functions according to the operat ing mode. 0 operating mode selection bits 6 rw rw rw rw rw rw rw rw
timer a 7733 group users manual 6C7 6.2.4 timer ai interrupt control register figure 6.2.4 shows the structure of the timer ai interrupt c ontrol register. for details about interrupts, refer to chapter 4. interrupts. 6.2 block description fig. 6.2.4 structure of timer ai interrupt control register (1) interrupt priority level selection bits (bits 2 to 0) these bits select a timer ai interrupts priority level. whe n using timer ai interrupts, select one priority level from levels 1 to 7. if a timer ai interrupt request is generated, its priority level is compared with the processor interrupt priority level (ipl), and then the r equested interrupt is enabled only when its priority level is higher than the ipl. (however, this is app lied when the interrupt disable flag (i) = 0.) when disabling timer ai interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when a timer ai interrupt request is generated. this bit is automatically cleared to 0 when the timer ai interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software. bit not implemented. 3 interrupt request bit 2 1 0 interrupt priority level selection bits bit name at reset undefined 0 0 0 0 rw functions 0 0 0: level 0 (interrupt is disabled.) 0 0 1: level 1 priority is low. 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 priority is high. b2 b1 b0 0: no interrupt request has occurred. 1: interrupt request has occurred. 7 to 4 b7 b6 b5 b4 b3 b2 b1 b0 timer ai interrupt control register (i = 0 to 4) (addresses 75 16 to 79 16 ) rw rw rw rw C
timer a 7733 group users manual 6C8 6.2.5 port p5 and port p6 direction registers i/o pins of timers a0 to a3 are multiplexed with port p5, an d i/o pins of timer a4 are multiplexed with port p6. when using these pins as timer ais input pins, set the corresponding bits of the port p5 and port p6 direction registers to 0 in order to set these ports for t he input mode. when using these pins as timer ais output pins, these pins are forcibly set to output pins of timer ai independent of the direction registers contents. figure 6.2.5 shows the relationship between the po rt p5 and port p6 direction registers and the timer ais i/o pins. 6.2 block description fig. 6.2.5 relationship between port p5 and port p6 directio n registers and timer ais i/o pins bit corresponding pin name functions 0 1 2 3 4 5 6 7 pin p5 0 /ta0 out pin p5 2 /ta1 out pin p5 3 /ta1 in pin p5 4 /ta2 out pin p5 6 /ta3 out 0: input mode 1: output mode when using these pins as timer ais input pins, set the corresponding bits to 0. pin p5 5 /ta2 in port p5 direction register (address d 16 ) b1 b0 b2 b3 b4 b5 b6 b7 pin p5 1 /ta0 in pin p5 7 /ta3 in at reset rw 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 pin p6 0 /ta4 out pin p6 2 /int 0 pin p6 3 /int 1 pin p6 4 /int 2 pin p6 6 /tb1 in pin p6 5 /tb0 in port p6 direction register (address 10 16 ) b1 b0 b2 b3 b4 b5 b6 b7 pin p6 1 /ta4 in pin p6 7 /tb2 in / f sub rw 0 0 0 0 0 0 0 0 represents that bits 2 to 7 are not used for timer a. corresponding pin name functions bit at reset 0: input mode 1: output mode when using these pins as timer ais input pins, set the corresponding bits to 0. rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
timer a 7733 group users manual 6C9 6.3 timer mode (bits 1 and 0 of timer ai mode register = 00 2 ) in this mode, a count source internally generated is counted. (refer to table 6.3.1. ) figure 6.3.1 shows the structures of the timer ai mode register and timer ai register in the timer mode. table 6.3.1 specifications of timer mode 6.3 timer mode item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing pin tai in s function pin tai out s function read from timer write to timer specifications clock f 2 , f 16 , f 64 , or f 512 l countdown l at an underflow, the reload registers contents is reloaded, and counting is continued. when the count start flag is set to 1. when the count start flag is cleared to 0. at an underflow programmable i/o port or gate input programmable i/o port or pulse output a counter value can be read out by reading the timer ai register. n while counting is stopped when a value is written to the timer ai register, it is written to both of the reload register and counter. n while counting is in progress when a value is written to the timer ai register, it is written only to the reload register. (transferred to the counter at the next reload time.) 1 (n + 1) n: set value in the timer ai register clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit.
timer a 7733 group users manual 6C10 6.3 timer mode fig. 6.3.1 structures of timer ai mode register and timer ai register in timer mode clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. 3 gate function selection bits 2 pulse output function selection bit 1 0 operating mode selection bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0: timer mode 0: no pulse is output. (pin tai out functions as a programmable i/o port.) 1: pulse is output. (pin tai out functions as a pulse output pin.) 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 6 count source selection bits b1 b0 b4 b3 5 must be fixed to 0 in the timer mode. 00 0 0 x: no gate function (pin tai in functions as a programmable i/o port.) 1 0: counter counts only while pin tai in s input signal level is l. 1 1: counter counts only while pin tai in s input signal level is h. bit 4 at reset 0 0 0 0 0 0 0 0 rw b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. undefined rw rw rw rw rw rw rw rw rw
timer a 7733 group users manual 6C11 6.3.1 setting for timer mode figures 6.3.2 and 6.3.3 show an initial setting example for registers related to the timer mode. note that when using interrupts, setting for enabling interr upts is required. for details, refer to chapter 4. interrupts. 6.3 timer mode fig. 6.3.2 initial setting example for registers related to timer mode (1) h counter divides the count source frequency by (n + 1). b7 b0 pulse output function selection bit 0: no pulse is output. 1: pulse is output. 00 0 selection of the timer mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) x: it may be either 0 or 1. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. b7 b6 b4 b3 gate function selection bits 0 x: no gate function 1 0: counter counts only while pin tai in s input signal level is l. 1 1: counter counts only while pin tai in s input signal level is h. count source selection bits 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 timer mode is selected. setting of the division ratio b7 b0 values 0000 16 to ffff 16 (n) can be set. (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) continued to initial setting example for registers related to timer mode (2) on the next page
timer a 7733 group users manual 6C12 6.3 timer mode fig. 6.3.3 initial setting example for registers related to timer mode (2) aaaa aaaa aaaa counting is started. setting of the count start flag to ?. b7 b0 count start flag (address 40 16 ) timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag setting of the interrupt priority level b7 b0 timer ai interrupt control register (addresses 75 16 to 79 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set. continued from ?nitial setting example for registers related to timer mode (1) on the preceding page setting of the port p5 and port p6 direction registers b7 b0 port p5 direction register (address d 16 ) pin ta0 in pin ta1 in pin ta2 in b7 b0 port p6 direction register (address 10 16 ) when the gate function is selected, set the bit corresponding to pin tai in to ?.? pin ta4 in pin ta3 in
timer a 7733 group users manual 6C13 6.3.2 count source in the timer mode, by the count source selection bits (bits 6 and 7 at addresses 56 16 to 5a 16 ), a count source can be selected. table 6.3.2 lists the relationship between the count source selection bits and count source. table 6.3.2 relationship between count source selection bits and count source 6.3 timer mode b7 0 0 1 1 b6 0 1 0 1 count source f 2 f 16 f 64 f 512 frequency of count source when system clock = 25 mhz when system clock = 16 mhz when system clock = 8 mhz clocks f 2 , f 16 , f 64 , f 512 , and system clock: refer to chapter 14. clock generating circuit. note: this is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0 and the main clock division selection bit (bit 0 at address 6f 16 ) = 0. (for details, refer to chapter 14. clock generating circuit. ) 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz 8 mhz 1 mhz 250 khz 31.25 khz 4 mhz 500 khz 125 khz 15.625 khz
timer a 7733 group users manual 6C14 6.3.3 operation in timer mode when the count start flag is set to 1, the counter starts counting of the count source. when an underflow occurs, the reload registers contents is reloaded, and then counting is continued. a the timer ai interrupt request bit is set to 1 when the u nderflow occurs in . after this, the interrupt request bit remains set to 1 unt il the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 6.3.4 shows an operation example in the timer mode. 6.3 timer mode fig. 6.3.4 operation example in timer mode (without pulse ou tput and gate functions) counting is stopped. counting is restarted. ffff 16 n 0000 16 time count start flag timer ai interrupt request bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when an interrupt request is accepted; otherwise, cleared by software set to 1 by software counting is started. set to 1 by software 0 0 1 / f i 5 (n + 1) fi = frequency of count source (f 2 , f 16 , f 64 , f 512 ) cleared to 0 by software
timer a 7733 group users manual 6C15 6.3.4 selectable functions the gate and pulse output functions are described below. (1) gate function the gate function is selected by setting the gate function selection bits (bits 4 and 3 at addresses 56 16 to 5a 16 ) to 10 2 or 11 2 . when the gate function is selected, counting can be started or stopped by pin tai ins input signal. table 6.3.3 lists the count valid levels. figure 6.3.5 shows an operation example when the gate function is selected. when selecting the gate function, set the port p5 and port p6 direction registers bits which correspond to pin tai in for the input mode. also make sure that pin tai in s input signal has a pulse width equal to or greater than two cycles of the count source. table 6.3.3 count valid levels 6.3 timer mode count valid level (duration of counting) while pin tai in s input signal level is l while pin tai in s input signal level is h note: the counter does not count while pin tai in s input signal is not at the count valid level. b4 1 1 b3 0 1 gate function selection bits
timer a 7733 group users manual 6C16 6.3 timer mode fig. 6.3.5 operation example when gate function is selected ffff 16 n 0000 16 time count start flag timer ai interrupt request bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when an interrupt request is accepted; otherwise, cleared by software pin tai in s input signal count valid level counting is stopped. counting is started. 0 0 counting is performed while the count start flag = 1 and pin tai in s input signal is at the count valid level. counter stops counting while pin tai in s input signal is not at the count valid level, and counter value is retained. set to 1 by software
timer a 7733 group users manual 6C17 (2) pulse output function the pulse output function is selected by setting the pulse o utput function selection bit (bit 2 at addresses 56 16 to 5a 16 ) to 1. when this function is selected, pin tai out is forcibly set as the pulse output pin independent of the corresponding bits of the port p5 and port p6 direction registers. and then, pin tai out outputs the signal of which polarity is inverted each time an underflow occurs. when the count start flag (address 40 16 ) = 0, in other words, when counting is stopped, pin tai out outputs l level. figure 6.3.6 shows an operation example w hen the pulse output function is selected. 6.3 timer mode fig. 6.3.6 operation example when pulse output function is s elected counting is stopped. counting is restarted. ffff 16 n 0000 16 time count start flag pulse output from pin tai out 1 counter contents (hex.) n = reload registers contents cleared to 0 when an interrupt request is accepted; otherw ise, cleared by software set to 1 by software counting is started. 0 timer ai interrupt request bit 1 0 set to 1 by software 1 0 cleared to 0 by software
timer a 7733 group users manual 6C18 [precautions in timer mode] while counting is in progress, by reading out the timer ai register, the counter value can be read at an arbitrary timing. however, when reading is performed at the reload timing shown in figure 6.3.7, value ffff 16 is read out. if reading is performed in the period from when a value is set into the timer ai register with the counter stopped until the counter starts counting, the set value is correctly read out. 6.3 timer mode fig. 6.3.7 timer ai register read out 210 n n ?1 counter value (hex.) 210 ffff n ?1 read value (hex.) reload time n = reload register? contents
timer a 7733 group users manual 6C19 6.4 event counter mode (bits 1 and 0 of timer ai mode register = 01 2 ) in this mode, an external signal is counted. (refer to tables 6.4.1 and 6.4.2. ) figures 6.4.1 and 6.4.2 show the structures of the timer ai mode register and timer ai register in the event counter mode. table 6.4.1 specifications of event counter mode (when not using two-phase pulse signal processing function) 6.4 event counter mode specifications l external signal input to pin tai in l falling edge or rising edge can be selected as the valid edge of the count source by software. l countup or countdown can be selected by the external signal or software l at an overflow or underflow, the reload registers contents is reloaded, and counting is continued (note) . item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing pin tai in s function pin tai out s function read from timer write to timer when the count start flag is set to 1. when the count start flag is cleared to 0. at an overflow or underflow count source input programmable i/o port, pulse output, or countup/countdown switch signal input a counter value can be read out by reading the timer ai register. n while counting is stopped when a value is written to the timer ai register, it is written to both of the reload register and counter. n while counting is in progress when a value is written to the timer ai register, it is written only to the reload register. (transferred to the counter at the next reload time.) < while counting up> < while counting down> 1 (n + 1) 1 (ffff 16 C n + 1) n: set value in the timer ai register note: this is applied when not using the free-run count function.
timer a 7733 group users manual 6C20 item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing pin taj in , taj out s (j = 2 to 4) function read from timer write to timer table 6.4.2 specifications of event counter mode (when using two-phase pulse signal processing function in timers a2, a3, and a4) specifications external signal (two-phase pulse) input to pin taj in or taj out (j = 2 to 4) l countup or countdown can be selected by the external signal (two-phase pulse). l at an overflow or underflow, the reload registers contents is reloaded, and counting is continued. (note) 6.4 event counter mode when the count start flag is set to 1. when the count start flag is cleared to 0. at an overflow or underflow two-phase pulse input a counter value can be read out by reading the timer a2, a3, or a4 register. n while counting is stopped when a value is written to the timer a2, a3, or a4 register, it is written to both of the reload register and counter. n while counting is in progress when a value is written to the timer a2, a3, or a4 register, it is written only to the reload register. (transferred to the counter at the next reload time.) < while counting up> < while counting down> 1 (n + 1) 1 (ffff 16 C n + 1) n: set value in the timer aj register note: this is applied when not using the free-run count function.
timer a 7733 group users manual 6C21 6.4 event counter mode fig. 6.4.1 structures of timer a0 and a1 mode registers and timer a0 and a1 registers in event counter mode timer a0 mode register (address 56 16 ) timer a1 mode register (address 57 16 ) b7 b6 b5 b4 b3 b2 b1 b0 5 00 1 bit 4 up-down switching factor selection bit 3 count polarity selection bit bit name 6 these bits are ignored in the event counter mode. 5 must be fixed to 0 in the event counter mode. 7 functions 0: counts at falling edge of external signal 1: counts at rising edge of external signal 0: contents of the up-down flag 1: a signal which is input to pin ta0 out or ta1 out at reset 0 0 0 0 0 rw 2 pulse output function selection bit 0 operating mode selection bits 1 0: no pulse is output. (pin ta0 out or ta1 out functions as a programmable i/o port.) 1: pulse is output. (pin ta0 out or ta1 out functions as a pulse output pin.) 0 1: event counter mode b1 b0 0 0 0 b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (ffff 16 C n + 1) in up- counting. at reading this register, the counter value is read out. undefined bit functions at reset rw rw rw rw rw rw rw rw rw 5
timer a 7733 group users manual 6C22 6.4 event counter mode fig. 6.4.2 structures of timer a2, a3, and a4 mode registers and timer a2, a3, and a4 registers in event counter mode b7 b6 b5 b4 b3 b2 b1 b0 timer a2 mode register (address 58 16 ) timer a3 mode register (address 59 16 ) timer a4 mode register (address 5a 16 ) 00 1 bit 4 up-down switching factor selection bit 0 operating mode selection bits bit name 6 count type selection bit 5 must be fixed to 0 in the event counter mode. note: this bit is valid only for the timer a3 mode register. for the timer a2 and a4 mode registers, this bit i s ignored. (it may be 0 or 1.) 1 7 two-phase pulse signal processing type selection bit (note) functions 0 1: event counter mode b1 b0 0: contents of the up-down flag 1: a signal which is input to pin ta2 out , ta3 out , or ta4 out at reset 0 0 0 0 0 0 rw 2 pulse output function selection bit 0: no pulse is output. (pin ta2 out , ta3 out , or ta4 out functions as a programmable i/o port.) 1: pulse is output. (pin ta2 out , ta3 out , or ta4 out functions as a pulse output pin.) 0 3 count polarity selection bit 0: counting is performed at the falling edge of the external signal. 1: counting is performed at the rising edge of the external signal. 0 0: reload count type 1: free-run count type 0: normal processing 1: quadruple processing b7 b0 b7 b0 (b15) (b8) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (ffff 16 C n + 1) in up-counting. at reading this register, the counter value is read out. undefined timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw rw rw rw rw rw rw rw rw
timer a 7733 group users manual 6C23 6.4.1 setting for event counter mode figure 6.4.3 and 6.4.4 show an initial setting example for r egisters related to the event counter mode. note that when using interrupts, setting for enabling interr upts is required. for details, refer to chapter 4. interrupts. 6.4 event counter mode fig. 6.4.3 initial setting example for registers related to event counter mode (1) h counter divides the count source frequency by (n + 1) while counting down or by (ffff 16 C n + 1) while counting up. setting of the up-down flag b7 b0 timer a0 up-down flag continued to initial setting example for registers related to event coun ter mode (2) on the next page b7 b0 two-phase pulse signal processing type selection bit (valid only for i = 3) 0: normal processing 1: quadruple processing 01 0 selection of the event counter mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) pulse output function selection bit 0: no pulse is output. 1: pulse is output. count polarity selection bit 0: counts at falling edge of external signal. 1: counts at rising edge of external signal. up-down switching factor selection bit 0: contents of the up-down flag 1: input signal to pin tai out count type selection bit (valid only for i = 2 to 4) 0: reload count type 1: free-run count type event counter mode is selected. setting of the division ratio b7 b0 values 0000 16 to ffff 16 (n) can be set. (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) up-down flag (address 44 16 ) ?when up-down flag is selected as up-down switching factor, set corresponding up-down flag. 0: countdown 1: countup ?selection of the two-phase pulse signal processing function set the corresponding bit to 1. 0: two-phase pulse signal processing function is disabl ed. 1: two-phase pulse signal processing function is enable d. timer a1 up-down flag timer a2 up-down flag timer a3 up-down flag timer a4 up-down flag timer a2 two-phase pulse signal processing selection bit timer a3 two-phase pulse signal processing selection bit timer a4 two-phase pulse signal processing selection bit
timer a 7733 group users manual 6C24 6.4 event counter mode fig. 6.4.4 initial setting example for registers related to event counter mode (2) aaa aaa aaa counting is started. setting of the count start flag to ? b7 b0 count start flag (address 40 16 ) timer a0 count start flag timer a1 count start flag timer a2 count start flag continued from ?nitial setting example for registers related to event counter mode (1) on the preceding page timer a3 count start flag timer a4 count start flag setting of the port p5 and port p6 direction registers b7 b0 port p5 direction register (address d 16 ) pin ta0 out pin ta0 in pin ta1 out pin ta1 in b7 b0 port p6 direction register (address 10 16 ) pin ta4 out set a bit corresponding to pin tai in to ?. when the two-phase pulse signal processing function is selected, or when pin tai out ? input signal is selected as the up-down switching factor, set a bit corresponding to pin tai out to ?. pin ta2 out pin ta2 in pin ta3 out pin ta3 in pin ta4 in setting of the interrupt priority level b7 b0 timer ai interrupt control register (addresses 75 16 to 79 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set.
timer a 7733 group users manual 6C25 6.4.2 operation in event counter mode when the count start flag is set to 1, the counter starts counting of the count source. the counter counts the count sources valid edges. a when an underflow or overflow occurs, the reload registers contents is reloaded, and then counting is continued. ? the timer ai interrupt request bit is set to 1 when the underflow or overflow occurs in a . after this, the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 6.4.5 shows an operation example in the event counter mode. 6.4 event counter mode fig. 6.4.5 operation example in event counter mode (without free-run count function, pulse output function, and two-phase pulse signal processing function) timer ai interrupt request bit ffff 16 n 0000 16 time count start flag ? ? counter contents (hex.) n = reload register? contents cleared to ??when an interrupt request is accepted; otherwise, cleared by software set to ??by software counting is started. up-down flag ? h the above is applied when the up-down flag? content is selected as the up-down switching factor (i.e., up-down switching factor selection bit = ??. ? ? ? set to ??by software
timer a 7733 group users manual 6C26 (1) switching between countup and countdown a register named up-down flag (address 44 16 ) or pin tai out s input signal switches countup from and to countdown. this switching is performed by an up-down flag when the up-down switching factor selection bit (bit 4 at addresses 56 16 to 5a 16 ) = 0 and by pin tai out s input signal when the up-down switching factor selection bit = 1. when the switching between countup and countdown is set whil e counting is in progress, this switching is realized at the next valid edge of the count source. n when switching by up-down flag countdown is performed when the up-down flag = 0, and coun tup is performed when the up-down flag = 1. figure 6.4.6 shows the structure of the up-down flag. n when switching by pin tai out s input signal countdown is performed when pin tai out s input signal level is l and countup is performed when it is h. when switching countup from and to countdown by pin tai out s input signal, set a port p5 or p6 direction registers bit which corresponds to pin tai out for the input mode. 6.4 event counter mode fig. 6.4.6 structure of up-down flag bit bit name at reset 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 up-down flag (address 44 16 ) 0 0 0 4 timer a4 up-down flag 3 timer a3 up-down flag 2 timer a2 up-down flag 1 timer a1 up-down flag 0 timer a0 up-down flag 5 timer a2 two-phase pulse signal processing selection bit 6 timer a3 two-phase pulse signal processing selection bit 7 timer a4 two-phase pulse signal processing selection bit 0: countdown 1: countup this bits is valid when the contents of the up-down flag is selected as the up-down switching factor. 0: two-phase pulse signal processing function is disabled. 1: two-phase pulse signal processing function is enabled. when not using the two-phase pulse signal processing function, be sure to set this bit to 0. this bit is 0 at reading. rw rw rw rw rw wo wo wo note: when writing to bits 5 to 7, use the ldm or sta instruction.
timer a 7733 group users manual 6C27 6.4.3 selectable functions the free-run count, pulse output, and two-phase pulse signal processing functions are described below. (1) free-run count function (timers a2 to a4) for timers a2 to a4, when the count type selection bit (bit 6 at addresses 58 16 to 5a 16 ) is set to 1, the free-run count function is selected. when the free-run c ount function is selected, although a timer a2/a3/a4 interrupt request is generated at an overflow or un derflow, the reload registers contents is not reloaded into the counter. figure 6.4.7 shows an operation example when the free-run co unt function is selected. 6.4 event counter mode fig. 6.4.7 operation example when free-run count function is selected (without pulse output function and two-phase pulse signal processing function) ffff 16 n 0000 16 time count start flag timer a2/a3/a4 interrupt request bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when an interrupt request is accepted; otherw ise, cleared by software set to 1 by software counting is started. up-down flag 1 0 0 0 h the above is applied when the up-down flags contents is se lected as the up-down switching factor (i.e., up-down switching factor selection bit = 0). set to 1 by software after an underflow, counter starts counting from ffff 16 . after an overflow, counter starts counting from 0000 16 .
timer a 7733 group users manual 6C28 (2) pulse output function the pulse output function is selected by setting the pulse output function selection bit (bit 2 at addresses 56 16 to 5a 16 ) to 1. when this function is selected, pin tai out is forcibly set as the pulse output pin independent of the corresponding bit of the port p5 or port p6 direction register. and then, pin tai out outputs a signal of which polarity is inverted each time an underflow or overflow occurs (refer to figure 6.3.6 ). when the count start flag (address 40 16 ) = 0, in other words, when counting is stopped, pin tai out outputs l level. (3) two-phase pulse signal processing function (timers a2 to a4) for timers a2 to a4, the two-phase pulse signal processing function is selected by setting the two- phase pulse signal processing selection bits (bits 5 to 7 at address 44 16 ) to 1. (refer to figure 6.4.6. ) figure 6.4.8 shows the timer a2, a3, and a4 mode registers when the two-phase pulse signal processing function is selected. in a timer with the two-phase pulse signal processing function selected, two kinds of pulses of which phases differ by 90 degrees are counted. there are two types of the two-phase pulse signal processing: normal processing and quadruple processing. in timer a2, normal processing is performed; in timer a4, quadruple processing is performed. in timer a3, either normal processing or quadruple processing can be selected by the two-phase pulse signal processing type selection bit (bit 7 at address 59 16 ). some bits of the port p5 and p6 direction registers correspond to pins used for the two-phase pulse input. set these bits for the input mode. 6.4 event counter mode 1 00001 timer a2 mode register (address 58 16 ) timer a3 mode register (address 59 16 ) timer a4 mode register (address 5a 16 ) 0: reload count type 1: free-run count type b7 b6 b5 b4 b3 b2 b1 b0 h h : bit 7 of the timer a3 mode register is used to select the two-phase pulse signal processing type of timer a3. normal processing is selected when this bit = ?,?and quadruple processing is selected when this bit = ?. bit 7 of the timer a2/a4 mode register is ignored. (it may be ??or ?.? fig. 6.4.8 timer a2, a3, and a4 mode registers when two-phase pulse signal processing function is selected
timer a 7733 group users manual 6C29 6.4 event counter mode n normal processing countup is performed at the rising edges of pin tak in (k = 2 and 3) if the phase relationship is such that pin tak in s input signal level changes from l to h while pin tak out s input signal level is h. countdown is performed at the falling edges of pin tak in if the phase relationship is such that pin tak in s input signal level changes from h to l while pin tak out s input signal level is h. (refer to figure 6.4.9 .) fig. 6.4.9 normal processing n quadruple processing countup is performed at the rising and falling edges of pins tai out (l = 3 and 4) and tai in if the phase relationship is such that pin tai in s input signal level changes from l to h while pin tai out s input signal level is h. countdown is performed at the rising and falling edges of pins tai out and tai in if the phase relationship is such that pin tai in s input signal level changes from h to l while pin tai out s input signal level is h. (refer to figure 6.4.10 .) table 6.4.3 lists input signals of pins tai out and tai in when the quadruple processing is selected. fig. 6.4.10 quadruple processing tal out tal in (l = 3, 4) ? ? ? ? +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 counted up at all edges ? ? ? ? ? ? ? ? ? ? counted down at all edges counted up at all edges counted down at all edges tak out tak in (k = 2, 3) ? ? ? +1 +1 +1 ? ? ? counted down ? counted up counted up counted up counted down counted down
timer a 7733 group users manual 6C30 table 6.4.3 pin tai out and tai in s input signals when quadruple processing is selected 6.4 event counter mode countup countdown input signal of pin tai in rising edge falling edge l level h level falling edge rising edge h level l level input signal of pin tai out h level l level rising edge falling edge h level l level rising edge falling edge
timer a 7733 group users manual 6C31 [precautions in event counter mode] 1. while counting is in progress, by reading out the timer ai register, the counter value can be read at an arbitrary timing. however, when reading is performed at the reload timing shown in figure 6.4.11, value ffff 16 is read out at an underflow and value 0000 16 is read out at an overflow. if reading is performed in the period from when a value is set into the timer ai register with the counter stopped until the counter starts counting, the set value is correctly read out. 6.4 event counter mode fig. 6.4.11 timer ai register read out 2. pin tai out is used for all functions listed below. therefore, only one of the following functions can be used for one timer. l switching between countup and countdown by pin tai out s input signal l pulse output function l two-phase pulse signal processing function (timers a2 to a4) 210 n n ?1 counter value (hex.) 210 ffff n ?1 read value (hex.) reload time n = reload register? contents (1) while counting down fffd fffe ffff n n + 1 fffd fffe ffff 0000 n + 1 (2) while counting up counter value (hex.) read value (hex.) reload time n = reload register? contents
timer a 7733 group users manual 6C32 6.5 one-shot pulse mode (bits 1 and 0 of timer ai mode register = 10 2 ) in this mode, a pulse which has an arbitrary width is output once. (refer to table 6.5.1 .) after a trigger occurs, h level is output from pin tai out for an arbitrary time. figure 6.5.1 shows the structures of the timer ai mode register and timer ai register in the one-shot pulse mode. table 6.5.1 specifications of one-shot pulse mode 6.5 one-shot pulse mode item count source count operation output pulse width (h) count start condition count stop condition interrupt request occurrence timing pin tai in s function pin tai out s function read from timer write to timer specifications clock f 2 , f 16 , f 64 , or f 512 l countdown l when the counter value reaches 0000 16 , the reload registers contents is reloaded, and counting stops. l when a trigger occurs while counting is in progress, the reload registers contents is reloaded, and counting is continued. n fi n: set value in the timer ai register l when a trigger occurs. ( note ) l internal or external trigger can be selected by software. l when the counter value reaches 0000 16 . l when the count start flag is cleared to 0. when counting stops. programmable i/o port or trigger input one-shot pulse output an undefined value is read out by reading the timer ai register. n while counting is stopped when a value is written to the timer ai register, it is written to both of the reload register and counter. n while counting is in progress when a value is written to the timer ai register, it is written only to the reload register. (transferred to the counter at the next reload time.) [s] clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. note: a trigger occurs when the count start flag = 1.
timer a 7733 group users manual 6C33 6.5 one-shot pulse mode fig. 6.5.1 structures of timer ai mode register and timer ai register in one-shot pulse mode b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, h level width of the one-shot pulse output from pin tai out is n/fi. undefined fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) 3 trigger selection bits 2 must be fixed to 1 in the one-shot pulse mode. 1 0 operating mode selection bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 1 0: one-shot pulse mode 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 6 count source selection bits b1 b0 b4 b3 5 must be fixed to 0 in the one-shot pulse mode. 10 1 clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. 0 x: writing 1 to the one-shot start flag (pin tai in functions as a programmable i/o ?@ ?@ ?@ port.) 1 0: falling edge of the pin tai in s input signal 1 1: rising edge of the pin tai in s input signal bit at reset 0 0 0 0 0 0 0 0 rw 0 4 rw rw rw rw rw rw rw rw wo
timer a 7733 group users manual 6C34 6.5.1 setting for one-shot pulse mode figures 6.5.2 and 6.5.3 show an initial setting example for registers related to the one-shot pulse mode. note that when using interrupts, setting for enabling interr upts is required. for details, refer to chapter 4. interrupts. 6.5 one-shot pulse mode fig. 6.5.2 initial setting example for registers related to one-shot pulse mode (1) continued to initial setting example for registers related to one-shot p ulse mode (2) on the next page setting of the interrupt priority level b7 b0 timer ai interrupt control register (addresses 75 16 to 79 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set. b7 b0 10 0 selection of the one-shot pulse mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 1 b4 b3 trigger selection bits 0 x: writing 1 to the one-shot start flag: internal trigge r 1 0: falling edge of pin tai in s input signal: external trigger 1 1: rising edge of pin tai in s input signal: external trigger b7 b6 count source selection bits 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 x: it may be 0 or 1. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. one-shot pulse mode is selected. setting of the one-shot pulses h level width b7 b0 values 0000 16 to ffff 16 (n) can be set. (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) h h level width = n/fi fi = frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) however, if n = 0000 16 , the counter does not operate and pin tai out outputs l level. at this time, no timer ai interrupt request is generated.
timer a 7733 group user? manual 6?5 6.5 one-shot pulse mode fig. 6.5.3 initial setting example for registers related to one-shot pulse mode (2) counting is started. trigger is generated. trigger input to pin tai in when the internal trigger is selected when the external trigger is selected continued from ?nitial setting example for registers related to one-shot p ulse mode (1) on the preceding page b7 b0 one-shot start flag (address 42 16 ) setting of one-shot start flag to ? timer a0 one-shot start flag setting of count start flag to ? b7 b0 timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag count start flag (address 40 16 ) b7 b0 port p5 direction register (address d 16 ) setting of port p5 and port p6 direction registers pin ta0 in pin ta1 in pin ta2 in pin ta3 in port p6 direction register (address 10 16 ) pin ta4 in b7 b0 clear the corresponding bit to ?. setting of count start flag to ? b7 b0 timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag count start flag (address 40 16 ) timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag
timer a 7733 group users manual 6C36 6.5.2 count source in the one-shot pulse mode, by the count source selection bits (bits 7 and 6 at addresses 56 16 to 5a 16 ), a count source can be selected. table 6.5.2 lists the relationship between the count source selection bits and count source. table 6.5.2 relationship between count source selection bits and count source 6.5 one-shot pulse mode count source f 2 f 16 f 64 f 512 b7 0 0 1 1 b6 0 1 0 1 frequency of count source when system clock = 25 mhz when system clock = 16 mhz when system clock = 8 mhz clocks f 2 , f 16 , f 64 , f 512 , and system clock: refer to chapter 14. clock generating circuit. note: the above is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0 and the main clock division selection bit (bit 0 at address 6f 16 ) = 0. (for details, refer to chapter 14. clock generating circuit. ) 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz 8 mhz 1 mhz 250 khz 31.25 khz 4 mhz 500 khz 125 khz 15.625 khz
timer a 7733 group users manual 6C37 6.5.3 trigger the counter enters the count enable state when the count sta rt flag (address 40 16 ) is set to 1. and then, the counter starts counting when a trigger occurs. an intern al or external trigger can be selected as this trigger. an internal trigger is selected when the trigger selection b its (bits 4 and 3 at addresses 56 16 to 5a 16 ) are 00 2 or 01 2 ; an external trigger is selected when the trigger selectio n bits are 10 2 or 11 2 . when a trigger occurs during counting, the reload registers contents is reloaded and the counter continues counting. when generating a trigger during counting, make su re that a certain time which is equivalent to two cycles of the timers count source or more has passed be tween the trigger previously generated and a new trigger. (1) when internal trigger is selected a trigger is generated when the one-shot start flag (address 42 16 ) is set to 1. figure 6.5.4 shows the structure of the one-shot start flag. (2) when external trigger is selected a trigger is generated at the falling edge of pin tai in s input signal when bit 3 at addresses 56 16 to 5a 16 = 0 or at the rising edge of pin tai in s input signal when bit 3 = 1. when using an external trigger, set the port p5 or p6 direct ion registers bit which corresponds to pin tai in s for the input mode. 6.5 one-shot pulse mode fig. 6.5.4 structure of one-shot start flag bit 7 to 5 not implemented. 4 timer a4 one-shot start flag 3 timer a3 one-shot start flag 2 timer a2 one-shot start flag 1 timer a1 one-shot start flag 0 timer a0 one-shot start flag bit name at reset 0 0 undefined 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 one-shot start flag (address 42 16 ) 1: one-shot pulse output is started. (valid when the internal trigger is selected). 0 at reading. wo wo wo wo wo C
timer a 7733 group users manual 6C38 6.5.4 operation in one-shot pulse mode when the one-shot pulse mode is selected by the operating mode selection bits, pin tai out outputs l level. when the count start flag is set to 1, the counter enters the count enable state, and then it starts counting if a trigger occurs. a when the counter starts counting, pin tai out s output level becomes h. (however, if value 0000 16 is set in the timer ai register, the counter does not operate and the output level of pin tai out remains l. nor is a timer ai interrupt request generated.) ? when the counter value reaches 0000 16 , the output level of pin tai out becomes l. and then, the reload registers contents is reloaded, and the counter stops counting. ? simultaneously with ? , a timer ai interrupt request bit is set to 1. after this, the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 6.5.5 shows an operation example in the one-shot pulse mode. when a trigger occurs after ? above, the counter and pin tai out perform the same operations beginning from again. when a trigger occurs during counting, the counter down-counts once after this new trigger occurs. and then, the reload registers contents is reloaded and counting is continued. when generating a trigger during counting, make sure that a certain time which is equivalent to two cycles of the timers count source or more has passed between the trigger previously generated and a new trigger. the one-shot pulse output from pin tai out can be disabled by clearing the timer ai mode registers bit 2 to 0. therefore, timer ai can be used as an internal one-shot timer that does not output the pulse. (in this case, pin tai out functions as a programmable i/o port.) 6.5 one-shot pulse mode
timer a 7733 group user? manual 6?9 6.5 one-shot pulse mode fig. 6.5.5 operation example in one-shot pulse mode (when ex ternal trigger selected) counting is stopped. counting is started. ffff 16 n 0001 16 time count start flag timer ai interrupt request bit ? ? counter contents (hex.) n = reload register? contents cleared to ??when an interrupt request is accepted; otherw ise, cleared by software set to ??by software counting is started. pin tai in ? input signal ? one-shot pulse output from pin tai out ? trigger during counting 1 / f i 5 (n) h the above is applied when an external trigger (rising edge of pin tai in ? input signal) is selected. ? ? ? ? 1 / f i 5 (n + 1) when the count start flag = ?,?in other words, when count ing is stopped, pin tai out outputs ??level. when a trigger occurs during counting, the counter counts t he count source (n + 1) times after a new trigger occurs. fi = frequency of count source (f 2 ,f 16 ,f 64 ,f 512 ) counting is stopped. reloaded reloaded
timer a 7733 group users manual 6C40 [precautions in one-shot pulse mode] 1. when the count start flag is cleared to 0 during counting, the followings are performed. ?the counter stops counting, and the reload registers contents is reloaded. ?pin tai out s output level becomes l. ?an interrupt request is generated, and a timer ai interrupt request bit is set to 1. 2. a one-shot pulse is output synchronously with an internally generated count source. therefore, when an external trigger is selected, in the period from when a trigger is input to pin tai in until a one-shot pulse is output, there will be a delay equivalent to one cycle of the count source at maximum. 6.5 one-shot pulse mode fig. 6.5.6 delay in one-shot pulse output 3. when a timers operating mode is set by the procedure listed below, a timer ai interrupt request bit is set to 1. l when the one-shot pulse mode is selected after reset l when the operating mode is switched from the timer mode to the one-shot pulse mode l when the operating mode is switched from the event counter mode to the one-shot pulse mode therefore, when using a timer ai interrupt (interrupt request bit), be sure to clear the timer ai interrupt request bit to 0 after setting the above. h the above is applied when an external trigger (falling edge of pin tai in ? input signal) is selected. pin tai in ? input signal ? ? count source trigger input one-shot pulse output is started. one-shot pulse output from pin tai out
timer a 7733 group users manual 6C41 6.6 pulse width modulation (pwm) mode (bits 1 and 0 of timer ai mode register = 11 2 ) in this mode, a pulse which has an arbitrary width is output in succession. (refer to table 6.6.1. ) figure 6.6.1 shows the structures of the timer ai mode register and timer ai register in the pwm mode. table 6.6.1 specifications of pwm mode 6.6 pulse width modulation (pwm) mode item count source count operation specifications clock f 2 , f 16 , f 64 , or f 512 l countdown (operates as an 8-bit or 16-bit pulse width modulator) l reload registers contents is reloaded at the rising edge of pwm pulse, and counting is continued. l a trigger generated during counting does not affect the counting. pwm period and h level width 2 16 C 1 fi period = [s] h level width = k fi [s] <8-bit pulse width modulator> <16-bit pulse width modulator> (m + 1)(2 8 C 1) fi period = h level width = n(m + 1) fi [s] [s] k: set value in the timer ai register m: set value in the low-order 8 bits of the timer ai register n: set value in the high-order 8 bits of the timer ai register count start condition count stop condition interrupt request occurrence timing pin tai in s function pin tai out s function read from timer write to timer l when a trigger occurs. l internal or external trigger can be selected by software. when the count start flag is cleared to 0. at the falling edge of pwm pulse programmable i/o port or trigger input pwm pulse output an undefined value is read out by reading the timer ai register. n while counting is stopped when a value is written to the timer ai register, it is written to both of the reload register and counter. n while counting is in progress when a value is written to the timer ai register, it is written only to the reload register. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit.
timer a 7733 group users manual 6C42 6.6 pulse width modulation (pwm) mode b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 6 count source selection bits 11 1 clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. at reset 0 0 0 0 0 0 0 0 rw 3 trigger selection bits 2 must be fixed to 1 in the pwm mode. 1 0 operating mode selection bits bit name functions 1 1: pwm mode b1 b0 b4 b3 5 16/8-bit pwm mode selection bit 0 x: writing 1 to the count start flag (pin tai in functions as a programmable i/o port.) 1 0: falling edge of the pin tai in s input signal 1 1: rising edge of the pin tai in s input signal bit 0: the counter operates as a 16-bit pulse width modulator. 1: the counter operates as an 8-bit pulse width modulator. 4 n when operating as an 8-bit pulse width modulator (b15) b7 b0 b7 b0 (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 7 to 0 values 00 16 to ff 16 can be set. assuming that the set value = m, period of the pwm pulse which is output from pin tai out is (m + 1)(2 8 C 1)/fi. fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) 15 to 8 values 00 16 to fe 16 can be set. assuming that the set value = n, h level width of the pwm pulse which is output from pin tai out is n(m +1)/fi. un- defined un- defined b7 b0 b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 values 0000 16 to fffe 16 can be set. assuming that the set value = n, h level width of the pwm pulse which is output from pin tai out is n/fi. un- defined fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) n when operating as a 16-bit pulse width modulator (b15) (b8) rw rw rw rw rw rw rw rw wo wo wo fig. 6.6.1 structures of timer ai mode register and timer ai register in pwm mode
timer a 7733 group user? manual 6?3 6.6.1 setting for pwm mode figures 6.6.2 and 6.6.3 show an initial setting example for registers related to the pwm mode. note that when using interrupts, setting for enabling interr upts is required. for details, refer to chapter ?. interrupts. 6.6 pulse width modulation (pwm) mode fig. 6.6.2 initial setting example for registers related to pwm mode (1) b7 b0 count source selection bits 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 11 selection of pwm mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) b7 b6 1 16/8-bit pwm mode selection bit 0: the counter operates as 16-bit pulse width modulator. 1: the counter operates as 8-bit pulse width modulator. continued to ?nitial setting example for registers related to pwm mode ( 2) on the next page trigger selection bits 0 x: writing ??to the count start flag: internal trigger 1 0: falling edge of pin tai in ? input signal: external trigger 1 1: rising edge of pin tai in ? input signal: external trigger b4 b3 x: it may be ??or ?. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter ?4. clock generating circuit. pwm mode selected setting of pwm pulse? period and ??level width b7 b0 values 0000 16 to fffe 16 (n) can be set. (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) h when operating as a 16-bit pulse width modulator period = (2 16 ?1)/fi fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) however, if n = 0000 16 , the pulse width modulator does not operate and pin tai out outputs ??level. at this time, no timer ai interrupt request is generated. n when operating as a 16-bit pulse width modulator b7 b0 values 00 16 to ff 16 (m) can be set. (b15) (b8) b7 b0 n when operating as an 8-bit pulse width modulator values 00 16 to fe 16 (n) can be set. h when operating as an 8-bit pulse width modulator period = (m+1) (2 8 ?1)/fi ??level width = n(m + 1)/fi fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) however, if n = 00 16 , the pulse width modulator does not operate and pin tai out outputs ??level. at this time, no timer ai interrupt request is generated. timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 )
timer a 7733 group users manual 6C44 6.6 pulse width modulation (pwm) mode fig. 6.6.3 initial setting example for registers related to pwm mode (2) aaa aaa aaa counting is started. trigger input to pin tai in when the external trigger is selected when the internal trigger is selected continued from ?nitial setting example for registers related to pwm mode (1) on the preceding page trigger is generated. b7 b0 port p5 direction register (address d 16 ) setting of the port p5 and port p6 direction registers pin ta0 in pin ta1 in pin ta2 in pin ta3 in pin ta4 in b7 b0 clear the corresponding bit to ?.? port p6 direction register (address 10 16 ) setting of the interrupt priority level b7 b0 timer ai interrupt control register (addresses 75 16 to 79 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set. setting of the count start flag to ? b7 b0 count start flag (address 40 16 ) timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag timer a0 count start flag setting of the count start flag to ? b7 b0 count start flag (address 40 16 ) timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag timer a0 count start flag
timer a 7733 group users manual 6C45 6.6.2 count source in the pwm mode, by the count source selection bits (bits 7 and 6 at addresses 56 16 to 5a 16 ), a count source can be selected. table 6.6.2 lists the relationship between the count source selection bits and count source. table 6.6.2 relationship between count source selection bits and count source 6.6 pulse width modulation (pwm) mode frequency of count source when system clock = 25 mhz when system clock = 16 mhz when system clock = 8 mhz count source f 2 f 16 f 64 f 512 b7 0 0 1 1 b6 0 1 0 1 clocks f 2 , f 16 , f 64 , f 512 , and system clock: refer to chapter 14. clock generating circuit. note: the above is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0 and the main clock division selection bit (bit 0 at address 6f 16 ) = 0. (for details, refer to chapter 14. clock generating circuit. ) 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz 8 mhz 1 mhz 250 khz 31.25 khz 4 mhz 500 khz 125 khz 15.625 khz
timer a 7733 group users manual 6C46 6.6.3 trigger when a trigger occurs, pin tai out starts the pwm pulse output. an internal or external trigger can be selected as this trigger. an internal trigger is selected when the trigger selection bits (bits 4 and 3 at addresses 56 16 to 5a 16 ) are 00 2 or 01 2 ; an external trigger is selected when the trigger selection bits are 10 2 or 11 2 . a trigger generated during pwm pulse output is invalid and does not affect the pulse output operation. (1) when internal trigger is selected a trigger is generated when the count start flag (address 40 16 ) is set to 1. (2) when external trigger is selected a trigger is generated at the falling edge of the pin tai in s input signal when bit 3 at addresses 56 16 to 5a 16 = 0 or at the rising edge of the pin tai in s input signal when bit 3 = 1. however, a trigger input is accepted only when the count start flag = 1. when using an external trigger, set the port p5 or p6 direction registers bit which corresponds to pin tai in for the input mode. 6.6 pulse width modulation (pwm) mode
timer a 7733 group users manual 6C47 6.6.4 operation in pwm mode when the pwm mode is selected by the operating mode selection bits, pin tai out outputs l level. when a trigger occurs, the counter (pulse width modulator) starts counting and pin tai out outputs a pwm pulse ( notes 1 and 2 ). a a timer ai interrupt request bit is set to 1 each time the pwm pulse level changes from h to l. after this, the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. ? each time a pwm pulse is output for one period, the reload registers contents is reloaded and counting is continued. operation of the pulse width modulator is described below. [16-bit pulse width modulator] when the 16/8-bit pwm mode selection bit is set to 0, the counter operates as a 16-bit pulse width modulator. each of figures 6.6.4 and 6.6.5 shows an operation example of the 16-bit pulse width modulator. [8-bit pulse width modulator] when the 16/8-bit pwm mode selection bit is set to 1, the counter is divided into 8-bit halves. then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit prescaler. each of figures 6.6.6 and 6.6.7 shows an operation example of the 8-bit pulse width modulator. notes 1: if a value of 0000 16 is set in the timer ai register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output level of pin tai out remains l. nor is a timer ai interrupt request generated. these operations are also applied to the case where a value of 00 16 is set in high-order 8 bits of the timer ai register when the counter operates as an 8-bit pulse width modulator. 2: when the counter operates as an 8-bit pulse width modulator, after a trigger occurs, pin tai out outputs l level of which width is the same as the pwm pulses h level width which was set. and then, pin tai out starts the pwm pulse output. 6.6 pulse width modulation (pwm) mode
timer a 7733 group users manual 6C48 6.6 pulse width modulation (pwm) mode fig. 6.6.4 operation example of 16-bit pulse width modulator fig. 6.6.5 operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 1 / f i 5 (2 16 1) 1 / f i 5 (n) count source pin tai in ? input signal pwm pulse output from pin tai out h the above is applied when the reload register = 0003 16 and an external trigger (rising edge of pin tai in ? input signal) is selected. trigger is not generated by this signal. ? ? ? ? timer ai interrupt request bit ? ? cleared to ??when an interrupt request is accepted; otherwise, cleared by software fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) pwm pulse output from pin tai out when an arbitrary value is reset to the timer ai register after value ?000 16 ?is set to it, the rising timing of pwm pulse depends on this reset timing. h the above is applied when an external trigger (rising edge of pin tai in ? input signal) is selected. fffe 16 n 0001 16 pin tai in ? input signal ? counter contents (hex.) ? ? ? (1 / f i ) 5 (2 16 ?1) (2 16 ?1) ?n (1 / f i ) 5 (2 16 ?1) value ?000 16 ?is set to the timer ai register. value ?000 16 ?is set to the timer ai register. 2000 16 value ?ffe 16 ?is set to the timer ai register. n = reload register? contents fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) counting is restarted. counting is stopped. time (1 / f i ) 5 (2 16 ?1)
timer a 7733 group user? manual 6?9 6.6 pulse width modulation (pwm) mode fig. 6.6.6 operation example of 8-bit pulse width modulator count source pin tai in ? input signal 1 / f i 5 (m + 1) 5 (2 8 ?1) 1 / f i 5 (m + 1) 5 (n) pwm pulse output from pin tai out h the above is applied when the following conditions are sati sfied: ?eload register? high-order 8 bits = ?2 16 ?eload register? low-order 8 bits = ?2 16 ?hen an external trigger (falling edge of pin tai in ? input signal) is selected. ? ? ? ? ? ? ? ? timer ai interrupt request bit cleared to ??when an interrupt request is accepted; otherw ise, cleared by software fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) 8-bit prescaler counts the count source. 8-bit pulse width modulator counts the 8-bit prescaler? un derflow signal. 8-bit prescaler? underflow signal 1 / f i 5 (m + 1)
timer a 7733 group user? manual 6?0 6.6 pulse width modulation (pwm) mode fig. 6.6.7 operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) ? ? ? ? (1 / f i ) 5 (m + 1) 5 (2 8 ?1) pwm pulse output from pin tai out count source pin tai in ? input signal (1 / f i ) 5 (m + 1) 5 (2 8 ?1) (1 / f i ) 5 (m + 1) 5 (2 8 ? 1) 00 16 prescaler contents (hex.) 02 16 time counting is stopped. 01 16 counter contents (hex.) 04 16 0a 16 time when an arbitrary value is reset to the timer ai register a fter value ?0 16 ?is set to the timer ai register? high-order 8 bits, the r ising timing of the pwm pulse depends on this reset timing. value ?002 16 ?is set to the timer ai register. value ?a02 16 ?is set to the timer ai register. value ?402 16 ?is set to the timer ai register. counting is restarted. h the above is applied when an external trigger (falling edge of pin tai in ? input signal) is selected. f i : frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) m: contents of the reload register? low-order 8 bits
timer a 7733 group users manual 6C51 [precautions in pwm mode] 1. when the count start flag is cleared to 0 while a pwm pulse is output, the counter stops counting. at this time, if pin tai out outputs h level, the output level becomes l and a timer ai interrupt request bit is set to 1. if pin tai out outputs l level, the output level does not change and a timer ai interrupt request is not generated. 2. when a timers operating mode is set by the procedure listed below, a timer ai interrupt request bit is set to 1. l when the pwm mode is selected after reset l when the operating mode is switched from the timer mode to the pwm mode l when the operating mode is switched from the event counter mode to the pwm mode therefore, when using a timer ai interrupt (interrupt request bit), be sure to clear the timer ai interrupt request bit to 0 after setting the above. 6.6 pulse width modulation (pwm) mode
timer a 7733 group users manual 6C52 6.6 pulse width modulation (pwm) mode memo
chapter 7 chapter 7 timer b 7.1 overview 7.2 block description 7.3 timer mode 7.4 event counter mode 7.5 pulse period/pulse width measurement mode 7.6 clock timer
timer b 7733 group users manual 7C2 7.1 overview timer b consists of three counters (timers b0 to b2), and each has a 16-bit reload function. timers b0 to b2 operate independently of each other. timer bi (i = 0 to 2) has three operating modes listed below. furthermore, timer b2 can function as a clock timer. except that timer b2 functions as a clock timer and timer b1 has an internal connect function, timers b0 to b2 have the same functions. n timer mode timer b counts a count source internally generated. n event counter mode timer b counts an external signal, and the following functions can be used: l internal connect function (timer b1 only) n pulse period/pulse width measurement mode timer b measures an external signals pulse period/pulse width. n clock timer (timer b2) 7.1 overview
timer b 7733 group users manual 7C3 7.2 block description figure 7.2.1 shows the timer b block diagram. registers related to timer b are described below. fig. 7.2.1 timer b block diagram f 2 f 16 f 64 f 512 clock source selection ?imer mode ?ulse period/pulse width measurement mode polarity switching and edge pulse generating circuit event counter mode count start flag counter reset circuit data bus (odd) data bus (even) (low-order 8 bits) (high-order 8 bits) timer bi reload register (16) timer bi counter (16) timer bi interrupt request bit tbi in (i = 0 to 2) timer bi overflow flag fc 32 (note 1) tb2 overflow signal (note 2) (address 40 16 ) addresses timer b0 51 16 50 16 timer b1 53 16 52 16 timer b2 55 16 54 16 notes 1: clock source for clock timer can be selected only for tb2 (refer to figure 14.3.1. ) 2: can be selected only for tb1 (internal connect mode) clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter ?4. clock generating circuit. 7.2 block description
timer b 7733 group users manual 7C4 7.2.1 counter and reload register (timer bi register) each of timer bi counter and its reload register consists of 16 bits and has the following functions. (1) functions in timer mode, event counter mode, and clock timer the counter performs countdown each time a count source is input. the reload register is used to memorize the initial value of a counter. when an underflow occurs in the counter, the reload registers contents is reloaded into the counter. values are set to the counter and reload register by writing the values to the timer bi register. table 7.2.1 lists the memory allocation of the timer bi register. a value written into the timer bi register while counting is stopped is set to the counter and reload register. a value written into the timer bi register while counting is in progress is set only to the reload register. in this case, the reload registers updated contents is transferred to the counter when the next underflow occurs. a value obtained by reading out the timer bi register is the counter value. note: perform reading or writing from/to the timer bi register by the 16 bits. for a value read from the timer bi register, refer to precautions in timer mode and precautions in event counter mode. (2) functions in pulse period/pulse width measurement mode the counter performs countup each time a count source is input. the reload register is used to hold the pulse period or pulse width measurement result. when a valid edge is input to pin tbi in , the counter value is transferred to the reload register. in this mode, a value obtained by reading out the timer bi register is the reload registers contents, and the measurement result can be obtained. note: perform reading from the timer bi register by the 16 bits. low-order byte address 50 16 address 52 16 address 54 16 high-order byte address 51 16 address 53 16 address 55 16 timer bi register timer b0 register timer b1 register timer b2 register note: at reset, the contents of the timer bi register is undefined. table 7.2.1 memory allocation of timer bi register 7.2 block description
timer b 7733 group users manual 7C5 7.2.2 count start flag this register is used to start or stop counting. each bit of this register corresponds to each timer, respectively. figure 7.2.2 shows the structure of the count start flag. fig. 7.2.2 structure of count start flag bit 7 timer b2 count start flag 6 timer b1 count start flag 5 timer b0 count start flag 4 timer a4 count start flag 3 timer a3 count start flag 2 timer a2 count start flag 1 timer a1 count start flag 0 timer a0 count start flag bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 count start flag (address 40 16 ) 0: counting is stopped. 1: counting is started. represents that bits 0 to 4 are not used for timer b. rw rw rw rw rw rw rw rw 7.2 block description
timer b 7733 group users manual 7C6 7.2.3 timer bi mode register figure 7.2.3 shows the structure of the timer bi mode register. the operating mode selection bits are used to select an operating mode of timer bi. bits 7 to 5 and bits 3 and 2 have different functions according to the operating mode. these bits are described in a section of each operating mode. fig. 7.2.3 structure of timer bi mode register rw rw rw rw rw rw rw bit 7 ?@ 4 must be fixed to ??(i = 0). 3 ?@ 1 bit name at reset 0 0 0 0 un- defined 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 0 0: timer mode 0 1: event counter mode 1 0: pulse period/pulse width measurement mode 1 1: do not select. b1 b0 2 these bits have different functions according to the operating mode. 0 operating mode selection bits 6 note: in the timer and event counter modes, bit 5 is ignored and undefined at reading. 5 these bits have different functions according to the operating mode. not implemented (i = 1, 2). 0 un- defined ro (note) 7.2 block description
timer b 7733 group users manual 7C7 7.2.4 timer bi interrupt control register figure 7.2.4 shows the structure of the timer bi interrupt control register. for details about interrupts, refer to chapter 4. interrupts fig. 7.2.4 structure of timer bi interrupt control register (1) interrupt priority level selection bits (bits 2 to 0) these bits select a timer bi interrupts priority level. when using timer bi interrupts, select one priority level from levels 1 to 7. if a timer bi interrupt request is generated, its priority level is compared with the processor interrupt priority level (ipl), and then the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this is applied when the interrupt disable flag (i) = 0.) when disabling timer bi interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when a timer bi interrupt request is generated. this bit is automatically cleared to 0 when the timer bi interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software. at reset bit 7 to 4 not implemented. 2 1 0 interrupt priority level selection bits bit name un- defined 0 0 0 0 rw functions 0 0 0: level 0 (interrupt is disabled.) 0 0 1: level 1 priority is low. 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 priority is high. b2 b1 b0 0: no interrupt request has occurred. 1: interrupt request has occurred. b7 b6 b5 b4 b3 b2 b1 b0 timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) rw rw rw rw 3 interrupt request bit 7.2 block description
timer b 7733 group users manual 7C8 7.2.5 port p6 direction register i/o pins of timer bi are multiplexed with port p6. when usin g these pins as timer bis input pins, set the corresponding bits of the port p6 direction register to 0 in order to set these ports for the input mode. figure 7.2.5 shows the relationship between the port p6 dire ction register and the timer bis input pins. fig. 7.2.5 relationship between port p6 direction register a nd timer bis input pins at reset bit corresponding pin name functions 0 1 2 3 4 5 6 7 pin p6 0 /ta4 out pin p6 2 / int 0 pin p6 3 / int 1 pin p6 4 / int 2 pin p6 6 /tb1 in pin p6 5 /tb0 in port p6 direction register (address 10 16 ) b1 b0 b2 b3 b4 b5 b6 b7 pin p6 1 /ta4 in pin p6 7 /tb2 in / sub 0 0 0 0 0 0 0 0 0: input mode 1: output mode when using these pins as timer bis input pins, set the corresponding bits to 0. represents that bits 0 to 4 are not used for timer b. rw rw rw rw rw rw rw rw rw 7.2 block description
timer b 7733 group users manual 7C9 7.2.6 port function control register figure 7.2.6 shows the structure of the port function contro l register. notes 1: when the port-xc selection bit = 0 and timer b2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: when timer b1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 and 3 to 7 are not used for t imer b. port-xc selection bit ] : bit 4 of the oscillation circuit control register 0 (addr ess 6c 16 ) bit functions b7 b6 b5 b4 b3 b2 b1 b0 port function control register (address 6d 16 ) bit name 0: pins p0 to p3 are used for the external bus output. 1: pins p0 to p3 are used for the port output. 0 standby state selection bit 1 sub-clock output selection bit/ timer b2 clock source selection bit 0: no internal connection 1: internal connection with timer b2 2 timer b1 internal connect selection bit 3 port p6 pull-up selection bit 0 0: no pull-up for pins p5 4 /ta2 out /ki 0 to p5 7 /ta3 in /ki 3 1: with pull-up for pins p5 4 /ta2 out /ki 0 to p5 7 /ta3 in /ki 3 6 port p5 pull-up selection bit 7 key input interrupt selection bit 0: int 2 interrupt (ta2 in and ta3 in inputs are assigned to pins p5 5 and p5 7 .) 1: key input interrupt (ta2 i n and ta3 in inputs are assigned to pins p7 2 and p7 3 .) 5 port p6 pull-up selection bit 1 4 must be fixed to 0. at reset rw rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 0 ?port-x c selection bit ] = 0 (when the sub clock is not used) timer b2 (event counter mode) clock source selection (note 1) 0: tb2 in input (event counter mode) 1: main clock divided by 32 (clock timer) ?port-x c selection bit = 1 (when the sub clock is used) sub-clock output selection 0: pin p6 7 /tb2 in / sub functions as a programmable i/o port. 1: sub clock sub is output from pin p6 7 /tb2 in / sub . (note 2) ?key input interrupt selection bit = 0 0: no pull-up for pin p6 4 /int 2 1: with pull-up for pin p6 4 /int 2 ?key input interrupt selection bit = 1 0: pin p6 4 /int 2 is a port with no pull-up. 1: pin p6 4 /int 2 is an input pin with pull-up and is used for the key input interrupt. 0: no pull-up for pins p6 2 /int 0 and p6 3 /int 1 1: with pull-up for pins p6 2 /int 0 and p6 3 /int 1 fig. 7.2.6 structure of port function control register 7.2 block description
timer b 7733 group users manual 7C10 7.3 timer mode (bits 1 and 0 of timer bi mode register = 00 2 ) in this mode, a count source internally generated is counted. (refer to table 7.3.1. ) figure 7.3.1 shows the structures of the timer bi mode register and timer bi register in the timer mode. table 7.3.1 specifications of timer mode item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing pin tbi in s function read from timer write to timer specifications clock f 2 , f 16 , f 64 , or f 512 l countdown l at an underflow, the reload registers contents is reloaded, and counting is continued. n: set value in the timer bi register when the count start flag is set to 1. when the count start flag is cleared to 0. at an underflow programmable i/o port (pin tb2 in is a programmable i/o port or f sub output pin.) a counter value can be read out by reading the timer bi register. n while counting is stopped when a value is written to the timer bi register, it is written to both of the reload register and counter. n while counting is in progress when a value is written to the timer bi register, it is written only to the reload register. (transferred to the counter at the next reload time.) 1 (n + 1) clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. 7.3 timer mode
timer b 7733 group users manual 7C11 fig. 7.3.1 structures of timer bi mode register and timer bi register in timer mode at reset 0 0 un- defined un- defined 0 0 rw bit 3 bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) b1 b0 b4 b3 0 0 x x x 0 0 0 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 6 count source selection bits 5 this bit is ignored in the timer mode and is undefined at reading. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter ?4. clock generating circuit. b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. un- defined 2 these bits are ignored in the timer mode. 1 0 operating mode selection bits 0 0: timer mode 4 ?imer b0 mode register must be fixed to ?. ?imer b1 and b2 mode registers not implemented. rw rw rw rw rw ro rw rw rw 7.3 timer mode
timer b 7733 group users manual 7C12 7.3 timer mode 7.3.1 setting for timer mode figure 7.3.2 shows an initial setting example for registers related to the timer mode. note that when using interrupts, setting for enabling interrupts is required. for details, refer to chapter 4. interrupts.
timer b 7733 group users manual 7C13 7.3 timer mode fig. 7.3.2 initial setting example for registers related to timer mode aaa aaa aaa counting is started. b7 b0 count source selection bits 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 00 selection of the timer mode and the count source timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) setting of the count start flag to ? b7 b0 count start flag (address 40 16 ) timer b0 count start flag timer b1 count start flag timer b2 count start flag b7 b6 setting of the interrupt priority level b7 b0 timer bi interrupt control register (addresses 7a 16 to 7c 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set. x must be fixed to ??(for i = 0). x: it may be ??or ?. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter ?4. clock generating circuit. timer mode is selected. h counter divides count source frequency by (n + 1). setting of the division ratio b7 b0 values 0000 16 to ffff 16 (n) can be set. (b15) (b8) b7 b0 timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) xx 0
timer b 7733 group users manual 7C14 7.3.2 count source in the timer mode, by the count source selection bits (bits 7 and 6 at addresses 5b 16 to 5d 16 ), a count source can be selected. table 7.3.2 lists the relationship between the count source selection bits and count source. table 7.3.2 relationship between count source selection bits and count source 7.3 timer mode b7 0 0 1 1 b6 0 1 0 1 count source f 2 f 16 f 64 f 512 frequency of count source when system clock = 25 mhz when system clock = 16 mhz when system clock = 8 mhz clocks f 2 , f 16 , f 64 , f 512 , and system clock: refer to chapter 14. clock generating circuit. note: this is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0 and the main clock division selection bit (bit 0 at address 6f 16 ) = 0. (for details, refer to chapter 14. clock generating circuit. ) 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz 8 mhz 1 mhz 250 khz 31.25 khz 4 mhz 500 khz 125 khz 15.625 khz
timer b 7733 group users manual 7C15 7.3.3 operation in timer mode when the count start flag is set to 1, the counter starts counting of the count source. when an underflow occurs, the reload registers contents is reloaded, and then counting is continued. a the timer bi interrupt request bit is set to 1 when the u nderflow occurs in . after this, the interrupt request bit remains set to 1 unt il the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 7.3.3 shows an operation example in the timer mode. 7.3 timer mode fig. 7.3.3 operation example in timer mode counting is stopped. counting is restarted. ffff 16 n 0000 16 time count start flag timer bi interrupt request bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when an interrupt request is accepted; otherwise, cleared by software set to 1 by software counting is started. set to 1 by software 0 0 1 / f i 5 (n + 1) fi = frequency of count source ( 2 , f 16 , f 64 , f 512 ) cleared to 0 by software f
timer b 7733 group users manual 7C16 7.3 timer mode [precautions in timer mode] while counting is in progress, by reading out the timer bi register, the counter value can be read at an arbitrary timing. however, when reading is performed at the reload timing shown in figure 7.3.4, value ffff 16 is read out. if reading is performed in the period from when a value is set into the timer bi register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 7.3.4 timer bi register read out 210 n n ?1 counter value (hex.) 210 ffff n ?1 read value (hex.) reload time n = reload register? contents
timer b 7733 group users manual 7C17 7.4 event counter mode (bits 1 and 0 of timer bi mode register = 01 2 ) in this mode, an external signal is counted. (refer to table 7.4.1. ) figure 7.4.1 shows the structures of the timer bi mode register and timer bi register in the event counter mode. table 7.4.1 specifications of event counter mode specifications l external signal input to pin tbi in (notes 1 and 2) . l falling edge, rising edge, or falling and rising edges can be selected as the valid edge of the count source by software. l countdown l at an underflow, the reload registers contents is reloaded, and counting is continued. n: set value in the timer bi register when the count start flag is set to 1. when the count start flag is cleared to 0. at an underflow count source input a counter value can be read out by reading the timer bi register. n while counting is stopped when a value is written to the timer bi register, it is written to both of the reload register and counter. n while counting is in progress when a value is written to the timer bi register, it is written only to the reload register. (transferred to the counter at the next reload time.) item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing pin tbi in s function read from timer write to timer 1 (n + 1) notes 1: when the timer b1 internal connect selection bit (bit 2 at address 6d 16 ) = 1, timer b1 counts the timer b2s underflow signal. (refer to section 7.4.3 selectable functions. ) 2: when using timer b2 in the event counter mode, set both of the port-xc selection bit (bit 4 at address 6c 16 ) and the sub-clock output selection bit/timer b2 clock source selection bit (bit 1 at address 6d 16 ) to 0. when one of or both of these bits = 1, timer b2 functions as a clock timer. (refer to section 7.6 clock timer. ) 7.4 event counter mode
timer b 7733 group users manual 7C18 7.4 event counter mode fig. 7.4.1 structures of timer bi mode register and timer bi register in event counter mode 0 0: counting is performed at the falling edge of the external signal. 0 1: counting is performed at the rising edge of the external signal. 1 0: counting is performed at both falling and rising edges of the external signal. 1 1: do not select. b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) bit 5 this bit is ignored in the event counter mode and is undefined at reading. 4 ?imer b0 mode register must be fixed to ?. 3 2 count polarity selection bits 1 0 operating mode selection bits bit name functions 0 1: event counter mode b1 b0 b3 b2 x 01 6 these bits are ignored in the event counter mode. 7 at reset 0 0 0 un- defined un- defined 0 0 rw 0 ?imer b1 and b2 mode registers not implemented. 0 b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. un- defined xx rw rw rw rw rw ro rw rw rw
timer b 7733 group users manual 7C19 7.4 event counter mode 7.4.1 setting for event counter mode figure 7.4.2 shows an initial setting example for registers related to the event counter mode. note that when using interrupts, setting for enabling interrupts is required. for details, refer to chapter 4. interrupts.
timer b 7733 group users manual 7C20 7.4 event counter mode fig. 7.4.2 initial setting example for registers related to event counter mode h counter divides count source frequency by (n + 1). setting of the division ratio b7 b0 values 0000 16 to ffff 16 (n) can be set. (b15) (b8) b7 b0 timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) aaa aaa aaa counting is started. b7 b0 0 0: counts at falling edge of external signal. 0 1: counts at rising edge of external signal. 1 0: counts at both of falling and rising edges of external signal. 1 1: do not select. 01 selection of the event counter mode and the count polarity timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) setting of the count start flag to ? b7 b0 count start flag (address 40 16 ) timer b0 count start flag timer b1 count start flag timer b2 count start flag x: it may be ??or ?. b3b2 setting of the interrupt priority level b7 b0 timer bi interrupt control register (addresses 7a 16 to 7c 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set. setting of the port p6 direction register b7 b0 port p6 direction register (address 10 16 ) clear the corresponding bit to ?. x must be fixed to ??(for i = 0). pin tb0 in pin tb1 in pin tb2 in event counter mode is selected. count polarity selection bits xx0 selection of the timer b1 internal connection b7 b0 port function control register (address 6d 16 ) timer b1 internal connect selection bit 0: no internal connection 1: internal connection with timer b2 0
timer b 7733 group users manual 7C21 7.4 event counter mode 7.4.2 operation in event counter mode when the count start flag is set to 1, the counter starts counting of the count source. the counter counts the count sources valid edges. a when an underflow occurs, the reload registers contents is reloaded, and then counting is continued. ? the timer bi interrupt request bit is set to 1 when the underflow occurs in a . after this, the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 7.4.3 shows an operation example in the event counter mode. fig. 7.4.3 operation example in event counter mode counting is stopped. counting is restarted. ffff 16 n 0000 16 time count start flag timer bi interrupt request bit ? ? counter contents (hex.) n = reload register? contents cleared to ??when an interrupt request is accepted; otherwise, cleared by software set to ??by software counting is started. ? ? set to ??by software cleared to ??by software
timer b 7733 group users manual 7C22 7.4.3 selectable functions timer b1 internal connection is described below. (1) timer b1 internal connection when the timer b1 internal connect selection bit (bit 2 at address 6d 16 ) is set to 1, timer b1 is internally connected to timer b2 and counts the timer b2s underflow signal. accordingly, timers b2 and b1 function as a 32-bit (16 bits + 16 bits) timer and counts the timer b2s count source. this function can be used when timer b2 operates in the timer or event counter mode, or as a clock timer. figure 7.4.4 shows connection between timers b2 and b1 when timer b1 internal connection is selected. figure 7.4.5 shows structures of the timer b1 mode register and port function control register when timer b1 internal connection is selected. figure 7.4.6 shows an operation example when timer b1 internal connection is selected. fig. 7.4.4 connection between timers b2 and b1 when timer b1 internal connection is selected b7 b0 timer b1 mode register (address 5c 16 ) 1 1 b7 b0 port function control register (address 6d 16 ) a a 1 0 0 x: it may be ??or ?. 0 x x x x fig. 7.4.5 structures of timer b1 mode register and port function control register when timer b1 internal connection is selected timer b1 (event counter mode) timer b1 interrupt request bit counter (16) timer b2 count source tb 1 in timer b2 interrupt request bit reload register (16) timer b2 timer mode event counter mode clock timer timer b1 internal connect selection bit counter (16) reload register (16) 7.4 event counter mode
timer b 7733 group users manual 7C23 fig. 7.4.6 operation example when timer b1 internal connecti on is selected 3 0 timer b1/b2 count start flag timer b2 interrupt request bit timer b2 counters content (hex.) h : cleared to 0 when an interrupt request is accepted; otherw ise, cleared by software set to 1 by software 0 1 0 2 timer b1 counters contents (hex.) 0 1 timer b1 interrupt request bit h the above is applied in the following case. set value of timer b2 register = 0003 16 set value of timer b1 register = 0002 16 h h h h h time 7.4 event counter mode
timer b 7733 group users manual 7C24 7.4 event counter mode [precautions in event counter mode] 1. while counting is in progress, by reading out the timer bi register, the counter value can be read at an arbitrary timing. however, when reading is performed at the reload timing shown in figure 7.4.7, value ffff 16 is read out. if reading is performed in the period from when a value is set into the timer bi register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 7.4.7 timer bi register read out 2. the internal connect function between timer b2 and timer b1 can be used when timer b2 operates in the timer or event counter mode, or as a clock timer. do not use this function in the pulse period/pulse width measurement mode. 210 n n ?1 counter value (hex.) 210 ffff n ?1 read value (hex.) reload time n = reload register? contents
timer b 7733 group users manual 7C25 7.5 pulse period/pulse width measurement mode 7.5 pulse period/pulse width measurement mode (bits 1 and 0 of timer bi mode register = 10 2 ) in this mode, an external signals pulse period or pulse width is measured. (refer to table 7.5.1. ) figure 7.5.1 shows the structures of the timer bi mode register and timer bi register in the pulse period/pulse width measurement mode. n pulse period measurement the pulse period of an external signal which is input to pin tbi in is measured. n pulse width measurement the pulse width (l level width and h level width) of an external signal which is input to pin tbi in is measured. note: when the port-xc selection bit (bit 4 at address 6c 16 ) = 1, timer b2 functions as a clock timer. accordingly, pulse period/pulse width measurement cannot be performed. table 7.5.1 specifications of pulse period/pulse width measurement mode item count source count operation count start condition count stop condition interrupt request occurrence timing pin tbi in s function read from timer write to timer specifications clock f 2 , f 16 , f 64 , or f 512 l countup l when valid edge of the measurement pulse is input, the counter value is transferred to the reload register. and then, the counter value is cleared to 0000 16 , and counting is continued. when the count start flag is set to 1. when the count start flag is cleared to 0. l when the valid edge of the measurement pulse is input ( note 1 ). l at an overflow (simultaneously, the overflow flag is set to 1.) measurement pulse input by reading the timer bi register, the reload registers contents (measurement result) is read out ( note 2 ). ignored clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. overflow flag: a flag used to identify the source of an interrupt request occurrence. notes 1: an interrupt request is not generated when the first valid edge is input after counting starts. 2: from when counting starts until the second valid edge is input, a value obtained by reading the timer bi register is undefined.
timer b 7733 group users manual 7C26 7.5 pulse period/pulse width measurement mode fig. 7.5.1 structures of timer bi mode register and timer bi register in pulse period/pulse width measurement mode b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 the result of the pulse period or pulse width measurement is read out. un- defined 0 0: pulse per i od measurement ( interval between falling edges of the measurement pulse) 0 1: pulse per i od measurement interval between rising edges of t he measurement pulse) 1 0: pulse width measurement ( i nt er v al f r om a f al l i ng edge t o a rising edge, and fr om a r i s i ng edge t o a f al l i ng edge of t he measurement pulse) 1 1: do not select. b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) bit count source selection bits timer bi overflow flag (note) ?timer b0 mode register must be fixed to 0. 3 measurement mode selection bits 1 operating mode selection bits bit name functions 1 0: pulse per i od/ pulse width measurement b1 b0 0: no overflow 1: overflow b3 b2 10 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 at reset 0 0 0 un- defined 1 0 0 rw 0 ?timer b1 and b2 mode registers not implemented. 0 clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. note: timer bi overflow flag is cleared to 0 when writing to the timer bi mode register is performed with the count start flag = 1. this flag cannot be set to 1 by software. rw rw rw rw rw ro rw rw ro 0 2 mode 6 5 4
timer b 7733 group users manual 7C27 7.5 pulse period/pulse width measurement mode 7.5.1 setting for pulse period/pulse width measurement mode figure 7.5.2 shows an initial setting example for registers related to the pulse period/pulse width measurement mode. note that when using interrupts, setting for enabling interrupts is required. for details, refer to chapter 4. interrupts.
timer b 7733 group users manual 7C28 7.5 pulse period/pulse width measurement mode fig. 7.5.2 initial setting example for registers related to pulse period/pulse width measurement mode aaa aaa aaa counting is started. b7 b0 measurement mode selection bits 10 selection of the pulse period/pulse width measurement mode and each function timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) setting of the count start flag to ? b7 b0 count start flag (address 40 16 ) timer b0 count start flag timer b1 count start flag timer b2 count start flag must be fixed to ??(for i = 0). b3 b2 setting of the interrupt priority level b7 b0 timer bi interrupt control register (addresses 7a 16 to 7c 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set. count source selection bits b7 b6 timer bi overflow flag (note) 0: no overflow 1: overflow setting of the port p6 direction register b7 b0 port p6 direction register (address 10 16 ) clear the corresponding bit to ?. pin tb0 in pin tb1 in pin tb2 in 0 0: pulse period measurement (interval between falling edges) 0 1: pulse period measurement (interval between rising edges) 1 0: pulse width measurement 1 1: do not select. 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 note: the timer bi overflow flag is a read-only flag. this flag is cleared to ??when writing to timer bi mode register is performed with the count start flag = ?. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. pulse period/pulse width measurement mode is selected. 0
timer b 7733 group users manual 7C29 7.5.2 count source in the pulse period/pulse width measurement mode, by the count source selection bits (bits 7 and 6 at addresses 5b 16 to 5d 16 ), a count source can be selected. table 7.5.2 lists the relationship between the count source selection bits and count source. table 7.5.2 relationship between count source selection bits and count source b7 0 0 1 1 b6 0 1 0 1 count source f 2 f 16 f 64 f 512 frequency of count source when system clock = 25 mhz when system clock = 16 mhz when system clock = 8 mhz 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz 4 mhz 500 khz 125 khz 15.625 khz 8 mhz 1 mhz 250 khz 31.25 khz clocks f 2 , f 16 , f 64 , f 512 , and system clock: refer to chapter 14. clock generating circuit. note: this is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0 and the main clock division selection bit (bit 0 at address 6f 16 ) = 0. (for details, refer to chapter 14. clock generating circuit. ) 7.5 pulse period/pulse width measurement mode
timer b 7733 group users manual 7C30 7.5 pulse period/pulse width measurement mode 7.5.3 operation in pulse period/pulse width measurement mode when the count start flag is set to 1, the counter starts counting of the count source. when a valid edge of the measurement pulse is input, the counter value is transferred to the reload register. (refer to (1) pulse period/pulse width measurement. ) a after a transfer in , the counter value becomes 0000 16, and the counter continues counting. ? the timer bi interrupt request bit is set to 1 when the counter value becomes 0000 16 in a ,( note ). after this, the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. ? operations to ? are repeated. note: timer bi interrupt request is not generated when the first valid edge is input after counting starts. (1) pulse period/pulse width measurement whether to measure the pulse period or the pulse width of an external signal can be selected by the measurement mode selection bits (bits 3 and 2 at addresses 5b 16 to 5d 16 ). table 7.5.3 lists the relationship between the measurement mode selection bits and the pulse period/pulse width measurement. make sure that the measurement interval from the falling edge to the rising edge and that of from the rising edge to the falling edge are two cycles of the count source or more. when measuring pulse width of a signal whose duty ratio is not 50%, identify whether the measurement result is the h level width or the l level width by software. table 7.5.3 relationship between measurement mode selection bits and pulse period/pulse width measurement b3 0 0 1 pulse period/pulse width measurement pulse period measurement pulse width measurement measurement interval (valid edge) from falling edge to falling edge (falling edge) from rising edge to rising edge (rising edge) from falling edge to rising edge, and from rising edge to falling edge (falling and rising edges) b2 0 1 0
timer b 7733 group users manual 7C31 7.5 pulse period/pulse width measurement mode (2) timer bi overflow flag when a measurement pulses valid edge is input or an overflow occurs, a timer bi interrupt request is generated. the timer bi overflow flag is used to identify the cause of an interrupt request occurrence, in other words, determine whether it is an overflow or a valid edge input. when an overflow occurs, the timer bi overflow flag is set to 1. therefore, the source of the interrupt request occurrence can be identified by checking the timer bi overflow flags state in the interrupt routine. the timer bi overflow flag is cleared to 0 at the next count timing of the count source when a value is written to the timer bi mode register with the count start flag = 1. the timer bi overflow flag is a read-only flag. do not use this flag for detection of overflow timing. figure 7.5.3 shows the operation during pulse period measurement. figure 7.5.4 shows the operation during pulse width measurement. fig. 7.5.3 operation during pulse period measurement count source measurement pulse timing when counter is cleared to ?000 16 ? ? ? h the above is applied when measurement is performed from one falling edge of the measurement pulse until the next falling edge of that. reload register @@ counter transfer timing ? ? ? count start flag ? ? initialization of the counter because of measurement completion overflow cleared to ??when an interrupt request is accepted; otherwise, cleared by software timer bi interrupt request bit timer bi overflow flag transferred (undefined value) transferred (measured value)
timer b 7733 group users manual 7C32 7.5 pulse period/pulse width measurement mode fig. 7.5.4 operation during pulse width measurement measurement pulse h count source reload register counter transfer timing timing when counter is cleared to 0000 16 1 1 transferred (measured value) l 0 0 1 0 cleared to 0 when an interrupt request is accepted; otherwise, cleared by software initialization of the counter because of measurement complet ion overflow count start flag timer bi interrupt request bit timer bi overflow flag transferred (measured value) transferred (measured value) transferred (undefined value)
timer b 7733 group users manual 7C33 7.5 pulse period/pulse width measurement mode [precautions in pulse period/pulse width measurement mode] 1. a timer bi interrupt request is generated by the following sources: l the measurement pulses valid edge which is input l an overflow the interrupt request source shown above can be determined by the timer bi overflow flag. 2. at reset, the timer bi overflow flag is set to 1. this flag can be cleared to 0 by performing writing to the timer bi mode register with the count start flag = 1. 3. when the first valid edge is input after counting starts, an undefined value is transferred to the reload register. at this time, a timer bi interrupt request is not generated. 4. at start of counting, the counter value is undefined. therefore, there is a possibility that a timer bi interrupt request is generated by an overflow which occurs immediately after counting starts. 5. when the measurement mode selection bits are changed after counting starts, the timer bi interrupt request bit is set to 1. note that the timer bi interrupt request bit does not change if the same value as before is written to the measurement mode selection bits. 6. when an input signal to pin tbi in is affected by noise or others, there is a possibility that the counter cannot perform the exact measurement. we recommend to verify, by software, that the measurement values are within a constant range.
timer b 7733 group users manual 7C34 7.6 clock timer timer b2 functions as a clock timer on the following condition (refer to table 7.6.1. ): l when the port-xc selection bit (bit 4 at address 6c 16 ) = 1 l when the port-xc selection bit = 0 and the timer b2 clock source selection bit (bit 1 at address 6d 16 ) = 1 figure 7.6.1 shows the structures of the timer b2 mode register and timer b2 register when a clock timer is used. item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing pin tb2 in s function read from timer write to timer table 7.6.1 specifications of clock timer specifications fc 32 (sub clock divided by 32: f(x cin )/32), or main clock divided by 32: f(x in )/32) l countdown l at an underflow, the reload registers contents is reloaded, and counting is continued. 1 (n + 1) when the count start flag is set to 1. when the count start flag is cleared to 0. at an underflow programmable i/o port or f sub output pin a counter value can be read out by reading the timer b2 register. n while counting is stopped when a value is written to the timer b2 register, it is written to both of the reload register and counter. n while counting is in progress when a value is written to the timer b2 register, it is written only to the reload register. (transferred to the counter at the next reload time.) n: set value in the timer b2 register clocks fc 32 and f(x cin ): refer to chapter 14. clock generating circuit. either of f(x cin )/32 or f(x in )/32 can be selected as the clock timers count source, fc 32 . the way to generate f(x cin )/32 is different from that for clocks whose source is the system clock (e.g., internal clock f , clocks f 2 to f 512 , and so on). (refer to chapter 14. clock generating circuit. ) f(x cin )/32 is not affected by the system clock selection bit and system clock stop bit at wait state (bits 3 and 5 at address 6c 16 ). therefore, in the wait mode, (refer to chapter 11. stop and wait modes. ) only the clock timer can operate by itself. in other words, it is possible to supply fc 32 only. oppositely, the way to generate f(x in )/32 is the same as that for the system clock. therefore, when the system clock stop bit at wait state = 1, fc 32 is not supplied in the wait mode. figure 7.6.2 shows the structure of the clock timer. 7.6 clock timer
timer b 7733 group users manual 7C35 fig. 7.6.1 structures of timer b2 mode register and timer b2 register when clock timer is used at reset functions 0 0 un- defined un- defined 0 0 rw bit 3 must be fixed to 0 for the clock timer. b7 b6 b5 b4 b3 b2 b1 b0 timer b2 mode register (address 5d 16 ) 1 0 1 0 0 0 6 these bits are ignored for the clock timer. 5 this bit is ignored for the clock timer. b7 b0 b7 b0 (b15) (b8) timer b2 register (addresses 55 16 and 54 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. un- defined 2 must be fixed to 1 for the clock timer. 1 must be fixed to 0 for the clock timer. 0 must be fixed to 1 for the clock timer. 4 not implemented. x 7 xx rw rw rw rw ro rw rw rw 7.6 clock timer
timer b 7733 group users manual 7C36 7.6 clock timer sub clock : f(x cin ) main clock : f(x in ) clock timer (timer b2 counter) system clock (clock source for f 2 to f 512 , and internal clock ) timer b2 interrupt request bit 1/32 fc 32 clock prescaler timer b2 reload register fig. 7.6.2 structure of clock timer
timer b 7733 group users manual 7C37 7.6 clock timer 7.6.1 setting for clock timer figure 7.6.3 shows an initial setting example for registers related to the clock timer. note that when using interrupts, setting for enabling interrupts is required. for details, refer to chapter 4. interrupts. fig. 7.6.3 initial setting example for registers related to clock timer aaaaa aaaaa aaaaa aaaaa aaaaa counting is started. b7 b0 selection of the clock timer oscillation circuit control register 0 (address 6c 16 ) setting of the count start flag to ? b7 b0 count start flag (address 40 16 ) timer b2 count start flag setting of the interrupt priority level b7 b0 timer b2 interrupt control register (address 7c 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set. initialization of the clock prescaler by using ldm instruction, write value ?0 16 ?to address 6f 16 . 1: x cin ? cout selected (sub clock used) note: after oscillation of an oscillator connected to the sub-clock oscillation circuit is stabilized, set the count start flag to ?. port-xc selection bit 1 1 0 1 0 b7 b0 timer b2 mode register (address 5d 16 ) h counter divides the count source frequency by (n + 1). b7 b0 b7 b0 setting of the division ratio values 0000 16 to ffff 16 (n) can be set. (b15) (b8) timer b2 register (addresses 55 16 and 54 16 ) x x: it may be ??or ?. xx 1 b7 b0 selection of the clock timer oscillation circuit control register 0 (address 6c 16 ) port-xc selection bit 0: ports p7 7 and p7 6 selected (sub clock not used) 0 1 0 1 0 b7 b0 timer b2 mode register (address 5d 16 ) x x: it may be ??or ?. xx when using sub clock (xc) b7 b0 port function control register (address 6d 16 ) sub-clock output selection bit/timer b2 clock source selection bit timer b2 (event counter mode) clock source selection 1: main clock divided by 32 1 when not using sub clock (xc)
timer b 7733 group users manual 7C38 7.6 clock timer 7.6.2 operation of clock timer when the count start flag is set to 1, the counter starts counting of the count source. when an underflow occurs, the reload registers contents is reloaded, and then counting is continued. a the timer b2 interrupt request bit is set to 1 when the u nderflow occurs in . after this, the interrupt request bit remains set to 1 unt il the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. for example, if f(x cin ) = 32.768 khz, a timer b2 interrupt request can be issued e very second when value 3ff 16 is set into the timer b2 register (addresses 54 16 and 55 16) and every minute when value efff 16 is set into the register. figure 7.6.4 shows an operation ex ample of clock timer. fig. 7.6.4 operation example of clock timer ffff 16 n 0000 16 count start flag timer b1 interrupt request bit 1 1 timer b2 counters contents (hex.) cleared to 0 when an interrupt request is accepted; otherw ise, cleared by software set to 1 by software 0 0 0000 16 ffff 16 n timer b2 counters contents (hex.) cleared to 0 by software
timer b 7733 group users manual 7C39 7.6 clock timer [precautions for clock timer] 1. while counting is in progress, by reading out the timer b2 register, the counter value can be read at an arbitrary timing. however, when reading is performed at the reload timing shown in figure 7.6.5, value ffff 16 is read out. if reading is performed in the period from when a value is set into the timer b2 register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 7.6.5 timer b2 register read out 210 n n ?1 counter value (hex.) 210 ffff n ?1 read value (hex.) reload time n = reload register? contents 2. for the clock prescaler reset, refer to section 14.3.4 clock prescaler reset.
timer b 7733 group users manual 7C40 memo 7.6 clock timer
chapter 8 chapter 8 serial i/o 8.1 overview 8.2 block description 8.3 clock synchronous serial i/o mode 8.4 clock asynchronous serial i/o (uart) mode
serial i/o 7733 group users manual 8C2 the serial i/o consists of 3 channels: uart0, uart1 and uart2. they each have a dedicated timer for generating a transfer clock and can operate independently. 8.1 overview uarti (i = 0 to 2) has the following two operating modes: clock synchronous serial i/o and clock asynchronous serial i/o (uart) modes. except for a few functions in the clock synchronous serial i/o mode, uart0, uart1 and uart2 have the same functions. l clock synchronous serial i/o mode transmitter and receiver use the same clock as a transfer clock. transfer data has a length of 8 bits. l clock asynchronous serial i/o (uart) mode transfer rate and transfer data format can arbitrarily be set. the transfer data length can be selected from the following three types: 7 bits, 8 bits, and 9 bits. figure 8.1.1 shows the transfer data formats in each operating mode. table 8.1.1 shows the differences between uart0, uart1 and uart2. 8.1 overview fig. 8.1.1 transfer data formats in each operating mode n clock synchronous serial i/o mode n uart mode transfer data length : 7 bits transfer data length : 8 bits transfer data length : 9 bits
serial i/o 7733 group users manual 8C3 table 8.1.1 differences between uart0, uart1 and uart2 communication clock synchronous or asynchronous (uart) mode is selectable. clock synchronous or asynchronous (uart) mode is selectable. clock synchronous or asynchronous (uart) mode is selectable. uart0 uart1 uart2 notes 1: the a-d conversion interrupt and uart2 transmission/reception interrupt share the interrupt vector addresses and the interrupt control register. when the uart2 mode is selected by specifying bits 2 to 0 of the uart2 transmit/receive mode register (address 64 16 ), the a-d conversion interrupt function cannot be used. 2: uart2 is fixed as follows. ? data output (txd 2 pin): cmos output ? polarity of clk 2 : transmit data is output at the falling edge of the transfer clock. receive data is input at the rising edge of the transfer clock. when not transferring, clk 2 pins level is h. (used in the clock synchronous serial i/o mode) ? transfer format: lsb (the least significant bit) first 8.1 overview multiple clocks output function available not available not available sleep function available available not available _______ cts input/ _______ rts output function both functions are available. both functions are available. _______ only cts input function is available. interrupt function ?uart0 transmission ?uart0 reception (2 systems) ?uart1 transmission ?uart1 reception (2 systems) ?uart2 transmission /reception (note 1) (1 system) data output/clk polarity/transfer format select function available available not available ( note 2 )
serial i/o 7733 group users manual 8C4 note: the bit converter, the polarity reversing circuit and rtsi output function are not assigned for uart2. n: value set to the uarti baud rate register divider [1/ (n+1)] uart2 (address 65 16 ) divider(1/16 ) clki ctsi / rtsi 0000000d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data bus (odd) transfer clock receive control circuit transmission control circuit transmission register d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart0 (addresses 37 16 , 36 16 ) receive buffer register uart1 (addresses 3f 16 , 3e 16 ) transmission buffer register divider(1/16 ) uart transmission divider (1/2 ) f 2 f 16 f 64 f 512 clock synchronous (when internal clock is selected) uart receive clock synchronous clock synchronous clock synchronous (internal clock) clock synchronous (external clock) internal external baud rate register uart0 (address 31 16 ) clock source selection rxd i txd i bit converter receive register data bus (odd) bit converter polarity reversing circuit data bus (even) uart2 (addresses 6b 16 , 6a 16 ) ( note ) ( note ) ( note ) ( note ) data bus (even) transfer clock uart0 (addresses 33 16 , 32 16 ) uart1 (addresses 3b 16 , 3a 16 ) uart2 (addresses 67 16 , 66 16 ) uart1 (address 39 16 ) 8.2 block description figure 8.2.1 shows the block diagram for serial i/o. registers related to serial i/o are described below. 8.2 block description fig. 8.2.1 block diagram for serial i/o
serial i/o 7733 group users manual 8C5 bit 7 sleep selection bit (valid in the uart mode.) (note) 6 parity enable bit (valid in the uart mode.) (note) 5 odd/even parity selection bit (valid in the uart mode when the parity enable bit = ?.? (note) 4 stop bit length selection bit (valid in the uart mode.) (note) 3 internal/external clock selection bit 2 1 0 serial i/o mode selection bits bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0 0: serial i/o is disabled. (p8 functions as a programmable i/o port.) 0 0 1: clock synchronous serial i/o mode 0 1 0: do not select. 0 1 1: do not select. 1 0 0: uart mode (transfer data length = 7 bits) 1 0 1: uart mode (transfer data length = 8 bits) 1 1 0: uart mode (transfer data length = 9 bits) 1 1 1: do not select. uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) note: bits 4 to 6 are ignored in the clock synchronous serial i/o mode. (they may be ??or ?.? fix bit 7 to ?. b2 b1 b0 0: odd parity 1: even parity 0: parity is disabled. 1: parity is enabled. 0: the sleep mode is terminated. (ignored.) 1: the sleep mode is selected. 0: internal clock 1: external clock 0: one stop bit 1: two stop bits rw rw rw rw rw rw rw rw 8.2.1 uarti transmit/receive mode register figures 8.2.2 and 8.2.3 show the structure of uarti transmit/receive mode register. the serial i/o mode selection bits are used to select a uartis operating mode. for bits 4 to 6, refer to section 8.4.2 transfer data format. for bit 7, refer to section 8.4.8 sleep mode. fig. 8.2.2 structure of uarti transmit/receive mode register (1) 8.2 block description
in the clock synchronous serial i/o mode, bits 4 to 6 are i gnored. (they may be 0 or 1.) serial i/o 7733 group users manual 8C6 bit not implemented. parity enable bit (valid in the uart mode.) (note 2) odd/even parity selection bit (valid in the uart mode when the parity enable bit = 1.) (note 2) 4 (valid in the uart mode.) (note 2) internal/external clock selection bit 2 1 serial i/o mode selection bits (note 1) bit name at reset un- defined 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0 0: serial i/o is ignored. (p7 functions as a programmable i/o port) 0 0 1: clock synchronous serial i/o mode 0 1 0: 0 1 1: 1 0 0: uart mode (transfer data length = 7 bits) 1 0 1: uart mode (transfer data length = 8 bits) 1 1 0: uart mode (transfer data length = 9 bits) 1 1 1: do not select. uart2 transmit/receive mode register (address 64 16 ) notes 1: by specifying these bits, an a-d conversion interrupt or a uart2 transmit/receive interrupt is selected. when bits 2 to 0 = 000 2 , an a-d conversion interrupt is selected. when bits 2 to 0 = 001 2 or 100 2 to 111 2 , a uart2 transmit/receive interrupt is selected. 2: b2 b1 b0 0: odd parity 1: even parity 0: parity is disabled. 1: parity is enabled. 0: internal clock 1: external clock 0: one stop bit 1: two stop bits rw rw rw rw rw rw rw do not select. 8.2 block description fig. 8.2.3 structure of uarti transmit/receive mode register (2) 0 stop bit length selection bit 5 6 7
serial i/o 7733 group users manual 8C7 (1) internal/external clock selection bit (bit 3) l clock synchronous serial i/o mode when an internal clock is selected by clearing this bit to 0, a clock which is specified with the brg count source selection bits (bits 1 and 0 at addresses 34 16 , 3c 16 and 68 16 ) becomes the count source of brgi (described later). at this time, the brgis output divided by 2 is the transfer clock. the transfer clock is output from the clki pin ( note ). when an external clock is selected by setting this bit to 1, a clock input to the clki pin becomes the transfer clock. note : when selecting an internal clock and performing only transmission in uart0, the number of the transfer clock output pins varies according to the contents of the transmit clock output pin selection bits (bits 5 and 4 at address 6e 16 ). (refer to section 8.3.1 transfer clock. ) l uart mode when an internal clock is selected by clearing this bit to 0, a clock which is specified with the brg count source selection bits (bits 1 and 0 at addresses 34 16 , 3c 16 and 68 16 ) becomes the count source of the brgi (described later). at this time, the clki pin functions as a programmable i/o port. when an external clock is selected by setting this bit to 1, a clock input to the clki pin becomes the count source of brgi . note that, in the uart mode, the brgis output divided by 16 is always the transfer clock. brgi: uarti baud rate register (refer to section 8.2.7 uarti baud rate register (brgi). ) 8.2 block description
0: the serial i/o 7733 group users manual 8C8 0: at the falling edge of the transfer clock, transmit data is output; at the rising edge of the transfer clock, receive data is input. when not in transferring, pin clk i s level is h. 1: at the rising edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. when not in transferring, pin clk i s level is l. 0: the cts / rts function is enabled. 1: the cts / rts function is disabled. (p8 0 and p8 4 function as ? programmable i/o ports.) (valid when the cts / rts enable bit is 0.) 2 cts / rts function selection bit bit 1 0 brg count source selection bits bit name at reset 0: data is present in the transmission register. (transmission is in progress.) 1: no data is present in the transmission register. (transmission is completed.) rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 uart0 transmit/receive control register 0 (address 3 4 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b1 b0 cts function is selected. 1: the rts function is selected. 4 cts / rts enable bit 3 transmission register empty flag 0 1 0 0 0 clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. note: fix bits 6 and 7 to 0 in the uart mode. 5 data output selection bit 0: pin txd i is set for cmos output. 1: pin txd i is set for n-channel open- drain output. 0 6 0 7 0: lsb (least significant bit) first 1: msb (most significant bit) first 0 clk polarity selection bit (this bit is used in the clock synchronous serial i/o mode.) (note) transfer format selection bit (this bit is used in the clock synchronous serial i/o mode.) (note) rw rw rw ro rw rw rw rw fig. 8.2.4 structure of uarti transmit/receive control regis ter 0 (1) 8.2 block description 8.2.2 uarti transmit/receive control register 0 figures 8.2.4 and 8.2.5 show the structure of uarti transmit /receive control register 0. for bits 1 and 0, refer to section (1) internal/external clock selection bit in page 8-7. for bits 7 to 4, refer to the description of each operating mode.
serial i/o 7733 group users manual 8C9 2 cts enable bit bit 1 0 brg count source selection bits bit name at reset functions b7 b6 b5 b4 b3 b2 b1 b0 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 uart2 transmit/receive control register 0 (address 68 16 ) b1 b0 0: the cts function is enabled. 1: the cts function is disabled. (p8 0 and p8 4 function as programmable i/o ports.) 3 transmission register empty flag not implemented. 1 0 0 0 7 to 4 rw rw rw rw ro 0: data is present in the transmission register. (transmission is in progress.) 1: no data is present in the transmission register. (transmission is completed.) un- defined clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. fig. 8.2.5 structure of uarti transmit/receive control regis ter 0 (2) (1) ____ ____ cts / rts function selection bit (bit 2) (uart0, uart1) ____ ____ this bit becomes valid when the cts / rts enable bit (bit 6) is cleared to 0. ____ when this bit is cleared to 0 in order to select the cts function, the p8 0 and p8 4 pins function as ____ ____ cts input pins. at this time, a l-level signal input to the cts pin is one of the transmit conditions. ____ ____ when this bit is set to 1 in order to select the rts function, the p8 0 and p8 4 pins function as rts output pins. when the receive enable bit (bit 2 at addresses 35 16 , 3d 16 ) is 0 (in other words, ____ reception is disabled.), the rts pin outputs h level. ____ in the clock synchronous serial i/o mode, the output level o f rts pin becomes l when receive conditions are satisfied; it becomes h when reception is s tarted. note that, when an internal clock ____ is selected (bit 3 at addresses 30 16 , 38 16 = 0), the rts function is ignored. ____ in the clock asynchronous serial i/o mode, the output level of the rts pin becomes l when receive enable bit is set to 1; it becomes h when reception is s tarted; it becomes l when the reception is completed. ____ (2) cts enable bit (bit 2) (uart2) ____ cts input pin is valid when this bit is set to 0. ____ a l-level signal input to the cts pin is one of the transmit conditions. (3) transmission register empty flag (bit 3) this flag is cleared to 0 when the contents of the uarti t ransmission buffer register is transferred to the uarti transmission register. when transmission is com pleted and the uarti transmission register becomes empty, this flag is set to 1. 8.2 block description
serial i/o 7733 group users manual 8C10 at reset bit bit name 5 framing error flag (notes 1 and 2) (valid in the uart mode.) 0 0: no framing error is detected. 1: framing error is detected. rw functions b7 b6 b5 b4 b3 b2 b1 b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) notes 1: bits 4 to 7 are cleared to 0 when the serial i/o mode sel ection bits (bits 2 to 0 at addresses 30 16 , 38 16 ) are cleared to 000 2 or when the receive enable bit is cleared to 0. (bit 7 is cleared to 0 when all of bits 4 to 6 are 0.) note also that bits 5 and 6 are cleared to 0 when the low- order byte of the uarti receive buffer register (addresses 36 16 , 3e 16 , 6a 16 ) is read out. 2: bits 5 to 7 are ignored in the clock synchronous serial i/o mode. 0 transmit enable bit 0 0: transmission is disabled. 1: transmission is enabled. 1 transmission buffer empty flag 1 0: data is present in the transmission buffer register. 1: no data is present in the transmission buffer register. 2 receive enable bit 0 0: reception is disabled. 1: reception is enabled. 3 receive completion flag 0 0: no data is present in the receive buffer register. 1: data is present in the receive buffer register. 4 overrun error flag (note 1) 0 0: no overrun error is detected. 1: overrun error is detected. 6 parity error flag (notes 1 and 2) (valid in the uart mode.) 0 0: no parity error is detected. 1: parity error is detected. 7 error sum flag (notes 1 and 2) (valid in the uart mode.) 0 0: no error is detected. 1: error is detected. rw ro rw ro ro ro ro ro 8.2 block description 8.2.3 uarti transmit/receive control register 1 figure 8.2.6 shows the structure of uarti transmit/receive c ontrol register 1. for bits 7 to 4, refer to the description of each operating mode. fig. 8.2.6 structure of uarti transmit/receive control regis ter 1
serial i/o 7733 group users manual 8C11 (1) transmit enable bit (bit 0) when this bit is set to 1, uarti enters the transmit enable state. when this bit is cleared to 0 during transmission, uarti enters the transmit disable state after the transmission which is in progress at this clearing is completed. (2) transmission buffer empty flag (bit 1) this flag is set to 1 when data is transferred from the uarti transmission buffer register to the uarti transmission register. this flag is cleared to 0 when data is set to the uarti transmission buffer register. (3) receive enable bit (bit 2) when this bit is set to 1, uarti enters the receive enable state. when this bit is cleared to 0 during reception, uarti quits the reception immediately and enters the receive disable state. (4) receive completion flag (bit 3) this flag is set to 1 in the following case; ? when data is ready in the uarti receive register and is transferred to the uarti receive buffer register (in other words, when reception is completed). this flag is cleared to 0 in one of the following cases; ? when the low-order byte of the uarti receive buffer register is read out, ? when the receive enable bit (bit 2) is cleared to 0, ? when port p8 is used as a programmable i/o port by clearing the serial i/o mode selection bits (bits 2 to 0 at addresses 30 16 , 38 16 and 64 16 ) to 000 2 8.2 block description
serial i/o 7733 group users manual 8C12 bit bit name at reset rw functions b7 b6 b5 b4 b3 b2 b1 b0 serial transmit control register (address 6e 16 ) h when using multiple transfer clock output pins, satisfy the following conditions: l serial i/o mode selection bits (bits 2 to 0 at address 30 16 ) = 001 2 l internal/external clock selection bit (bit 3 at address 30 16 ) = 0 l cts / rts enable bit (bit 4 at address 34 16 ) = 1 l receive enable bit (bit 2 at address 35 16 ) = 0 (for cases and in table 8.3.4) l transmission clock output pin selection bits = 01 2 , 10 2 , or 11 2 (refer to table 8.3.3 .) note: bits 4 and 5 are ignored in the uart mode. (they may be 0 or 1.) not implemented. un- defined 4 transmission clock output pin selection bits (valid only in the clock synchronous serial i/o mode.) (note) 0 0 0: one transfer clock output pin (clk 0 ) 0 1: 1 0: 1 1: 5 0 0 3 to 0 7, 6 not implemented. value 0 is read out from here. b5 b4 multiple transfer clock output pins rw rw 8.2.4 serial transmit control register figure 8.2.7 shows the structure of the serial transmit cont rol register. the transmission clock output pin selection bits are valid only for uart0. for these bits, ref er to section 8.3.1 transfer clock. 8.2 block description fig. 8.2.7 structure of serial transmit control register
serial i/o 7733 group users manual 8C13 8.2.5 uarti transmission register and uarti transmission buffer register figure 8.2.8 shows the block diagram for the transmitter. figure 8.2.9 shows the structure of the uarti transmission buffer register. fig. 8.2.8 block diagram for transmitter 8.2 block description fig. 8.2.9 structure of uarti transmission buffer register sp sp par ? 2sp 1sp uart 7-bit uart 8-bit uart 7-bit uart 9-bit uart clock sync. clock sync. clock sync. data bus (even) data bus (odd) txd i uarti transmission register parity enabled parity disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp : stop bit par : parity bit uarti transmission buffer register bit converter 8-bit uart 9-bit uart ( note ) note: the bit converter is not assigned for uart2. b7 b0 (b15) (b8) b7 b0 uart0 transmission buffer register (addresses 33 16 , 32 16 ) uart1 transmission buffer register (addresses 3b 16 , 3a 16 ) uart2 transmission buffer register (addresses 67 16 , 66 16 ) bit not implemented. the transmit data is set. at reset un- defined rw functions 8 to 0 15 to 9 un- defined wo
serial i/o 7733 group users manual 8C14 transmit data is set into the uarti transmission buffer register. when the microcomputer operates in the clock synchronous serial i/o mode or when 7-bit or 8-bit length is selected as the transfer datas length in the uart mode, the transmit data is set into the low-order byte of this register. when 9-bit length is selected as the transfer datas length in the uart mode, the transmit data is set into the uarti transmission buffer register as follows. l bit 8 of the transmit data is set into bit 0 of the high-order byte of the uarti transmission buffer register. l bits 7 to 0 of the transmit data are set into the low-order byte of the uarti transmission buffer register. when transmit conditions are satisfied, the transmit data which is set in the uarti transmission buffer register is transferred to the uarti transmission register, and then it is output from the txdi pin synchronously with the transfer clock. the uarti transmission buffer register becomes empty when data which is set in this register is transferred to the uarti transmission register, so the next transmit data can be set. when the msb first is selected in the clock synchronous serial i/o mode, bit position of set data is reversed, and then this data is written into the uarti transmission buffer register as the transmit data. (refer to section 8.3.2 transfer data format. ) transmit operation itself is the same whichever format is selected, lsb first or msb first. when quitting the transmission which is in progress and setting the uarti transmission buffer register again, follow the procedure described below. clear the serial i/o mode selection bits (bits 2 to 0 at addresses 30 16 , 38 16 and 64 16 ) to 000 2 . (serial i/o is ignored.) set the serial i/o mode selection bits again. a set the transmit enable bit (bit 0 at addresses 35 16 , 3d 16 and 69 16 ) to 1 (in other words, transmission is enabled.) and set the transmit data into the uarti transmission buffer register. 8.2 block description
serial i/o 7733 group users manual 8C15 8.2.6 uarti receive register and uarti receive buffer register figure 8.2.10 shows the block diagram for the receiver. figure 8.2.11 shows the structure of the uarti receive buffer register. fig. 8.2.10 block diagram for receiver 8.2 block description fig. 8.2.11 structure of uarti receive buffer register b7 b0 (b15) (b8) b7 b0 uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) uart2 receive buffer register (addresses 6b 16 , 6a 16 ) bit not implemented. a value of ??is read out from here. the receive data is read out from here. at reset 0 un- defined rw functions 8 to 0 15 to 9 ro clock sync. sp sp par 2sp 1sp uart 0 0 0 0 0 0 0 rxd i d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp : stop bit par : parity bit 8-bit uart 9-bit uart 7-bit uart 9-bit uart clock sync. clock sync. 7-bit uart 8-bit uart data bus (even) data bus (odd) bit converter uarti receive register parity enabled parity disabled uarti receive buffer register ( note ) note: the bit converter is not assigned for uart2.
serial i/o 7733 group users manual 8C16 b7 b0 b7 b0 0000000 0000000 0000000 receive data (9 bits) receive data (8 bits) receive data (7 bits) (transfer data length : 9 bits) during uart mode (transfer data length : 8 bits) during uart mode (transfer data length : 7 bits) same value as bit 7 in low-order byte same value as bit 6 in low-order byte high-order byte (addresses 37 16 , 3f 16 , 6b 16 ) low-order byte (addresses 36 16 , 3e 16 , 6a 16 ) the uarti receive register is used to convert serial data, which is input from the rxdi pin, into parallel data. this register takes a signal which is input from the rxdi pin by the 1 bit synchronously with the transfer clock. the uarti receive buffer register is used to read receive data. when reception is completed, the receive data which is taken into the uarti receive register is automatically transferred to the uarti receive buffer register. note that the contents of the uarti receive buffer register is updated when the next data is ready in the uarti receive register before data which has been transferred to the uarti receive buffer register is read out (in other words, when an overrun error occurs). when msb first is selected in the clock synchronous serial i/o mode, bit position of data in the uarti receive buffer register is reversed, and then this data is read out as the receive data. (refer to section 8.3.2 transfer data format. ) receive operation itself is the same whichever format is selected, lsb first or msb first. the uarti receive buffer register is initialized when the receive enable bit (bit 2 at addresses 35 16 , 3d 16 and 69 16 ) is set to 1 after clearing it to 0. figure 8.2.12 shows the contents of the uarti receive buffer register when reception is completed. fig. 8.2.12 contents of uarti receive buffer register when reception is completed 8.2 block description
serial i/o 7733 group users manual 8C17 8.2.7 uarti baud rate register (brgi) the uarti baud rate register (brgi) is an 8-bit timer used only for uarti. it generates a transfer clock and has a reload register. assuming that a value set in brgi is n (n = 00 16 to ff 16 ), the brgi divides the count source frequency by (n + 1). in the clock synchronous serial i/o mode, brgi is valid when an internal clock is selected. at this time, the brgis output divided by 2 is the transfer clock. in the uart mode, the brgi is always valid. at this time, the brgis output divided by 16 is the transfer clock. when a value is written to addresses 31 16 , 39 16 , and 65 16 , the value is also written to the timer and the reload register whether transmission/reception is in progress or stopped. therefore, when writing a value to these addresses, be sure to perform it while transmission/reception is stopped. figure 8.2.13 shows the structure of brgi and figure 8.2.14 shows the block diagram of transfer clock generating section. 8.2 block description fig. 8.2.13 structure of uarti baud rate register (brgi) fig. 8.2.14 block diagram of transfer clock generating section b7 b0 uart0 baud rate register (address 31 16 ) uart1 baud rate register (address 39 16 ) uart2 baud rate register (address 65 16 ) functions bit at reset rw 7 to 0 values 00 16 to ff 16 can be set. assuming that the set value = n, brgi divides the count source frequency by (n + 1). un- defined wo brg i 1/2 transmit control circuit receive control circuit transfer clock for transmit operation transfer clock for receive operation transmit control circuit receive control circuit transfer clock for transmit operation transfer clock for receive operation brg i 1/16 f i : clock selected with the brg count source selection bits (f 2 , f 16 , f 64 , or f 512 ) f ext : clock input to the clki pin (external clock) 1/16 f i f ext f i f ext
serial i/o 7733 group users manual 8C18 at reset bit 7 to 4 not implemented. 3 interrupt request bit 2 1 0 interrupt priority level selection bits bit name un- defined 0 (note) 0 0 0 rw functions 0 0 0: level 0 (interrupt is disabled.) 0 0 1: level 1 priority is low. 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 priority is high. b2 b1 b0 0: no interrupt has occurred. 1: interrupt has occurred. b7 b6 b5 b4 b3 b2 b1 b0 a-d/uart2 trans./rece. interrupt control register (address 7 0 16 ) uart0 transmission interrupt control register (address 71 16 ) uart0 receive interrupt control register (address 72 16 ) uart1 transmission interrupt control register (address 73 16 ) uart1 receive interrupt control register (addresses 74 16 ) rw rw rw rw note: when the uart2 function is selected, bit 3 of the a-d conve rsion/uart2 trans./rece. interrupt control register is set to 1. accordingly, before enabling interrupts, write value 0 to this bit. 8.2.8 interrupt control register related to uarti when uarti is used, the following interrupts can be used: ua rti transmission interrupt and uarti reception interrupt. each interrupt has its corresponding in terrupt control register. however, in uart2, an interrupt for transmission and an interrupt for reception ar e controlled with the same register. figure 8.2.15 shows the structure of interrupt control registers related t o uarti. for details about interrupts, refer to chapter 4 interrupts. the uart2 transmission/reception interrupt and the a-d conve rsion interrupt share the same interrupt vector addresses and interrupt control register. switching between the a-d conversion interrupt and the uart2 transmission/reception interrupt is performed with bits 2 to 0 of the uart2 transmission/reception mode re gister. (refer to figure 8.2.3. ) 8.2 block description fig. 8.2.15 structure of interrupt control registers related to uarti
serial i/o 7733 group users manual 8C19 (1) interrupt priority level selection bits (bits 2 to 0) these bits are used to select the priority level of the uarti transmission interrupt or uarti reception interrupt. when using the uarti transmission/reception interrupt, select one of priority levels 1 to 7. when a uarti transmission/reception interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl) and the requested interrupt is enabled only when its priority level is higher than the ipl. (note that this is applied when the interrupt disable flag (i) = 0.) when these bits are set to 000 2 (level 0), the uarti transmission/reception interrupt is disabled. (2) interrupt request bit (bit 3) the uarti transmission interrupt request bit is set to 1 when data is transferred from the uarti transmission buffer register to the uarti transmission register. the uarti reception interrupt request bit is set to 1 when data is transferred from the uarti receive register to the uarti receive buffer register. note that these bits do not change when an overrun error occurs. when each interrupt request is accepted, the corresponding interrupt request bit is automatically cleared to 0. note that each bit can be set to 1 or cleared to 0 by software. 8.2 block description
serial i/o 7733 group users manual 8C20 8.2.9 ports p7 and p8 direction registers i/o pins of uarti are multiplexed with ports p7 and p8. when using the p7 4 , p8 2 and p8 6 pins as serial data input pins (rxdi), set the corresponding bits of the po rts p7 and p8 direction registers to 0 to set _____ these ports for the input mode. when using the p7 2 pin as the cts 2 input pin, set bit 2 of the port p7 direction register to 0 to set this port for the input mod e. when using the p7 3 , p7 5 , p8 0 , p8 1 , p8 3 Cp8 5 , _________ _________ and p8 7 pins as uartis i/o pins ( ctsi / rtsi , clki, txdi), these pins are forcibly set as the uartis i/ o pins, regardless of the ports p7 and p8 direction registers contents. also, as for clks 0 and clks 1 , refer to section 8.3.1 (4) number of transfer clock output pins (uart0). figure 8.2.16 shows the relationship between the ports p7, p8 direction registers and uartis i/o pins. note that the functions of the uartis i/o pins can be switc hed by software. for details, refer to the description of each operating mode. 8.2 block description bit corresponding pin name functions 0 1 2 3 4 5 6 7 pin p7 4 /an 4 /rxd 2 pin p7 6 /an 6 /x cout 0: input mode 1: output mode when using pin p7 2 as the cts 2 input pin and using pin p7 4 as serial datas input pin (rxd 2 ), set the corresponding bit to 0. pin p7 5 /an 5 / ad trg /txd 2 port p 7 direction register (address 11 16 ) b1 b0 b2 b3 b4 b5 b6 b7 pin p7 0 /an 0 pin p7 2 /an 2 / cts 2 pin p7 3 /an 3 /clk 2 pin p7 1 /an 1 pin p7 7 /an 7 /x cin at reset rw 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 pin p8 0 / cts 0 / rts 0 /clks 1 pin p8 2 /rxd 0 /clks 0 pin p8 3 /txd 0 pin p8 4 / cts 1 / rts 1 pin p8 6 /rxd 1 pin p8 5 /clk 1 port p8 direction register (address 14 16 ) b1 b0 b2 b3 b4 b5 b6 b7 pin p8 1 /clk 0 pin p8 7 /txd 1 rw 0 0 0 0 0 0 0 0 not used for serial i/o corresponding pin name functions bit at reset 0: input mode 1: output mode when using pins p8 2 and p8 6 as serial datas input pins (rxd 0 , rxd 1 ), set the corresponding bits to 0. rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw note: for pins clks 0 and clks 1 , refer to section 8.3.1 (4) number of transfer clock output pins (uart0). fig. 8.2.16 relationship between ports p7, p8 direction regi ster and uartis i/o pins :
serial i/o 7733 group users manual 8C21 ____ note: the rts function is not assigned for uart2. table 8.3.2 functions of i/o pins in clock synchronous serial i/o mode 8.3 clock synchronous serial i/o mode table 8.3.1 lists the performance overview in the clock synchronous serial i/o mode and table 8.3.2 lists the functions of i/o pins in this mode. table 8.3.1 performance overview in clock synchronous serial i/o mode item transfer data format transfer rate transmit/receive control functions transfer data has a length of 8 bits. lsb first or msb first is selected by software. brgis output divided by 2 maximum of 5 mbps ____ ____ cts function or rts function is selected by software ( note ). when internal clock is selected when external clock is selected pin name txdi (p8 3 , p8 7 , p7 5 ) rxdi (p8 2 , p8 6 , p7 4 ) clki (p8 1 , p8 5 , p7 3 ) _________ _________ cts 0 / rts 0 (p8 0 ), _________ _________ cts 1 / rts 1 (p8 4 ) ( note 1 ) _________ cts 2 (p7 2 ) functions serial data output serial data input transfer clock output transfer clock input ____ cts input ____ rts output programmable i/o port ____ cts input programmable i/o port method of selection (they output dummy data when only reception is performed.) ports p7 and p8 direction registers corresponding bits =0 (they can be used as input ports when only transmission is performed.) internal/external clock selection bit = 0 internal/external clock selection bit = 1 ____ ____ cts / rts enable bit = 0 ____ ____ cts / rts function selection bit = 0 ____ ____ cts / rts enable bit = 0 ____ ____ cts / rts function selection bit = 1 ____ ____ cts / rts enable bit = 1 ____ cts enable bit = 0 ____ cts enable bit = 1 port p7 direction register: address 11 16 port p8 direction register: address 14 16 internal/external clock selection bit: bit 3 at addresses 30 16 , 38 16 , and 64 16 ____ ____ cts / rts enable bit: bit 4 at addresses 34 16 and 3c 16 ____ ____ cts / rts function selection bit: bit 2 at addresses 34 16 and 3c 16 ____ cts enable bit: bit 2 at address 68 16 h the txdi pin outputs h level from when a uartis operating mode is selected until transfer starts. (the txdi pin is in a floating state when n-channel open-drain output is selected.) h in uart0, multiple transfer clock output pins can be used. (refer to table 8.3.3. ) ____ notes 1: the rts function is not assigned for uart2. 2: as for clks 0 and clks 1 , refer to section 8.3.1 (4) number of transfer clock output pins (uart0). 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C22 8.3.1 transfer clock (sync clock) data is transferred synchronously with the transfer clock. for the transfer clock, the following items can be specified: l whether to generate the transfer clock internally or to input it from the external. l polarity of a clock which is output from the clki pin (uart0, uart1) l number of transfer clock output pins (uart0). note that the transfer clock is generated while the transmit control circuit is operating. therefore, even when performing only reception, set the transmit enable bit to 1 and make the transmit control circuit operate by setting dummy data into the uarti transmission buffer register. (1) how to generate transfer clock internally a count source is selected with the brg count source selection bits. the count source is divided in the brgi, and then the brgis output is further divided by 2. (in this way, the transfer clock is generated.) this transfer clock is output from the clki pin. [setting for related registers] l an internal clock is selected (bit 3 at addresses 30 16 , 38 16 , and 64 16 = 0). l the brgis count source is selected (bits 1 and 0 at addresses 34 16 , 3c 16 , and 68 16 ). l a value of divide value C 1 (= n: 00 16 to ff 16 ) is set into the brgi (addresses 31 16 , 39 16 , and 65 16 ). transfer clocks frequency = fi: brgis count source frequency (f 2 , f 16 , f 64 , and f 512 ) l transmission is enabled (bit 0 at addresses 35 16 , 3d 16 , and 69 16 = 1). l data is set into the uarti transmission buffer register (addresses 32 16 , 3a 16 , and 66 16 ) [pin status] l transfer clock is output from the clki pin. l serial data is output from the txdi pin. (dummy data is output when only reception is performed.) (2) how to input transfer clock from the external a clock which is input from the clki pin is the transfer clock. [setting related registers] l an external clock is selected (bit 3 at addresses 30 16 , 38 16 , and 64 16 = 1). l transmission is enabled (bit 0 at addresses 35 16 , 3d 16 , and 69 16 = 1). l data is set into the uarti transmission buffer register (addresses 32 16 , 3a 16 , 66 16 ). [pin status] l transfer clock is input from the clki pin. l serial data is output from the txdi pin. (dummy data is output when only reception is performed.) fi 2 (n+1) 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C23 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i d 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i d 0 d 0 when clk polarity selection bit = ?. h the transmit data is output to the txdi pin at the rising edge of the transfer clock; the receive data is input from the rxdi pin at the falling edge of the transfer clock. when not transferring, the clki pin? level is ?. when clk polarity selection bit = ?. h the transmit data is output to the txdi pin at the falling edge of the transfer clock; the receive data is input from the rxdi pin at the rising edge of the transfer clock. when not transferring, the clki pin? level is ?. (3) how to select polarity of transfer clock the polarity of a clock which is output from the clki pin can be selected with the clk polarity selection bit (uart0, uart1) as shown in figure 8.3.1. the clk polarity select bit is not implemented for uart2. the clk 2 pin outputs the transmit data at the fall of the transfer clock; this pin inputs the receive data at the rise of the transfer clock. [setting for related registers] l the clk polarity is selected (bit 6 at addresses 34 16 , 3c 16 ). fig. 8.3.1 polarity of transfer clock 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C24 m37733mhbxxxfp t x d 0 clks 1 clks 0 clk 0 in clk in clk in clk note: this is applied when the following conditions are satisfied: ?nly transmission is performed. ?lock synchronous serial i/o mode is selected. ?n internal clock is selected. (4) number of transfer clock output pins (uart0) only in uart0, when an internal clock is selected, one pin can be selected as the transfer clock output pin from the following pins: clk 0 , clks 0 (in common with rxd 0 ), and clks 1 (in common with ____ ____ cts 0 / rts 0 ). by this selection, data can be transmitted to the maximum of three external receiving devices. (refer ____ ____ to in table 8.3.4 ). in this case, since the rxd 0 and cts 0 / rts 0 pins function as the transfer clock ____ ____ output pins (clk 0 , clks 1 ), the cts / rts function and reception are disabled. _____ ____ when only the clk 0 and clks 0 pins are used as the transfer clock output pins, the p8 0 ( cts 0 / rts 0 / clks 1 ) pin can be used as a programmable i/o port. (refer to in table 8.3.4. ) also, when the clk 0 and clks 1 pins are used as the transfer clock output pins and bit 2 of the port p8 direction register is set to 0, data can be received from the rxd 0 pin. (refer to a in table 8.3.4. ) [setting for related registers] l an internal clock is selected (bit 3 at address 30 16 = 0). ____ ____ l the cts / rts function is disabled (bit 4 at address 34 16 = 1). l reception is disabled (bit 2 at address 35 16 = 0). (refer to and in table 8.3.4. ) l number of transfer clock output pins is selected. (bits 5 and 4 at address 6e 16 ; refer to table 8.3.3.) l conditions for output when not transferring (described later) are set. (clks 0 : bit 2 at address 14 16 = 1: clks 1 : bit 0 at address 14 16 = 1, bit 0 at address 12 16 = level at output when not transferring) [pin status] refer to table 8.3.3 . table 8.3.3 pin functions when one transfer clock output pin is selected transfer clock output pin selection bits number of pins from which one transfer clock output pin is selected 1 selectable b5 0 0 1 1 b4 0 1 0 1 txd 0 (p8 3 ) outputs serial data. clk 0 (p8 1 ) outputs transfer clock. outputs transfer clock. output when not transferring* output when not transferring* rxd 0 /clks 0 (p8 2 ) programmable i/o port h outputs transfer clock. h output when not transferring*: when the clk polarity selection bit (bit 6 at address 34 16 ) = 0, the clk 0 pin outputs h level; when this bit = 1, the clk 0 pin outputs l level. h when bit 2 at address 14 16 (port p8 direction register) = 0, the rxd 0 /clks 0 pin is in a floating state; when this bit = 1, the rxd 0 /clks 0 pin do the processing of output when not transferring. functions fig. 8.3.2 connection example when one transfer clock output pin is selected from three pins ____ ____ cts 0 / rts 0 /clks 1 (p8 0 ) programmable i/o port programmable i/o port programmable i/o port outputs transfer clock. 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C25 [switching of transfer clock output pin] when the transfer clock output pin is switched while transmission is enabled, follow the procedure described below. transmission starts when step a is executed: check whether the previous transfer is completed or not. (refer to figure 8.3.6. ) if the previous transfer has been completed, change the contents of the transmit clock output pin selection bit. a set the transmit data. for usage examples, refer to section 17.2.2 examples of transmission for several peripheral ics (clock synchronous serial i/o mode). table 8.3.4 number of channels for serial i/o transmission/reception for the case where multiple transfer clock output pins are used pin ____ ____ cts 0 / rts 0 /clks 1 (p8 0 ) clk 0 (p8 1 ) rxd 0 /clks 0 (p8 2 ) txd 0 (p8 3 ) ?number of channels for serial i/o transmission/ reception ?status of transmit clock output pin selection bits (b5, b4) setting example a outputs transfer clock. outputs transfer clock. receives data. transmits data. 1 channel for transmission clks 1 txd 0 1 channel for transmission/reception clk 0 rxd 0 txd 0 programmable i/o port outputs transfer clock. outputs transfer clock. transmits data. 2 channels for transmission clk 0 txd 0 clks 0 txd 0 outputs transfer clock. outputs transfer clock. outputs transfer clock. transmits data. 3 channels for transmission clks 1 txd 0 clk 0 txd 0 clks 0 txd 0 (1, 1) (0, 1) (1, 0) (0, 1) (1, 0) (1, 1) (0, 1) note: set bit 2 at address 14 16 (port p8 direction register) to 0. 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C26 db 7 d 7 db6 d 6 db5 d 5 db4 d 4 db3 d 3 db2 d 2 db1 d 1 db 0 d 1 db 7 d 7 db6 d 6 db5 d 5 db4 d 4 db3 d 3 db2 d 2 db1 d 1 db0 d 0 db 7 d 7 db 6 d 6 db 5 d 5 db 4 d 4 db 3 d 3 db 2 d 2 db 1 d 1 db 0 d 0 db7 d 7 db6 d 6 db5 d 5 db4 d 4 db3 d 3 db2 d 2 db1 d 1 db0 d 0 transfer format selection bit transfer data format when data is written to uarti transmission buffer register when data is read from uarti receive buffer register 0 lsb (least significant bit) first data bus uarti transmission buffer register data bus uarti receive buffer register 1 msb (most significant bit) first data bus uarti transmission buffer register data bus uarti receive buffer register 8.3.2 transfer data format lsb-first or msb-first can be selected (uart0, uart1). table 8.3.5 lists the relationship between the transfer data format and the way to write/read to and from t he uarti transmission/receive buffer register. by setting the transfer format selection bit (bit 7 at addre sses 34 16 , 3c 16 ), transfer data format can be selected. when this bit is cleared to 0, the set data is written to the uarti transmission buffer register as the transmit data. similarly, the data in the uarti receive buff er register is read out as the receive data. (refer to the upper row in table 8.3.5. ) when this bit is set to 1, each bits position of the set data is reversed, and then this data is written to the uarti transmission buffer register as the transmit data. similarly, each bits position of data in the uarti receive buffer register is reversed, and then this dat a is read out as the receive data. (refer to the lower row in table 8.3.5. ) note that only the way to write/read to and from the uarti t ransmission/receive buffer register is affected by the transfer data format. the transmit/receive operation is unaffected. the transfer data format for uart2 is fixed to lsb-first. table 8.3.5 relationship between transfer data format and w ay to write/read to and from uarti transmission/receive buffer register 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C27 8.3.3 method of transmission figures 8.3.3 and 8.3.4 show initial setting examples for related registers when transmitting. transmission is started when all of the following conditions ( to a ) are satisfied. when an external clock is selected, satisfy conditions to a with the following preconditions satisfied. [preconditions for uart0 and uart1] ? the clki pins input is at h level. (when an external clock is selected and the clk polarity selection bit = 0.) ? the clki pins input is at l level. (when an external clock is selected and the clk polarity selection bit = 1.) note: when an internal clock is selected, the above preconditions are ignored. [preconditions for uart2] ? the clki pins input is at h level. (when an external clock is selected) note: when an internal clock is selected, the above precondition is ignored. transmit enable state (transmit enable bit = 1) transmit data is present in the uarti transmission buffer register (transmission buffer empty flag = 0). _____ ____ a the ctsi pins input is at l level (when the cts function is selected) ____ note: when the cts function is not selected or in uart2, this condition is ignored. ____ ____ by connecting the rtsi pin (receiver side) and ctsi pin (transmitter side), the timing of transmission and that of reception can be matched (uart0, uart1). for details, refer to section 8.3.6 receive operation. when using interrupts, settings for enabling interrupts are required. for details, refer to chapter 4. interrupts. figure 8.3.5 shows how to write data after transmission is started and figure 8.3.6 shows how to detect the transmit completion. 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C28 multiple transfer clock output pins can be selected when performing only transmission with an internal clock selected in uart0. in this case, the cts function cannot be used. 0 0: one transfer clock output pin 0 1: 1 0: multiple transfer clock output pins 1 1: the cts / rts function selection bit is valid when the cts / rts enable bit = 0. note 2: 1 0 0 0 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) uart2 transmit/receive mode register (address 64 16 ) b7 b0 internal/external clock selection bit 0: internal clock 1: external clock : it may be 0 or 1. 5 55 5 clock synchronous serial i/o mode h continued to initial setting example for related registers when transmi tting (2) on the next page uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source selection bits cts / rts function selection bit (note 2) 0: the cts function is selected. 1: the rts function is selected. ( cts function is disabled.) cts / rts enable bit 0: the cts / rts function is enabled. 1: the cts / rts function is disabled. data output selection bit 0: t x d i pin is set for cmos output. 1: t x d i pin is set for n-channel open-drain output. clk polarity selection bit 0: at the falling edge of the transfer clock, transmit data is output. 1: at the rising edge of the transfer clock, transmit data i s output. transfer format selection bit 0: lsb first 1: msb first clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b1 b0 b7 b0 transmission clock output pin selection bits serial transmit control register (address 6e 16 ) b5 b4 uart2 transmit/receive control register 0 (address 68 16 ) b7 b0 brg count source selection bits cts enable bit 0: the cts function is enabled. 1: the cts function is disabled (i/o port). 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b1 b0 note 1: nothing is implemented to bit 7 of uart2 transmit/receive m ode register. fig. 8.3.3 initial setting example for related registers whe n transmitting (1) 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C29 uart0 transmission buffer register (address 32 16 ) uart1 transmission buffer register (address 3a 16 ) uart2 transmission buffer register (address 66 16 ) b7 b0 transmit data is set here. transmission is started. uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) uart2 baud rate register (brg2) (address 65 16 ) b7 b0 a value from 00 16 to ff 16 is set. h necessary only when internal clock is selected. port p8 register (address 12 16 ) b7 b0 5 set the output level of clks1 pin when not transferring 0: ??(when clock polarity selection bit = ?? 1: ??(when clock polarity selection bit = ?? uart0 transmission interrupt control register (address 71 16 ) uart1 transmission interrupt control register (address 73 16 ) a-d/uart2 trans./rece. interrupt control register (address 70 16 ) b7 b0 interrupt priority level selection bits when using interrupts, one of level 1 to 7 must be set. when disabling interrupts, level 0 must be set. continued from ?nitial setting example for related registers when transmitting (1)? on the preceding page (if the cts function is selected, transmission is started when the cts i pin? input level is ?.? port p8 direction register (address 14 16 ) b7 b0 1 5 1 5 clks1 pin clks0 pin 5 5 h 1 h 2 h 1: set this bit only when the number of the transfer clock output pins is 3. h 1 5 : it may be ??or ?. h 2: set this bit only when the number of the transfer clock output pins is 2 or 3. 0 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 b0 transmit enable bit 1: transmission is enabled. fig. 8.3.4 initial setting example for related registers when transmitting (2) 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C30 [when not using interrupts] [when using interrupts] a uarti transmission interrupt request occurs when the uarti transmission buffer register becomes empty. uarti transmission interrupt h uart0 transmission buffer register (address 32 16 ) uart1 transmission buffer register (address 3a 16 ) uart2 transmission buffer register (address 66 16 ) b7 b0 writing of next transmit data transmit data is set here. uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 transmission buffer empty flag 0: data is present in the transmission buffer register. 1: no data is present in the transmission buffer register. (next transmit data can be written.) checking status of the uarti transmission buffer register 1 this diagram indicates bits and registers required for processing. refer to figure 8.3.8 for details about the change of flag status and the occurrence timing of an interrupt request. b0 fig. 8.3.5 how to write data after transmission is started 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C31 [when not using interrupts] [when using interrupts] uarti transmission interrupt h uart0 transmission interrupt control register (address 71 16 ) uart1 transmission interrupt control register (address 73 16 ) a-d/uart2 trans./rece. interrupt control register (address 70 16 ) b7 b0 interrupt request bit checking the start of transmission uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) uart2 transmit/receive control register 0 (address 68 16 ) b7 b0 checking the completion of transmission transmission register empty flag 0: transmission is in progress. 1: transmission is completed. processing at completion of transmission 0: 1: no interrupt request has occurred. interrupt request has occurred. (transmission has been started.) a uarti transmission interrupt request occurs when the transmission is started. this diagram indicates bits and registers required for processing. refer to figure 8.3.8 for details about the change of flag status and the occurrence timing of an interrupt request. note: nothing is allocated to bits 7 to 4 of the uart2 transmit/receive control register 0. fig. 8.3.6 how to detect of transmit completion 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C32 8.3.4 transmit operation when the transmit conditions described in section 8.3.3 method of transmission are satisfied while an internal clock is selected, the transfer clock is generated. and then, the following operations are automatically performed after one cycle of the transfer clock has passed. when the transmit conditions are satisfied and the external clock is input to the clki pin while the external clock is selected, the following operations are automatically performed. l the uarti transmission buffer registers contents is transferred to the uarti transmission register. l the transmission buffer empty flag is set to 1. l the transmission register empty flag is cleared to 0. l a uarti transmission interrupt request occurs and the interrupt request bit is set to 1. l eight transfer clocks are generated (when an internal clock is selected). the transmit operation is described below. data in the uarti transmission register is transmitted from the txdi pin synchronously with the valid edge h of the clki pins clock. this data is transmitted bit by bit sequentially beginning with the least significant bit (lsb). a when one byte of data has been transmitted, the transmission register empty flag is set to 1. this indicates the completion of transmission. valid edge h : in uart0 and uart1, this means the falling edge when the clk polarity selection bit = 0 and the rising edge when the clk polarity selection bit = 1; in uart2, this means the rising edge. figure 8.3.7 shows the transmit operation. when an internal clock is selected, if the transmit conditions for the next data are satisfied at completion of transmission, the next transfer clock is generated immediately. accordingly, when performing transmission in succession, set the next transmit data to the uarti transmission buffer register during transmission (when the transmission register empty flag = 0). when the transmit conditions for the next data are not satisfied, the transfer clock stops at h level when the clk polarity selection bit = 0, and it stops at l level when the clk polarity selection bit = 1. ____ figure 8.3.8 shows an example of transmit timing (when an internal clock and the cts function are selected). 4 8.3 clock synchronous serial i/o mode
serial i/o 7733 group users manual 8C33 fig. 8.3.7 transmit operation ____ fig. 8.3.8 example of transmit timing (when internal clock a nd cts function are selected) 8.3 clock synchronous serial i/o mode clki pins clock uarti transmission buffer register d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 7 d 6 d 5 d 4 d 3 transmit data msb b7 b0 d 0 d 1 d 2 d 7 lsb h uarti transmission register this is applied when the clk polarity selection bit = 0. when the clk polarity selection bit = 1, data is shifted a t the rising edge of the transfer clock of clki pin. d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk cts i clk i t end i txd i h l 0 1 0 1 0 1 0 1 data is set in uarti transmission buffer register. transmit enable bit transmission buffer empty flag transfer clock stopped because ctsi pins level = h uarti transmission register ? uarti transmission buffer register the above timing diagram is applied when the following conditions are satisfied: ? internal clock is selected. cts function is selected. clk polarity selection bit = 0. uarti transmit interrupt request bit cleared to 0 when an interrupt request is accepted; otherw ise, cleared by software. transmission register empty flag stopped because transmit enable bit = 0 t endi : next transmit conditions are checked when this signal leve l becomes h. (t endi is an internal signal. accordingly, it cannot be read from the external.) tc = t clk = 2(n+1)/f i f i : brg i s count source frequency (f 2 , f 16 , f 64 , or f 512 ) n: value set to brg i ? ?
serial i/o 7733 group users manual 8C34 8.3 clock synchronous serial i/o mode ____ fig. 8.3.9 example of transmit timing (when internal clock is selected and cts function is not selected) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk clk i t end i txd i ? ? ? ? ? ? ? ? d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 data is set in uarti transmission buffer register. transmit enable bit transmission buffer empty flag transfer clock uarti transmission register ? uarti transmission buffer register the above timing diagram is applied when the following conditions are satisfied: ?? internal clock is selected. ?? cts function is not selected. ?? clk polarity selection bit = ?.? t endi : next transmit conditions are checked when this signal level becomes ?.? (t endi is an internal signal. accordingly, it cannot be read from the external.) tc = t clk = 2(n+1)/f i f i : brg i ? count source frequency (f 2 , f 16 , f 64 , or f 512 ) n: value set to brg i uarti transmit interrupt request bit cleared to ??when an interrupt request is accepted; otherwise, cleared by software. transmission register empty flag stopped because transmit enable bit = ?
serial i/o 7733 group users manual 8C35 8.3 clock synchronous serial i/o mode 8.3.5 method of reception figures 8.3.10 and 8.3.11 show initial setting examples for related registers when receiving. reception is started when all of the following conditions ( to a ) are satisfied. when an external clock is selected, satisfy conditions to a with the following preconditions satisfied. [preconditions for uart0 and uart1] ? the clki pins input is at h level. (when an external clock is selected and the clk polarity selection bit = 0.) ? the clki pins input is at l level. (when an external clock is selected and the clk polarity selection bit = 1.) note: when an internal clock is selected, the above preconditions are ignored. [preconditions for uart2] ? the clki pins input is at h level. (when an external clock is selected) note: when an internal clock is selected, the above precondition is ignored. receive enable state (receive enable bit = 1) transmit enable state (transmit enable bit = 1) a dummy data is present in the uarti transmission buffer register (transmission buffer empty flag = 0). ____ ____ by connecting the rtsi pin (receiver side) and ctsi pin (transmitter side), the timing of transmission and that of reception can be matched (uart0, uart1). for details, refer to section 8.3.6 receive operation. when using interrupts, settings for enabling interrupts are required. for details, refer to chapter 4. interrupts. figure 8.3.12 shows the processing after reception is completed.
serial i/o 7733 group users manual 8C36 8.3 clock synchronous serial i/o mode h necessary only when an internal clock is selected. uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) uart2 baud rate register (brg2) (address 65 16 ) b7 b0 a value from 00 16 to ff 16 is set. notes 2: the cts / rts function selection bit is valid when the cts / rts enable bit = ?. the rts function is ignored when an internal clock is selected. 3: the rts output function is not assigned for uart2. 1 0 0 0 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) uart2 transmit/receive mode register (address 64 16 ) b7 b0 internal/external clock selection bit 0: internal clock 1: external clock : it may be ??or ?. 5 5 5 5 clock synchronous serial i/o mode continued to ?nitial setting example for related registers when receiving (2)? on the next page uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source selection bits cts / rts function selection bit (note 2) 0: the cts function is selected. (the rts function is disabled.) 1: the rts function is selected. cts / rts enable bit 0: the cts / rts function is enabled. 1: the cts / rts function is disabled. clk polarity selection bit 0: the receive data is input at the rising edge of the transfer clock. 1: the receive data is input at the falling edge of the transfer clock. transfer format selection bit 0: lsb first 1: msb first clocks f 2 , f 16, f 64, and f 512 : refer to chapter ?4. clock generating circuit. 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b1b0 notes 1: nothing is implemented to bit 7 of the uart2 transmit/receive mode register. uart2 transmit/receive control register 0 (address 68 16 ) b7 b0 brg count source selection bits cts enable bit 0: the cts function is enabled. 1: the cts function is disabled ( i/o port ). 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b1b0 fig. 8.3.10 initial setting example for related registers when receiving (1)
serial i/o 7733 group users manual 8C37 8.3 clock synchronous serial i/o mode port p8 direction register (address 14 16 ) b7 b0 0 r x d 0 pin 0 r x d 1 pin continued from ?nitial setting example for related registers when receiving (1)? on the proceeding page uart0 receive interrupt control register (address 72 16 ) uart1 receive interrupt control register (address 74 16 ) a-d/uart2 trans./rece. interrupt control register (address 70 16 ) b7 b0 interrupt priority level selection bits when using interrupts, one of level 1 to 7 must be set. when disabling interrupts, level 0 must be set. uart0 transmission buffer register (address 32 16 ) uart1 transmission buffer register (address 3a 16 ) uart2 transmission buffer register (address 66 16 ) b7 b0 dummy data is set. uart0 transmit/receive control register 1(address 35 16 ) uart1 transmit/receive control register 1(address 3d 16 ) uart2 transmit/receive control register 1(address 69 16 ) b7 b0 transmit enable bit ( note 2 ) 1: transmission is enabled. 1 1 receive enable bit ( note 2 ) 1: receptipn is enabled. reception is started. notes 2: set the receive enable bit and the transmit enable bit to ??simultaneously. port p7 direction register (address 11 16 ) b7 b0 0 r x d 2 pin ( note 1 ) 0 notes 1: in the 7733 group or the 7735 group, set this bit. in the 7736 group, it is not necessary to set this bit. fig. 8.3.11 initial setting example for related registers when receiving (2)
serial i/o 7733 group users manual 8C38 8.3 clock synchronous serial i/o mode [when not using interrupts] [when using interrupts] a uarti receive interrupt request occurs when reception is completed. uarti receive interrupt this diagram indicates bits and registers required for processing. refer to figure 8.3.15 for details about the change of flag status and the occurrence timing of an interrupt request. processing after reading out receive data uart0 receive buffer register (address 36 16 ) uart1 receive buffer register (address 3e 16 ) uart2 receive buffer register (address 6a 16 ) b7 b0 reading of the receive data receive data is read out. uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 b0 receive completion flag 0: reception is not completed. 1: reception is completed. checking the completion of reception 1 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 b0 checking the error overrun error flag 0: no overrun error is detected. 1: error is detected. 1 1 h fig. 8.3.12 processing after reception is completed
serial i/o 7733 group users manual 8C39 8.3 clock synchronous serial i/o mode 8.3.6 receive operation when the receive conditions described in section 8.3.5 method of reception are satisfied while an internal clock is selected, the transfer clock is generated. and then, the receive is started after one cycle of the transfer clock has passed. when the receive conditions are satisfied while the external clock is selected, uarti is in the reception enabled state. then, the external clock is input to the clki pin and reception is started. ____ _____ in uart0 and uart1, when the rts function is selected with an external clock selected, the rtsi pins output level is l, and the microcomputer informs the transmitter side that reception is enabled. when ____ ____ ____ reception is started, the rtsi pins output level is h. accordingly, by connecting the rtsi pin to the ctsi pin of the transmitter side, the timing of transmission and that of reception can be matched. ____ ____ _ when an internal clock is selected, do not use the rts function because the rtsi output is undefined. figure 8.3.13 shows a connection example. ____ the rts output function is not assigned for uart2. the receive operation is described below. the signal which is input from the rxdi pin is taken in the most significant bit of the uarti receive register synchronously with the valid edge h of the clock which is output from the clki pin or input to the clki pin. the contents of the uarti receive register is shifted by 1 bit to the right. a operations and are repeated at each valid edge of the clock which is output from the clki pin or input to the clki pin. ? when one byte of data is prepared in the uarti receive register, the contents of this register is transferred to the uarti receive buffer register. ? simultaneously with ? , the receive completion flag is set to 1. at this time, a receive interrupt request occurs, and then an interrupt request bit is set to 1. valid edge h : in uart0 and uart1, this means the rising edge when the clk polarity selection bit = 0 and the falling edge when the clk polarity selection bit = 1; in uart2, this means the rising edge. the receive completion flag is cleared to 0 when the low-order byte of the uarti receive buffer register ____ is read out. the rtsi pin continues to output h level until the receive conditions are next satisfied (when ____ the rts function is selected). figure 8.3.14 shows the receive operation and figure 8.3.15 shows an example of receive timing (when an external clock is selected). when the contents of the uarti receive buffer register is read out with the transfer format selection bit = 1 (msb first), each bits position of this registers contents is reversed and the resultant data is read out (uart0, uart1).
serial i/o 7733 group users manual 8C40 8.3 clock synchronous serial i/o mode txd i rxd i clk i cts i txd i rxd i clk i rts i ( note ) transmitter side receiver side note: the rts i output function is not assigned for clock which is output from or input to clki pin uarti receive buffer register uarti receive register c d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 0 d 1 d 0 receive data c msb b7 b0 lsb d 2 d 1 d 0 h this is applied when the clk polarity selection bit = ?. when the clk polarity selection bit = ?,?data is shifted at the falling edge of the clock which is output from or input to the clki pin. fig. 8.3.14 receive operation fig. 8.3.13 connection example
serial i/o 7733 group users manual 8C41 8.3 clock synchronous serial i/o mode 1 / f ext ( note ) rts i clk i rxd i ? ? ? ? ? ? ? ? ? ? ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 dummy data is set in uarti transmission buffer register. transmit enable bit transmission buffer empty flag receive completion flag receive enable bit received data is taken in. uarti transmission register ? uarti transmission buffer register uarti receive buffer register is read out. the above timing diagram is applied when the following conditions are satisfied: ?? external clock is selected. ?? rts function is selected. ?? clk polarity selection bit = ?.? f ext : frequency of external clock when the clki pin? input level is ?,?satisfy the following conditions: ?? transmit enable bit ? ? ?? receive enable bit ? ? ?? writing of dummy data to uarti transmission buffer register uarti receive register ? uarti receive buffer register uarti receive interrupt request bit cleared to ??when an interrupt request is accepted; otherwise, cleared by software. note: the rtsi output function is not assigned for uart2. fig. 8.3.15 example of receive timing (when external clock is selected)
serial i/o 7733 group users manual 8C42 8.3 clock synchronous serial i/o mode 8.3.7 processing when an overrun error is detected in the clock synchronous serial i/o mode, an overrun error can be detected. an overrun error occurs when the next data is prepared in the uarti receive register with the receive completion flag = 1 (in other words, data is present in the uarti receive buffer register), and then the next data is transferred to the receive buffer register. in other words, when the next data is prepared before the contents of the uarti receive buffer register is read out, an overrun error occurs. when an overrun error occurs, the next data is written into the uarti receive buffer register. at this time, the uarti receive interrupt request bit does not change. an overrun error is detected when data is transferred from the uarti receive register to the uarti receive buffer register. at this time, the overrun error flag is set to 1. the overrun error flag is cleared to 0 when the serial i/o mode selection bits are cleared to 000 2 or when the receive enable bit is cleared to 0. when an overrun error occurs during reception, initialize the overrun error flag and the uarti receive buffer register, and then perform reception again. when it is necessary to perform transmission owing to an overrun error which occurs in the receiver side, set the uarti transmission buffer register again, and then starts transmission again. the method of initializing the uarti receive buffer register and that of setting the uarti transmission buffer register again are described below. (1) method of initializing uarti receive buffer register clear the receive enable bit to 0. (reception is disabled.) set the receive enable bit to 1 again. (reception is enabled.) (2) method of setting uarti transmission buffer register again clear the serial i/o mode selection bits to 000 2 . (serial i/o is ignored.) set the serial i/o mode selection bits to 001 2 again. a set the transmit enable bit to 1. (transmission is enabled.) and set the transmit data to the uarti transmission buffer register.
serial i/o 7733 group users manual 8C43 8.3 clock synchronous serial i/o mode 8.3.8 precautions for clock synchronous serial i/o 1. the transfer clock is generated by the operation of the transmit control circuit. accordingly, even when performing only reception, the transmit operation (setting for transmission) must be performed. in this case, dummy data is output from the txdi pin to the external. 2. when an internal clock is selected during reception, the transfer clock is generated if the following conditions are satisfied: ?the transmit enable bit is set to 1. (transmission is enabled.) ?dummy data is set to the uarti transmission buffer register. when an external clock is selected during reception, the transfer clock is generated if the following conditions are satisfied: ?the transmit enable bit is set to 1. ?a clock is input to the clki pin after dummy data is set to the uarti transmission buffer register. 3. when an external clock is selected, make sure that the following conditions are satisfied with the clki pins input level = h if the clk polarity selection bit = 0 or with the clki pins input level = l if the clk polarity selection bit = 1: [at transmitting] set the transmit enable bit to 1. write the transmit data to the uarti transmission buffer register. _____ ____ a input l level to the ctsi pin (when cts function is selected). [at receiving] set the receive enable bit to 1. set the transmit enable bit to 1. a write dummy data to the uarti transmission buffer register. 4. when receiving data in succession, set dummy data to the low-order byte of the uarti transmission buffer register each time when 1-byte data is received. 5. for performing the transmission and the reception simultaneously, uart2 does not distinguish the transmission interrupt from the reception interrupt. the uart2 transmission/reception interrupt request occurs when either interrupt request occurs. accordingly, in the system which performs the transmission and reception simultaneously for uart2, not use the uart2 transmission/reception interrupt but use the method of poling the transmission buffer empty flag and the receive completion flag by software.
serial i/o 7733 group users manual 8C44 8.4 clock asynchronous serial i/o (uart) mode 8.4 clock asynchronous serial i/o (uart) mode table 8.4.1 lists the performance overview in the uart mode and table 8.4.2 lists the functions of i/o pins in this mode. table 8.4.1 performance overview in uart mode functions 1 bit 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (odd or even can be selected.) 1 bit or 2 bits brgis output divided by 16 (maximum of 781.25 kbps (note) ) maximum of 312.5 kbps 4 types (overrun, framing, parity, and summing) presence of error can be detected only by checking error sum flag. item start bit character bit (transfer data) parity bit stop bit when internal clock is selected when external clock is selected transfer data format transfer rate error detection note: this is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0 and the system clock frequency = 25 mhz (f(f 2 ) = 12.5 mhz). (for details, refer to chapter 14. clock generating circuit. table 8.4.2 functions of i/o pins in uart mode pin name txdi (p8 3 , p8 7 , p7 5 ) rxdi (p8 2 , p8 6 , p7 4 ) clki (p8 1 , p8 5 , p7 3 ) ____ ____ ctsi / rtsi ( note ) (p8 0 , p8 4 ) cts 2 (p7 2 ) functions serial data output serial data input programmable i/o port brgi count source input ____ cts input ____ rts output programmable i/o port ____ cts input programmable i/o port method of selection (they cannot be used as programmable i/o ports.) ports p7 and p8 direction registers corresponding bit = 0 (they can be used as input ports when only transmission is performed.) internal/external clock selection bit = 0 internal/external clock selection bit = 1 ____ ____ cts / rts enable bit = 0 ____ ____ cts / rts function selection bit = 0 ____ ____ cts / rts enable bit = 0 ____ ____ cts / rts function selection bit = 1 ____ ____ cts / rts enable bit = 1 ____ cts enable bit = 0 ____ cts enable bit = 1 port p7 direction register: address 11 16 port p8 direction register: address 14 16 internal/external clock selection bit: bit 3 at addresses 30 16 , 38 16 , and 64 16 ____ ____ cts / rts enable bit: bit 4 at addresses 34 16 and 3c 16 ____ ____ cts / rts function selection bit: bit 2 at addresses 34 16 and 3c 16 ____ cts enable bit: bit 2 at addresses 68 16 h the txdi pin outputs h level while not transmitting after a uartis operating mode is selected. (the txdi pin is in a floating state when n-channel open-drain output is selected.) ____ note: the rtsi output function is not assigned for uart2.
serial i/o 7733 group users manual 8C45 8.4 clock asynchronous serial i/o (uart) mode 8.4.1 transfer rate (baud rate: transfer clock frequency) the transfer rate is determined by brgi (addresses 31 16 , 39 16 , and 65 16 ). when a value of n is set in brgi (n = 00 16 to ff 16 ), the count source is divided by (n + 1) in the brgi, and then the brgis output is further divided by 16. (in this way, the transfer clock is generated.) accordingly, assuming that the baud rate is b (bps), n is expressed by the following formula. n = C1 f : brgis count source frequency an internal clock or an external clock can be selected as the brgis count source by specifying the internal/external clock selection bit (bit 3 at addresses 30 16 , 38 16 , and 64 16 ). when an internal clock is selected, the clock selected by the brg count source selection bits (bits 1 and 0 at addresses 34 16 , 3c 16 , and 68 16 ) is the brgis count source. when an external clock is selected, the clock which is input to the clki pin is the brgis count source. tables 8.4.3 to 8.4.5 list examples of baud rate setting. be sure to set the same baud rate for both transmitter and receiver sides. f 16 5 b
serial i/o 7733 group users manual 8C46 8.4 clock asynchronous serial i/o (uart) mode table 8.4.3 example of baud rate setting (1) system clock: 19.6608 mhz system clock: 14.7456 mhz baud rate (bps) 300 600 1200 2400 4800 9600 19200 38400 57600 115200 brgis count source f 16 f 16 f 16 f 2 f 2 f 2 f 2 f 2 f 2 f 2 brgis set value: n 191 (bf 16 ) 95 (5f 16 ) 47 (2f 16 ) 191 (bf 16 ) 95 (5f 16 ) 47 (2f 16 ) 23 (17 16 ) 11 (0b 16 ) 7 (07 16 ) 3 (03 16 ) actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 57600.00 115200.00 brgis set value: n 255 (ff 16 ) 127 (7f 16 ) 63 (3f 16 ) 255 (ff 16 ) 127 (7f 16 ) 63 (3f 16 ) 31 (1f 16 ) 15 (f 16 ) actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 system clock, and clocks f 2 , f 16 : refer to chapter 14. clock generating circuit. note: this is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0. for details, refer to chapter 14. clock generating circuit. table 8.4.4 example of baud rate setting (2) system clock: 25 mhz system clock: 24.576 mhz baud rate (bps) 300 600 1200 2400 4800 9600 14400 19200 31250 brgis count source f 64 f 16 f 16 f 16 f 2 f 2 f 2 f 2 f 2 brgis set value: n 79 (4f 16 ) 159 (9f 16 ) 79 (4f 16 ) 39 (27 16 ) 159 (9f 16 ) 79 (4f 16 ) 52 (34 16 ) 39 (27 16 ) actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14490.57 19200.00 brgis set value: n 80 (50 16 ) 162 (a2 16 ) 80 (50 16 ) 40 (28 16 ) 162 (a2 16 ) 80 (50 16 ) 53 (35 16 ) 40 (28 16 ) 24 (18 16 ) actual time (bps) 301.41 599.12 1205.63 2381.86 4792.94 9645.06 14467.59 19054.88 31250.00 system clock, and clocks f 2 , f 16 , f 64 : refer to chapter 14. clock generating circuit. note: this is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0. for details, refer to chapter 14. clock generating circuit. table 8.4.5 example of baud rate setting (3) system clock: 12 mhz system clock: 11.0592 mhz baud rate (bps) 300 600 1200 2400 4800 9600 14400 19200 28800 31250 brgis count source f 16 f 16 f 16 f 2 f 2 f 2 f 2 f 2 f 2 f 2 brgis set value: n 143 (8f 16 ) 71 (47 16 ) 35 (23 16 ) 143 (8f 16 ) 71 (47 16 ) 35 (23 16 ) 24 (18 16 ) 17 (11 16 ) 12 (0c 16 ) actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14400.00 19200.00 28800.00 brgis set value: n 155 (9b 16 ) 77 (4d 16 ) 38 (26 16 ) 155 (9b 16 ) 77 (4d 16 ) 38 (26 16 ) 26 (1a 16 ) 13 (0d 16 ) 11 (0b 16 ) actual time (bps) 300.48 600.96 1201.92 2403.85 4807.69 9615.38 14423.08 28846.15 31250.00 system clock, and clocks f 2 , f 16 : refer to chapter 14. clock generating circuit. note: this is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0. for details, refer to chapter 14. clock generating circuit.
serial i/o 7733 group users manual 8C47 8.4 clock asynchronous serial i/o (uart) mode 8.4.2 transfer data format the transfer data format can be selected from three formats shown in figure 8.4.1. by setting bits 6 to 4 at addresses 30 16 , 38 16 and 64 16 , the transfer data format can be selected. (refer to figures 8.2.2 and 8.2.3. ) be sure to set the same transfer data format for both transmitter and receiver sides. figure 8.4.2 shows an example of transfer data format. table 8.4.6 lists each bit in transmit data. when transfer data has a length of 7 bits 1st-7data 1sp 1st-7data 2sp 1st-7data-1par- 1sp 1st-7data-1par- 2sp when transfer data has a length of 8 bits 1st-8data 1sp 1st-8data 2sp 1st-8data-1par- 1sp 1st-8data-1par- 2sp when transfer data has a length of 9 bits 1st-9data 1sp 1st-9data 2sp 1st-9data-1par- 1sp 1st-9data-1par- 2sp st : start bit data : character bit (transfer data) par : parity bit sp : stop bit fig. 8.4.1 transfer data format
serial i/o 7733 group users manual 8C48 8.4 clock asynchronous serial i/o (uart) mode data (8 bits) time next transmit/receive data (when transferring in succession) for the case where 1st-8data-1par-1sp ? st lsb msb par sp st transmit/receive data fig. 8.4.2 example of transfer data format table 8.4.6 each bit in transmit data name st start bit data character bit par parity bit sp stop bit functions l signal equivalent to 1 character bit which is added immediately before the character bits. it indicates start of data transmission. transmit data which is set in the uarti transmission buffer register. a signal which is added immediately after the character bits in order to improve data reliability. the level of this signal changes depending on odd/even parity selection in such a way that the sum of 1s in bits (this bit and character bits) is always an odd or even number. h level signal equivalent to 1 or 2 character bits which is added immediately after the character bits (or parity bit when parity is enabled). it indicates end of data transmission.
serial i/o 7733 group users manual 8C49 8.4 clock asynchronous serial i/o (uart) mode 8.4.3 method of transmission figure 8.4.3 shows an initial setting example for related registers when transmitting. the difference derived by selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data is transmitted in different lengths. when a 7/8-bit data length is selected, set the transmit data in the low- order byte of the uarti transmission buffer register; when a 9-bit data length is selected, set the transmit data in the low-order byte and bit 0 of the high-order byte. transmission is started when the following conditions ( to a ) are satisfied: transmit enable state (transmit enable bit = 1) transmit data is present in the uarti transmission buffer register (transmission buffer empty flag = 0) ____ ____ a the ctsi pins input is at l level (when the cts function is selected) ____ note : when the cts function is not selected or in uart2, this condition is ignored. ____ ____ by connecting the rtsi pin (receiver side) and ctsi pin (transmitter side), the timing of transmission and that of reception can be matched (uart0, uart1). for details, refer to section 8.4.6 receive operation. when using interrupts, settings for enabling interrupts are required. for details, refer to chapter 4. interrupts. figure 8.4.4 shows how to write data after transmission is started and figure 8.4.5 shows how to detect the transmit completion.
serial i/o 7733 group users manual 8C50 8.4 clock asynchronous serial i/o (uart) mode uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) uart2 baud rate register (brg2) (address 65 16 ) b7 b0 a value from 00 16 to ff 16 is set. interrupt priority level selection bits when using interrupts, one of level 1 to 7 must be set. when disabling interrupts, level 0 must be set. note 2: the cts/rts function selection bit is valid when the cts/rts enable bit = ?. uart0 transmission interrupt control register (address 71 16 ) uart1 transmission interrupt control register (address 73 16 ) a-d/uart2 transm./rece. interrupt control register (address 70 16 ) b7 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 b0 transmit enable bit 1: transmission is enabled. aaa aaa aaa transmission is started. (if the cts function is selected, transmission is started when the ctsi pin? input level is ?.? b0 uart0 transmission buffer register (addresses 33 16 , 32 16 ) uart1 transmission buffer register (addresses 3b 16 , 3a 16 ) uart2 transmission buffer register (addresses 67 16 , 66 16 ) b7 b0 transmit data is set here. b8 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) uart2 transmit/receive mode register (address 64 16 ) b7 b0 internal/external clock selection bit 0: internal clock 1: external clock 1 0 0: uart mode (7 bits) 1 0 1: uart mode (8 bits) 1 1 0: uart mode (9 bits) stop bit length selection bit 0: 1 stop bit 1: 2 stop bits odd/even parity selection bit 0: odd parity 1: even parity parity enable bit 0: parity is disabled. 1: parity is enabled. sleep selection bit ( note 1 ) 0: the sleep mode is terminated (ignored). 1: the sleep mode is selected. 1 b2b1b0 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source selection bits cts / rts enable bit 0: the cts / rts function is enabled. 1: the cts / rts function is disabled. cts / rts function selection bit 0: the cts function is selected. 1: the rts function is selected. (the cts function is disabled.) 0 0 data output selection bit 0: t x d i pin is set for cmos output. 1: t x d i pin is set for n-channel open-drain output. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter ?4. clock generating circuit. 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b1b0 (note 2) note 1: nothing is allocated to bit 7 of the uart2 transmit/ receive mode register. b7 b0 brg count source selection bits cts enable bit 0: the cts function is enabled. 1: the cts function is disabled ( i/o port ). 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b1b0 uart2 transmit/receive control register 0 (address 68 16 ) 0 fig. 8.4.3 initial setting example for related registers when transmitting
serial i/o 7733 group users manual 8C51 8.4 clock asynchronous serial i/o (uart) mode fig. 8.4.4 how to write data after transmission is started [when not using interrupts] [when using interrupts] a uarti transmission interrupt request occurs when the uarti transmission buffer register becomes empty. uarti transmission interrupt uart0 transmission buffer register (addresses 33 16 , 32 16 ) uart1 transmission buffer register (addresses 3b 16 , 3a 16 ) uart2 transmission buffer register (addresses 67 16 , 66 16 ) b15 b8 writing of the next transmit data transmit data is set here. b7 b0 h this diagram indicates bits and registers required for processing. refer to figures 8.4.6 , 8.4.7 and 8.4.8 for details about the change of flag status and the occurrence timing of an interrupt request. uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 b0 transmission buffer empty flag 0: data is present in the transmission buffer register. 1: no data is present in the transmission buffer register. (next transmit data can be written.) checking the status of the uarti transmission buffer register 1
serial i/o 7733 group users manual 8C52 fig. 8.4.5 how to detect transmit completion 8.4 clock asynchronous serial i/o (uart) mode [when not using interrupts] [when using interrupts] uarti transmission interrupt request occurs when transmission is started. uarti transmission interrupt h this diagram indicates bits and registers required for processing. refer to figures 8.4.6 , 8.4.7 and 8.4.8 for details about the change of flag status and the occurrence timing of an interrupt request. uart0 transmission interrupt control register (address 71 16 ) uart1 transmission interrupt control register (address 73 16 ) a-d/uart2 trans./rece. interrupt control register (address 70 16 ) b7 b0 interrupt request bit 0: no interrupt has occurred. 1: interrupt has occurred. (transmission has been started.) checking the start of transmission processing at transmit completion uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) uart2 transmit/receive control register 0 (address 68 16 ) b7 b0 checking the completion of transmission 00 transmisson register empty flag 0: transmission is in progress. 1: transmission is completed. note: nothing is implemented to bits 7 to 4 of uart2.
serial i/o 7733 group users manual 8C53 8.4.4 transmit operation when the transmit conditions described in section 8.4.3 method of transmission are satisfied, the transfer clock is generated and the following operations are automatically performed after one cycle of the transfer clock has passed. l the uarti transmission buffer registers contents is transferred to the uarti transmission register. l the transmission buffer empty flag is set to 1. l the transmission register empty flag is cleared to 0. l a uarti transmission interrupt request occurs and the interrupt request bit is set to 1. the transmit operation is described below. data in the uarti transmission register is transmitted from the t x di pin. this data is transmitted bit by bit sequentially in order of st ? data (lsb) ? ??? ? data (msb) ? par ? sp according to the transfer data format. a in the middle of the stop bit (the second stop bit when two stop bits are selected), the transmission register empty flag is set to 1. this indicates completion of transmission. also, whether the transmit conditions for the next data are satisfied or not is checked. when the transmit conditions for the next data are satisfied at completion of transmission in operation a , a start bit is generated following the stop bit and the next data is transmitted. when performing transmission in succession, set the next transmit data in the uarti transmission buffer register during transmission (when transmission register empty flag = 0). when the transmit conditions for the next data are not satisfied, the txdi pin outputs h level and the transfer clock is stopped. figure 8.4.6 shows an example of transmit timing when the transfer data length has a 8 bits. figure 8.4.7 shows an example of transmit timing when the transfer data length has a 9 bits. 8.4 clock asynchronous serial i/o (uart) mode
7733 group users manual 8C54 8.4 clock asynchronous serial i/o (uart) mode fig. 8.4.7 example of transmit timing when data is transferr ed in 9 bits (when parity is disabled and two stop bits) fig. 8.4.6 example of transmit timing when data is transferr ed in 8 bits (when parity is enabled, one ____ stop bit, and cts function is not selected) st d 0 t endi txd i d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 1 d 8 sp sp sp 0 1 0 1 0 1 tc 0 1 transmit enable bit transmission buffer empty flag transmission register empty flag start bit data is set in uarti transmission buffer register. transfer clock t endi : next transmit conditions are checked when this signal lev el becomes h. (t endi is an internal signal. accordingly, it cannot be read from the external.) the above timing diagram is applied when the following conditions are satisfied: l parity is disabled. l 2 stop bits l cts function is not selected. t c = 16(n + 1)/f i or 16(n + 1)/f ext f i : brg i s count source frequency (f 2 , f 16 , f 64 , or f 512 ) f ext : brg i s count source frequency (external clock) n : value set to brg i stopped because transmit enable bit = 0 uarti transmission interrupt request bit cleared to 0 when an interrupt request is accepted; otherw ise, cleared by software. stop bit stop bit uarti transmission register uarti transmission buffer register tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp st t endi txd i 0 1 0 1 0 1 0 1 transmit enable bit transmission buffer empty flag transmission register empty flag start bit stop bit data is set in uarti transmission buffer register. transfer clock the above timing diagram is applied when the following conditions are satisfied: l parity is enabled. l 1 stop bit l cts function is not selected. t c = 16(n + 1)/f i or 16(n + 1)/f ext f i : brg i s count source frequency (f 2 , f 16 , f 64 , or f 512 ) f ext : brg i s count source frequency (external clock) n : value set to brg i stopped because transmit enable bit = 0 uarti transmission interrupt request bit cleared to 0 when an interrupt request is accepted; otherw ise, cleared by software. parity bit t endi : next transmit conditions are checked when this signal lev el becomes h. (t endi is an internal signal. accordingly, it cannot be read from the external.) uarti transmission register uarti transmission buffer register seiral i/o
serial i/o 7733 group users manual 8C55 8.4 clock asynchronous serial i/o (uart) mode fig. 8.4.8 example of transmit timing when data is transferred in 8 bits (when parity is enabled, one ____ stop bit, and cts function is selected) tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st psp d 0 d 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp st t endi txd i ? ? ? ? ? ? ? ? ? ? cts i stopped because cts pin? level is ?. transmit enable bit transmission buffer empty flag transmission register empty flag start bit stop bit data is set in uarti transmission buffer register. transfer clock the above timing diagram is applied when the following conditions are satisfied: l parity is enabled. l 1 stop bit l cts function is selected. t c = 16(n + 1)/f i or 16(n + 1)/f ext f i : brg i ? count source frequency (f 2 , f 16 , f 64 , or f 512 ) f ext : brg i ? count source frequency (external clock) n : value set to brg i ? uarti transmission buffer register stopped because transmit enable bit = ? uarti transmission interrupt request bit cleared to ??when an interrupt request is accepted; otherwise, cleared by software. parity bit t endi : next transmit conditions are checked when this signal level becomes ?. (t endi is an internal signal. accordingly, it cannot be read from the external.) uarti transmission register
serial i/o 7733 group users manual 8C56 8.4 clock asynchronous serial i/o (uart) mode 8.4.5 method of reception figure 8.4.9 shows an initial setting example for related registers when receiving. reception is started when the following conditions ( and ) are satisfied. receive enable state (receive enable bit = 1). the start bit is detected. ____ ____ by connecting the rtsi pin (receiver side) and ctsi pin (transmitter side), the timing of transmission and that of reception can be matched (uart0, uart1). for details, refer to section 8.4.6 receive operation. when using interrupts, settings for enabling interrupts are required. for details, refer to chapter 4. interrupts. figure 8.4.10 shows the processing after reception is completed.
serial i/o 7733 group users manual 8C57 8.4 clock asynchronous serial i/o (uart) mode then, reception starts when the start bit is detected. port p8 direction register (address 14 16 ) b7 b0 0 0 r x d 0 pin r x d 1 pin uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) uart2 baud rate register (brg2) (address 65 16 ) b7 b0 a value from 00 16 to ff 16 is set. uart0 receive interrupt control register (address 72 16 ) uart1 receive interrupt control register (address 74 16 ) a-d/uart2 trans./rece. interrupt control register (address 70 16 ) b7 b0 interrupt priority level selection bits when using interrupts, one of level 1 to 7 must be set. when disabling interrupts, level 0 must be set. note 2: the cts/rts function selection bit is valid when cts/rts enable bit = ?. h set the transfer data format in the same way as set on the transmitter side. note 1: nothing is allocated to bit 7 of uart2 transmit/receive mode register. 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 b0 receive enable bit 1: reception is enabled. uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) uart2 transmit/receive mode register (address 64 16 ) b7 b0 internal/external clock selection bit 0: internal clock 1: external clock 1 0 0: uart mode (7 bits) 1 0 1: uart mode (8 bits) 1 1 0: uart mode (9 bits) stop bit length selection bit 0: 1 stop bit 1: 2 stop bits odd/even parity selection bit 0: odd parity 1: even parity parity enable bit 0: parity is disabled. 1: parity is enabled. sleep selection bit ( note 1 ) 0: the sleep mode is terminated (ignored) . 1: the sleep mode is selected. 1 b2b1b0 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source selection bits cts / rts enable bit 0: the cts / rts function is enabled. 1: the cts / rts function is disabled. cts / rts function selection bit (note 2) 0: the cts function is selected. (the rts function is disabled.) 1: the rts function is selected. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter ?4. clock generating circuit. 00 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b1b0 b7 b0 brg count source selection bits cts enable bit 0: the cts function is enabled. 1: the cts function is disabled ( i/o port ) . 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b1b0 port p7 direction register (address 11 16 ) b7 b0 0 r x d 2 pin ( note 3 ) note 3: in the 7733 group or the 7735 group, set this bit. in the 7736 group, it is not neccessary to set this bit. 0 uart2 transmit/receive control register 0 (address 68 16 ) fig. 8.4.9 initial setting example for related registers when receiving
serial i/o 7733 group users manual 8C58 8.4 clock asynchronous serial i/o (uart) mode [when not using interrupts] [when using interrupts] a uarti receive interrupt request occurs when reception is completed. uarti receive interrupt h this diagram indicates bits and registers required for processing. refer to figure 8.4.12 for details about the change of flag status and the occurrence timing of an interrupt request. processing after reading out receive data uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) uart2 receive buffer register (addresses 6b 16 , 6a 16 ) b15 b8 reading out the receive data read out the receive data b7 b0 0 0 0 0 0 0 0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 b0 receive completion flag 0: reception is not completed. 1: reception is completed. checking the completion of reception 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 b0 checking the error framing error flag parity error flag error sum flag 0: no error is detected. 1: error is detected. 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) b7 b0 checking the error overrun error flag 0: no error is detected. 1: error is detected. 1 fig. 8.4.10 processing after reception is completed
serial i/o 7733 group users manual 8C59 8.4 clock asynchronous serial i/o (uart) mode txd i rxd i cts i txd i rxd i rts i ( note ) transmitter side receiver side note: the rtsi output function is not assigned for 8.4.6 receive operation when the receive enable bit is set to 1, the uarti enters the receive enable state. and then, the transfer clock is generated when st is detected, and reception is started. ____ ____ when the rts function is selected (uart0, uart1), the rtsi pins output level becomes l if the uarti enters the receive enable state and the microcomputer informs the transmitter side that reception is ____ enabled. when reception is started, the rtsi pins output level becomes h. accordingly, by connecting ____ ____ the rtsi pin (receiver side) and the ctsi pin (transmitter side), the timing of transmission and that of reception can be matched. figure 8.4.11 shows an connection example. the receive operation is described below. the signal which is input from the rxdi pin is taken in the most significant bit of the uarti receive register synchronously with the transfer clocks rising edge. the contents of uarti receive register is shifted by 1 bit to the right. a operations and are repeated at each transfer clocks rising edge. ? when a set of data is prepared, in other words, when shifted several times depending on the specified data format, the uarti receive registers contents is transferred to the uarti receive buffer register. ? simultaneously with ? , the receive completion flag is set to 1. furthermore, a uarti receive interrupt request occurs and the interrupt request bit is set to 1. the receive completion flag is cleared to 0 when the low-order of the uarti receive buffer register is read ____ ____ out. the rtsi pins output level becomes l simultaneously with ? (when rts function is selected). figure 8.4.12 shows an example of receive timing when transfer data has a length of 8 bits. fig. 8.4.11 connection example
serial i/o 7733 group users manual 8C60 8.4 clock asynchronous serial i/o (uart) mode fig. 8.4.12 example of receive timing when data is transferred in 8 bits (when parity is disabled and one stop bit) d0 d1 d7 rxd i ( note ) rts i ? ? ? ? ? ? ? ? receive enable bit start bit stop bit the above timing diagram is applied when the following conditions are satisfied: l parity is disabled. l 1 stop bit l rts function is selected. ? uarti receive buffer register uarti receive interrupt request bit cleared to ??when an interrupt request is accepted; otherwise, cleared by software. receive completion flag check whether the level is ?. received data is taken in. the transfer clock is generated at the falling edge of start bit, and reception is started. brg i count source note: the rtsi output function is not assigned for transfer clock uarti receive register
serial i/o 7733 group users manual 8C61 8.4 clock asynchronous serial i/o (uart) mode 8.4.7 processing when error is detected errors listed below can be detected in the uart mode: l overrun error an overrun error occurs when the next data is prepared in the uarti receive register with the receive completion flag = 1 (in other words, data is present in the uarti receive buffer register), and then the next data is transferred to the uarti receive buffer register. in other words, when the next data is prepared before the contents of the uarti receive buffer register is read out. when an overrun error occurs, the next receive data is written into the uarti receive buffer register. at this time, the uarti receive interrupt request bit is not set to 1. l framing error a framing error occurs when the number of detected stop bits does not match the number which is set. (the uarti interrupt request bit is set to 1.) l parity error a parity error occurs when the sum of 1s in the parity bit and character bits does not match the number which is set. (the uarti interrupt request bit is set to 1.) each error is detected when data is transferred from the uarti receive register to the uarti receive buffer register, and the corresponding error flag is set to 1. furthermore, when any of the above errors occurs, the error sum flag is set to 1. accordingly, the error sum flag informs whether any error has occurred or not. error flags are cleared to 0 when the serial i/o mode selection bits are cleared to 000 2 or when the receive enable bit is cleared to 0. (when all of the overrun, framing, and parity error flags are cleared to 0, the error sum flag is cleared to 0.) note also that the framing and parity error flags are cleared to 0 when the low-order byte of the uarti receive buffer register is read out. when an error occurs during reception, initialize the error flags and the uarti receive buffer register, and then perform reception again. when it is necessary to perform transmission again owing to an error which occurs in the receiver side, set the uarti transmission buffer register again, and then starts transmission again. the method of initializing the uarti receive buffer register and that of setting the uarti transmission buffer register again are described below. (1) method of initializing uarti receive buffer register clear the receive enable bit to 0. (reception is disabled.) set the receive enable bit to 1 again. (reception is enabled.) (2) method of setting uarti transmission buffer register again clear the serial i/o mode selection bits to 000 2 . (serial i/o is ignored.) set the serial i/o mode selection bits again. a set the transmit enable bit to 1. (transmission is enabled.) and set the transmit data to the uarti transmission buffer register. 8.4.8 precautions for uart for performing the transmission and the reception simultaneously, uart2 does not distinguish the transmission interrupt from the reception interrupt. the uart2 transmission/reception interrupt request occurs when either interrupt request occurs. accordingly, in the system which performs the transmission and reception simultaneously for uart2, not use the uart2 transmission/reception interrupt but use the method of poling the transmission buffer empty flag and the receive completion flag by software.
serial i/o 7733 group users manual 8C62 8.4 clock asynchronous serial i/o (uart) mode master slave b slave a slave d slave c data is transferred between the master microcomputer and one specific slave microcomputer, which is selected from multiple slave microcomputers. 8.4.9 sleep mode (uart0 and uart1) this mode is used when data is transferred between the master microcomputer and one slave microcomputer, which is selected from multiple slave microcomputers connected to the master microcomputer using uarti. the sleep mode is selected when the sleep selection bit (bit 7 at addresses 30 16 and 38 16 ) is set to 1 at receiving. in the sleep mode, the receive operation is performed when the msb (d 8 when the transfer data has a length of 9 bits; d 7 when the transfer data has a length of 8 bits; d 6 when the transfer data has a length of 7 bits) of the receive data = 1. the receive operation is not performed when the msb = 0. (the uarti receive registers contents is not transferred to the uarti receive buffer register. the receive completion flag and error flags do not change and a uarti receive interrupt request does not occur, also.) a usage example of the sleep mode when the transfer data has a length of 8 bits is described below. set the same transfer data format for the master and slave microcomputers. select the sleep mode for the slave microcomputer. transmit the data, which has 1 in bit 7 and the address of the slave microcomputer to be communicated in bits 6 to 0, from the master microcomputer to all slave microcomputers. a all slave microcomputers receive data in operation . (at this time, a uarti receive interrupt request occurs.) ? for all slave microcomputers, check in the interrupt routine whether bits 6 to 0 in the receive data match their own addresses. ? for the slave microcomputer whose address matches bits 6 to 0 in the receive data, terminate the sleep mode. (do not terminate the sleep mode for the other slave microcomputers.) by performing operations to ? , the slave microcomputer which performs transmission can be specified. ? transmit the data, which has 0 in bit 7, from the master microcomputer. (only the microcomputer selected by operations to ? receives this data. the other microcomputers do not receive this data.) ? by repeating operation ? , data is transferred between two specific microcomputers in succession. also, by performing operations to ? , another slave microcomputer can be specified. fig. 8.4.13 sleep mode
chapter 9 chapter 9 a-d converter 9.1 overview 9.2 block description 9.3 a-d conversion method 9.4 absolute accuracy and differential non-linearity error 9.5 one-shot mode 9.6 repeat mode 9.7 single sweep mode 9.8 repeat sweep mode 9.9 precautions for a-d converter
a-d converter 7733 group users manual 9C2 the a-d converter is described below. for this a-d converter, 8-bit resolution or 10-bit resolution can be selected. its conversion method is the successive approximation method and has 8 analog input pins. 9.1 overview the performance overview is listed in table 9.1.1. table 9.1.1 performance overview 9.1 overview item a-d conversion method resolution absolute accuracy analog input pin conversion rate per analog input pin performance successive approximation method 8/10 bits can be selected by software 8-bit resolution: 2 lsb 10-bit resolution: 3 lsb 8 pins (an 0 to an 7 ) 8-bit resolution: 49 f ad ] cycles 10-bit resolution: 59 f ad ] cycles f ad ] : a-d converters operating clock the a-d convertor has the following four operation modes. n one-shot mode a-d conversion is once performed for the input voltage of one analog input pin. n repeat mode a-d conversion is repeatedly performed for the input voltage of one analog input pin. n single sweep mode a-d conversion is performed for the input voltage of multiple analog input pins, one at a time. n repeat sweep mode a-d conversion is repeatedly performed for the input voltage of multiple analog input pins.
a-d converter 7733 group users manual 9C3 comparator successive approximation register av ss v ref resistor ladder network v ref selector an 0 an 1 an 2 an 3 an 4 an 5 /ad trg an 6 an 7 a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7 a-d control register 1 decoder v in 1/2 f 2 1/2 ? ad data bus (even) a-d control register 0 data bus (odd) a-d conversion frequency selection v ref connection selection 9.2 block description figure 9.2.1 shows the block diagram of the a-d converter. registers related to the a-d converter are described below. fig. 9.2.1 block diagram of a-d converter 9.2 block description
a-d converter 7733 group users manual 9C4 b7 b6 b5 b4 b3 b2 b1 b0 @ a-d control register 0 (address 1e 16 ) bit a-d conversion frequency ( ad ) selection flag a-d conversion start flag trigger selection bit 4 @ a-d operation mode selection bits 2 @ 1 @ 0 bit name at reset 0 0 0 0 0 undefined undefined undefined rw functions 0 0 0: an 0 is stopped. 0 0 1: an 1 is stopped. 0 1 0: an 2 is stopped. 0 1 1: an 3 is stopped. 1 0 0: an 4 is stopped. 1 0 1: an 5 is stopped. (note 2) 1 1 0: an 6 is stopped. 1 1 1: an 7 is stopped. f 2 ] : refer to chapter ?4. clock generating circuit. b2 b1 b0 0: internal trigger 1: external trigger 0: f 2 /4 ] 1: f 2 /2 00: one-shot mode 01: repeat mode 10: single sweep mode 11: repeat sweep mode 0: a-d conversion is stopped. 1: a-d conversion is started. b4b3 these bits are ignored in the single sweep and repeat sweep modes. (they may be ?? or ?.? when an external trigger is selected, pin an 5 cannot be used as an analog input pin. writing to each bit (except bit 6) of the a-d control register 0 must be performed while the a-d converter stops operating. analog input selection bits (valid in the one-shot and repeat modes) (note 1) notes 1: 2: 3: 3 7 6 5 rw rw rw rw rw rw rw rw 9.2.1 a-d control register 0 figure 9.2.2 shows the structure of a-d control register 0. a-d operation mode selection bits select an operation mode of a-d converter. the other bits are described below. 9.2 block description fig. 9.2.2 structure of a-d control register 0 (1) analog input selection bits (bits 2 to 0) these bits are used to select an analog input pin in the one-shot and repeat modes. (refer to section 9.2.5 port p7 direction register. ) when switching the operating mode to the one-shot or repeat mode after a-d conversion is once performed in the single sweep or repeat sweep mode, set these bits again.
a-d converter 7733 group users manual 9C5 0 f 2 divided by 4 15.68 18.88 a-d conversion frequency ( f ad ) selection flag f ad conversion time resolution : 8 bits ?system clock = 25 mhz (note) resolution : 10 bits 1 f 2 divided by 2 7.84 9.44 (2) trigger selection bit (bit 5) this bit selects a trigger occurrence source. (refer to (3) a-d conversion start flag. ) (3) a-d conversion start flag (bit 6) ?? when internal trigger is selected when this bit is set to 1, a trigger occurs, and then the a-d converter starts operating. when this bit is cleared to 0, the a-d converter stops operating. in the one-shot or single sweep mode, this bit is cleared to 0 after a-d conversion is completed. in the repeat or repeat sweep mode, the a-d converter continues operating until this bit is cleared to 0 by software. ?? when external trigger is selected ______ if the ad trg pin level goes from h to l when this bit = 1, a trigger occurs, and then the a-d converter starts operating. the a-d converter stops operating when this bit is cleared to 0. in the one-shot or single sweep mode, this bit remains set to 1 even after a-d conversion is completed. in the repeat or repeat sweep mode, the a-d converter continues operating until this bit is cleared to 0 by software. (4) a-d conversion frequency ( f ad ) selection flag (bit 7) conversion time varies according to the a-d converters operating clock ( f ad ) selected by this bit as listed in table 9.2.1. since the a-d converters comparator consists of capacity coupling amplifiers, keep that f ad 3 250 khz during a-d conversion. note: this is applied when the following conditions are satisfied; ?f(x in ) = 25 mhz ?the main clock is selected as the system clock. ?main clock divided by 2 is available. table 9.2.1 conversion time per one analog input pin (unit: m s) 9.2 block description
a-d converter 7733 group users manual 9C6 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (address 1f 16 ) bit 1 0 bit name at reset 1 rw functions 0 0: pins an 0 and an 1 (2 pins) 0 1: pins an 0 to an 3 (4 pins) 1 0: pins an 0 to an 5 (6 pins) (note 2) 1 1: pins an 0 to an 7 (8 pins) b1 b0 not implemented. undefined 1 these bits are ignored in the one-shot and repeat modes. (t hey may be 0 or 1.) when an external trigger is selected, pin an 5 cannot be used as an analog input pin. writing to each bit of the a-d control register 1 must be pe rformed while the a-d converter stops operating. when the v ref connection selection bit is cleared from 1 to 0, wait f or an interval of 1 s or more passed, and then start a-d conversion. 2 3 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution a-d sweep pin selection bits (valid in the single sweep and repeat sweep modes.) (note 1) 0 4 must be fixed to 0. 5 v ref connection selection bit (note 4) 0: pin v ref is connected. 1: pin v ref is disconnected. (high impedance) 7 6 not implemented. 0 0 undefined rw rw rw rw rw _ 0 notes 1: 2: 3: 4: 9.2.2 a-d control register 1 figure 9.2.3 shows the structure of a-d control register 1. 9.2 block description fig. 9.2.3 structure of a-d control register 1 (1) a-d sweep pin selection bits (bits 1 and 0) these bits are used to select analog input pins in the singl e sweep and repeat sweep modes. refer to section 9.2.5 port p7 direction register. (2) v ref connection selection bit (bit 5) this bit is used to disconnect the a-d converters resistor ladder network from the reference voltage input pin (v ref ) when not using the a-d converter. when pin v ref is disconnected from the resistor ladder network, no curren t flows from pin v ref to the resistor ladder network. _
a-d converter 7733 group users manual 9C7 b7 b0 a-d register 0 (addresses 21 16 and 20 16 ) a-d register 1 (addresses 23 16 and 22 16 ) a-d register 2 (addresses 25 16 and 24 16 ) a-d register 3 (addresses 27 16 and 26 16 ) a-d register 4 (addresses 29 16 and 28 16 ) a-d register 5 (addresses 2b 16 and 2a 16 ) a-d register 6 (addresses 2d 16 and 2c 16 ) a-d register 7 (addresses 2f 16 and 2e 16 ) bit ??at reading. the a-d conversion result is read out. functions at reset 0 undefined ro ro rw b7 b0 (b15) (b8) l when resolution = 10 bits 15 to 10 9 to 0 b7 b0 a-d register 0 (addresses 21 16 and 20 16 ) a-d register 1 (addresses 23 16 and 22 16 ) a-d register 2 (addresses 25 16 and 24 16 ) a-d register 3 (addresses 27 16 and 26 16 ) a-d register 4 (addresses 29 16 and 28 16 ) a-d register 5 (addresses 2b 16 and 2a 16 ) a-d register 6 (addresses 2d 16 and 2c 16 ) a-d register 7 (addresses 2f 16 and 2e 16 ) bit ??at reading. the a-d conversion result is read out. functions at reset 0 undefined ro rw b7 b0 (b15) (b8) l when resolution = 8 bits 7 to 0 15 to 8 ro 9.2.3 a-d register i (i = 0 to 7) figure 9.2.4 shows the structure of a-d register i. when a-d conversion is completed, the conversion result (in other words, the contents of the successive approximation register) is stored into this register. each a- d register i corresponds to an analog input pin (an i ), one for one. table 9.2.2 lists the correspondence of an analog input pin to a-d register i. 9.2 block description fig. 9.2.4 structure of a-d register i table 9.2.2 correspondence of analog input pin and a-d register i analog input pin pin an 0 pin an 1 pin an 2 pin an 3 pin an 4 pin an 5 pin an 6 pin an 7 a-d register i where conversion result is stored a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7
a-d converter 7733 group users manual 9C8 bit 7 to 4 not implemented. 3 interrupt request bit (note) 2 1 0 interrupt priority level selection bits bit name at reset undefined 0 0 0 0 rw functions 0 0 0: level 0 (interrupt is disabled.) 0 0 1: level 1 priority is low. 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 priority is high. b2 b1 b0 0: no interrupt request has occurred. 1: interrupt request has occurred. b7 b6 b5 b4 b3 b2 b1 b0 a-d/uart2 trans./rece. interrupt control register (address 70 16 ) note: when uart2 is selected, in other words, when a serial i/o m ode is selected by specifying the serial i/o mode selection bits (bits 0 to 2 a t address 64 16 ), this bit is set to 1. rw rw rw rw 9.2.4 a-d/uart2 trans./rece. interrupt control register figure. 9.2.5 shows the structure of the a-d/uart2 trans./re ce. control register. the a-d conversion interrupt and uart2 transmission/receptio n interrupt share the same interrupt control register and interrupt vector addresses. when uart2 is selected, the a-d/uart2 trans./rece. interrupt control register functions as an register which control the uart2 transmission/reception interrupt. at this time, the a-d conversion interrupt cannot be used. for details on interrupts, refer to chapter 4. interrupts. for details on uart2, refer to chapter 8. serial i/o. the case where this register is used as the a-d conversion interrupt contr ol register is described below. fig. 9.2.5 structure of a-d/uart2 trans./rece. interrupt con trol register 9.2 block description C
a-d converter 7733 group users manual 9C9 (1) interrupt priority level selection bits (bits 2 to 0) these bits select an a-d conversion interrupts priority level. when using a-d conversion interrupts, select one priority level from levels 1 to 7. if an a-d conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl), and the requested interrupt is enabled only when its priority level is higher than the ipl. (note that this is applied to the case where the interrupt disable flag (i) = 0.) when disabling a-d conversion interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when an a-d conversion interrupt request occurs. this bit is automatically cleared to 0 when the a-d conversion interrupt request is accepted. note that this bit can be set to 1 or cleared to 0 by software. 9.2 block description
a-d converter 7733 group users manual 9C10 bit corresponding bit? name functions 0 1 2 3 4 5 6 pin an 0 pin an 2 /cts 2 pin an 3 /clk 2 pin an 4 /rxd 2 pin an 6 /x cout 0: input mode 1: output mode pin an 5 /ad trg /txd 2 port p7 direction register (address 11 16 ) b1 b0 b2 b3 b4 b5 b6 b7 pin an 1 at reset rw 0 0 0 0 0 0 0 when using these pins as a-d converter? input pins, set the corresponding bits to ?. 7 pin an 7 /x cin 0 rw rw rw rw rw rw rw rw 9.2.5 port p7 direction register input pins of the a-d converter are multiplexed with port p7. when using these pins as a-d converters input pins, set the corresponding bits of the port p7 direction register to 0 to set these ports for the input mode. figure 9.2.6 shows the relationship between the port p7 direction register and i/o pins of the sub- clock oscillation circuit and peripheral functions. fig. 9.2.6 relationship between port p7 direction register and i/o pins of sub-clock oscillation circuit and peripheral functions analog input pins function as the port p7s i/o pins and also function as i/o pins of the sub-clock oscillation circuit and uart2. for pins which are forcedly set to the output mode when the function for the sub-clock oscillation circuit or uart2 is selected, analog input is disabled. (refer to table 9.2.3. ) table 9.2.3 port p7s pin which is forcedly set to output mode 9.2 block description pin p7 3 /an 3 /clk 2 _____ p7 5 /an 5 / ad trg /txd 2 p7 6 /an 6 /x cout clock synchronous serial i/o mode is selected and an internal clock is used. (bits 3 to 0 at address 64 16 = 0001 2 ) serial i/o mode is selected. (bits 2 to 0 at address 64 16 = 001 2 , 100 2 , 101 2 , or 110 2 ) sub-clock oscillation circuit is operating by itself. (bit 4 at address 6c 16 = 1 and bit 2 at address 6f 16 = 0 ) conditions where pin is forcedly set to output mode
a-d converter 7733 group users manual 9C11 9.3 a-d conversion method the a-d converter compares the comparison voltage (v ref ), which is internally generated according to the contents of the successive approximation register, and the analog input voltage (v in ), which is input from the analog input pin. by reflecting the comparison result on the successive approximation register, v in is converted into a digital value (successive approximation method). when a trigger occurs, the a-d converter performs the following processing: determination of successive approximation registers bit 9 the a-d converter compares v ref and v in . at this time, contents of the successive approximation register is 1000000000 2 (initial value). bit 9 of the successive approximation register changes according to the comparison result as follows: if v ref < v in , bit 9 = 1 if v ref > v in , bit 9 = 0 determination of successive approximation registers bit 8 after setting bit 8 of the successive approximation register to 1, the a-d converter compares v ref and v in . bit 8 changes according to the comparison result as follows: if v ref < v in , bit 8 = 1 if v ref > v in , bit 8 = 0 a determination of successive approximation registers bits 7 to lsb when resolution = 8 bits ........... for bits 7 to 2, perform operation . when resolution = 10 bits ......... for bits 7 to 0, perform operation . when the lsb is determined, the contents of the successive approximation register, in other words, the conversion result is transferred to the a-d register i. v ref is generated according to the latest contents of the successive approximation register. table 9.3.1 lists the relationship between the successive approximation registers contents and v ref . tables 9.3.2 and 9.3.3 list changes of the successive approximation register and v ref during a-d conversion. figure 9.3.1 shows theoretical a-d conversion characteristics when resolution = 10 bits. table 9.3.1 relationship between successive approximation registers contents and vref 9.3 a-d conversion method 1 to 1023 (n C 0.5) v ref ] : reference voltage v ref ] 1024 successive approximation registers contents: n 0 v ref (v) 0
a-d converter 7733 group users manual 9C12 1 1 n 9 0 00000000 0 00000000 1 00000000 n 9 n 8 1 0000000 n 9 n 8 n 7 n 6 n 5 n 4 n 3 1 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 b9 b0 1st comparison result 2nd comparison result successive approximation register v ref a-d converter stopped 1st comparison 2nd comparison 3rd comparison 10th comparison conversion complete 2 v ref 2048 v ref 2 v ref 4 v ref 2048 v ref 2 v ref 4 v ref 8 v ref 2048 v ref 2 v ref 4 v ref 8 v ref v ref 1024 2048 v ref [v] [v] [v] [v] [v] 4 v ref ?when n 9 = 1, 4 v ref ?when n 9 = 0, 8 v ref ?when n 8 = 1, 8 v ref ?when n 8 = 0, 2 v ref C C C C n 2 n 1 n 1 n 0 + C + C 1 1 n 9 0 00000000 0 00000000 1 00000000 n 9 n 8 1 0000000 n 9 n 8 n 7 n 6 n 5 n 4 n 3 1 00 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 00 b9 b0 1st comparison result 2nd comparison result successive approximation register v ref a-d converter stopped 1st comparison 2nd comparison 3rd comparison 8th comparison conversion complete 2 v ref 2048 v ref 2 v ref 4 v ref 2048 v ref 2 v ref 4 v ref 8 v ref 2048 v ref 2 v ref 4 v ref 8 v ref v ref 256 2048 v ref [v] [v] [v] [v] [v] 4 v ref ?when n 9 = 1, 4 v ref ?when n 9 = 0, 8 v ref ?when n 8 = 1, 8 v ref ?when n 8 = 0, 2 v ref C C C C + C + C table 9.3.2 change of successive approximation register and vref during a-d conversion (when resolution = 8 bits) 9.3 a-d conversion method table 9.3.3 change of successive approximation register and vref during a-d conversion (when resolution = 10 bits)
a-d converter 7733 group users manual 9C13 000 16 001 16 002 16 003 16 3fe 16 3ff 16 analog input voltage v ref 1024 5 1 v ref 1024 5 2 v ref 1024 5 3 5 1021 v ref 1024 v ref 1024 5 1022 v ref 1024 5 1023 v ref v ref 1024 5 0.5 theoretical a-d conversion characteristics 0 a-d conversion result 3fd 16 9.3 a-d conversion method fig. 9.3.1 theoretical a-d conversion characteristics when r esolution = 10 bits
a-d converter 7733 group users manual 9C14 000 16 001 16 002 16 003 16 004 16 005 16 006 16 0 5 10152025303540455055 007 16 008 16 009 16 00a 16 00b 16 +3 lsb ? lsb ideal a-d conversion characteristics analog input voltage (mv) output code (a-d conversion result) fig. 9.4.1 absolute accuracy of a-d converter (when resolution = 10 bits) 9.4 absolute accuracy and differential non-linearity error the a-d conversions accuracy is described below. 9.4.1 absolute accuracy the absolute accuracy is the difference expressed in the lsb between the actual a-d conversion result and the output code of an a-d converter with ideal characteristics. the analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an a-d converter with ideal characteristics. for example, in the case of the 10-bit resolution, when v ref = 5.12 v, 1-lsb width is 5 mv, and 0 mv, 5 mv, 10 mv, 15 mv, 20 mv, ... are selected as the analog input voltages. the absolute accuracy = 3 lsb when the analog input voltage = 25 mv indicates that the output code expected from an ideal a-d conversion characteristics is 005 16 but the actual a-d conversion result is between 002 16 to 008 16 . the absolute accuracy includes the zero error and the full-scale error. the absolute accuracy degrades when v ref is lowered. the output codes for analog input voltages between v ref and av cc are 3ff 16 . 9.4 absolute accuracy and differential non-linearity error
a-d converter 7733 group users manual 9C15 000 16 001 16 002 16 003 16 004 16 005 16 006 16 0 5 1015202530354045 007 16 008 16 009 16 output code (a-d conversion result) differential non-linearity error analog input voltage (mv) 1 - lsb width with a-d conversion characteristics 9.4.2 differential non-linearity error the differential non-linearity error indicates the difference between the 1-lsb step width (the ideal analog input voltage width while the same output code is expected to output) of an a-d converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). for example, in the case of the 10-bit mode, when v ref = 5.12 v, the 1-lsb width of an a-d converter with ideal characteristics is 5 mv, but if the differential non-linearity error is 1 lsb, the actual measured 1-lsb width is 0 to 10 mv. (refer to section 16.1.4 a-d converter standard characteristics. ) 9.4 absolute accuracy and differential non-linearity error fig. 9.4.2 differential non-linearity error (when resolution = 10 bits)
a-d converter 7733 group users manual 9C16 07 05 06 03 00 02 analog input voltage (mv) 02 01 00 04 02 01 00 01 08 09 10 30 17.5 37.5 l 8-bit a-d converter (when v ref = 5.12 v) output code (a-d conversion result) l m37733mhbxxxfp? a-d converter with ideal characteristics (when v ref = 5.12 v) output code (a-d conversion result) 8-bit resolution 10-bit resolution ( h ) analog input voltage (mv) 8-bit resolution 10-bit resolution h : difference from output code change point v ref : reference voltage ( h ) 9.4.3 comparison voltage when resolution = 8 bits when 8-bit resolution is selected in the m37733mhbxxxfp, the high-order 8 bits of the 10-bit successive approximation register is the conversion result. accordingly, when compared with the 8-bit a-d converter, the comparison reference voltage is different by 3v ref /2048 (refer to the underlined portions in the table 9.4.1). the difference of the output code change point is generated as shown in figure 9.4.3. m37733mhbxxxfp (when resolution = 8 bits) 8-bit a-d converter comparison reference voltage v ref v ref ] 1 /2 8 5 n ] 2 C v ref /2 10 5 0.5 v ref /2 8 5 n C v ref /2 8 5 0.5 v ref ] 1 : reference voltage n ] 2 : contents of successive approximation register table 9.4.1 compare reference voltage 9.4 absolute accuracy and differential non-linearity error fig. 9.4.3 difference of output code change point
a-d converter 7733 group users manual 9C17 9.5 one-shot mode ?a-d operation mode selection bits (bits 4 and 3 at address 1e 16 ) = 00 2 in this mode, a-d conversion is once performed for the input voltage of one analog input pin. an a-d conversion interrupt request occurs when the a-d conversion is completed. note that an a-d conversion interrupt cannot be used when the uart2 transmission/reception interrupt is used. 9.5.1 setting for one-shot mode figure 9.5.1 shows an initial setting example for registers related to the one-shot mode. when using interrupts, settings for enabling interrupts are required. for details, refer to chapter 4. interrupts. 9.5 one-shot mode
a-d converter 7733 group users manual 9C18 a-d conversion is started. trigger is generated. falling edges input to pin ad trg when external trigger is selected when internal trigger is selected setting of the a-d conversion start flag to 1 b7 b0 a-d control register 0 (address 1e 16 ) a-d conversion start flag 1 note: writing to each bit (except bit 6) of the a-d control regis ter 0 and each bit of the a-d control register 1 must be pe rformed while a-d converter stops operating, in other words, be fore a trigger is generated. when the v ref connection selection bit is cleared from 1 to 0, wait for an interval of 1 s or more passed, and then generate a trigger. setting of the interrupt priority level b7 b0 a-d/uart2 trans./rece. interrupt control register (address 7 0 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set. setting of the a-d control registers 0, 1 b7 b0 a-d control register 0 (address 1e 16 ) 00 0 0 0 0: an 0 is selected. 0 0 1: an 1 is selected. 0 1 0: an 2 is selected. 0 1 1: an 3 is selected. 1 0 0: an 4 is selected. 1 0 1: an 5 is selected. 1 1 0: an 6 is selected. 1 1 1: an 7 is selected. trigger selection bit 0: internal trigger 1: external trigger a-d conversion start flag 0: a-d conversion is stopped. analog input selection bits b7 b0 a-d control register 1 (address 1f 16 ) 0 5 5 : it may be 0 or 1. f 2 : refer to chapter 14. clock generating circuit. a-d conversion frequency ( ad ) selection flag 0: f 2 /4 1: f 2 /2 v ref connection selection bit 0: pin v ref is connected. selection of the one-shot mode 0 setting of the port p7 direction register b7 b0 port p7 direction register (address 11 16 ) set bits corresponding to selected analog input pins to 0. when an external trigger is selected, set bit 7 to 0. an 0 an 5 an 1 an 2 an 3 an 4 b2b1b0 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution an 7 an 6 9.5 one-shot mode fig. 9.5.1 initial setting example for registers related to one-shot mode 5
a-d converter 7733 group users manual 9C19 a-d conversion interrupt request occurs. trigger is generated. input voltage of ani pin is converted. a-d converter is stopped. conversion result a-d register i 9.5.2 operation in one-shot mode figure 9.5.2 shows the conversion operation in the one-shot mode. (1) when internal trigger is selected by setting the a-d conversion start flag to 1, the a-d converter starts operating. the a-d conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the a-d register i. ?49 cycles of f ad have passed when resolution = 8 bits ?59 cycles of f ad have passed when resolution = 10 bits a when a uart2 trans./rece. interrupt is not used, the a-d conversion interrupt request bit is set to 1 simultaneously with . ? the a-d conversion start flag is cleared to 0, and then the a-d converter stops operating. (2) when external trigger is selected ______ if pin ad trg s level goes from h to l when the a-d conversion start flag = 1, the a-d converter starts operating. the a-d conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the a-d register i. ?49 cycles of f ad have passed when resolution = 8 bits ?59 cycles of f ad have passed when resolution = 10 bits a when a uart2 trans./rece. interrupt is not used, the a-d conversion interrupt request bit is set to 1 simultaneously with . ? the a-d converter stops operating. the a-d conversion start flag remains set to 1 after the a-d converter stops operating. accordingly, when ______ pin ad trg s level goes from h to l, the a-d converter restarts conversion from . note that when pin ______ ad trg s level goes from h to l during a-d conversion, the converter quits the conversion which is performed at that time and restarts it from . 9.5 one-shot mode fig. 9.5.2 conversion operation in one-shot mode
a-d converter 7733 group users manual 9C20 9.6 repeat mode ?a-d operation mode selection bits (bits 4 and 3 at address 1e 16 ) = 01 2 in this mode, a-d conversion is repeatedly performed for the input voltage of one analog input pin. no a-d conversion interrupt request occurs in this mode. the a-d conversion start flag (bit 6 at address 1e 16 ) remains set to 1 until it is cleared to 0 by software. while the a-d conversion start flag = 1, the a-d converter repeats a-d conversion without a stop. 9.6.1 setting for repeat mode figure 9.6.1 shows an initial setting example for registers related to the repeat mode. 9.6 repeat mode
a-d converter 7733 group user? manual 9?1 9.6 repeat mode fig. 9.6.1 initial setting example for registers related to repeat mode a-d conversion is started. trigger is generated. falling edges input to pin ad trg when external trigger is selected when internal trigger is selected setting of the a-d conversion start flag to ? b7 b0 a-d control register 0 (address 1e 16 ) a-d conversion start flag 1 note: writing to each bit (except bit 6) of the a-d control regis ter 0 and each bit of the a-d control register 1 must be performed while a-d converter stops operating, in other word s, before a trigger is generated. when the v ref connection selection bit is cleared from ??to ?,? wait for an interval of 1 s or more passed, and then generate a trigger. setting of the port p7 direction register b7 b0 port p7 direction register (address 11 16 ) set bits corresponding to selected analog input pins to ?.? when an external trigger is selected, set bit 7 to ?. an 0 setting of the a-d control registers 0, 1 b7 b0 a-d control register 0 (address 1e 16 ) 01 0 0 0 0: an 0 is selected. 0 0 1: an 1 is selected. 0 1 0: an 2 is selected. 0 1 1: an 3 is selected. 1 0 0: an 4 is selected. 1 0 1: an 5 is selected. 1 1 0: an 6 is selected. 1 1 1: an 7 is selected. b2b1b0 trigger selection bit 0: internal trigger 1: external trigger a-d conversion start flag 0: a-d conversion is stopped. analog input selection bits b7 b0 a-d control register 1 (address 1f 16 ) 5 : it may be ??or ?. f 2 : refer to chapter ?4. clock generating circuit. v ref connection selection bit 0: pin v ref is connected. a-d conversion frequency ( ad ) selection flag 0: f 2 /4 1: f 2 /2 selection of the repeat mode 0 an 5 an 1 an 2 an 3 an 4 0 5 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution an 7 an 6 5
a-d converter 7733 group users manual 9C22 trigger is generated. input voltage of an i pin is converted. conversion result a-d register i 9.6.2 operation in repeat mode figure 9.6.2 shows the conversion operation in the repeat mode. (1) when internal trigger is selected when the a-d conversion start flag is set to 1, the a-d converter starts operating. the first a-d conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the a-d register i. ?49 cycles of f ad have passed when resolution = 8 bits ?59 cycles of f ad have passed when resolution = 10 bits a the a-d converter continues operating until the a-d conversion start flag is cleared to 0 by software. each time a-d conversion is completed, the conversion result is transferred to the a-d register i. (2) when external trigger is selected ______ if pin ad trg s level goes from h to l when the a-d conversion start flag = 1, the a-d converter starts operating. the first a-d conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the a-d register i. ?49 cycles of f ad have passed when resolution = 8 bits ?59 cycles of f ad have passed when resolution = 10 bits a the a-d converter continues operating until the a-d conversion start flag is cleared to 0 by software. each time a-d conversion is completed, the conversion result is transferred to the a-d register i. ______ note that when pin ad trg s level goes from h to l during a-d conversion, the a-d converter quits the conversion which is performed at that time and restarts it from . 9.6 repeat mode fig. 9.6.2 conversion operation in repeat mode
a-d converter 7733 group users manual 9C23 9.7 single sweep mode ?a-d operation mode selection bits (bits 4 and 3) = 10 2 in this mode, a-d conversion is performed for the input voltage of multiple analog input pins, one at a time. a-d conversion is performed in order of an 0 , an 1 , an 2 , .... an a-d conversion interrupt request occurs when a-d conversions are completed for all analog input pins selected. 9.7.1 setting for single sweep mode figure 9.7.1 shows an initial setting example for registers related to the single sweep mode. when using interrupts, settings for enabling interrupts are required. for details, refer to chapter 4. interrupts. 9.7 single sweep mode
a-d converter 7733 group user? manual 9?4 a-d conversion is started. setting of the port p7 direction register b7 b0 port p7 direction register (address 11 16 ) set bits corresponding to selected analog input pins to ?.? when an external trigger is selected, set bit 7 to ?. an 0 trigger is generated. falling edges input to pin ad trg when external trigger is selected when internal trigger is selected setting of the a-d conversion start flag to ? b7 b0 a-d control register 0 (address 1e 16 ) a-d conversion start flag 1 setting of the a-d control registers 0, 1 b7 b0 a-d control register 0 (address 1e 16 ) 10 0 5 : it may be ??or ?. f 2 : refer to chapter ?4. clock generating circuit. b7 b0 a-d control register 1 (address 1f 16 ) a-d sweep pin selection bits b1b0 0 0: an 0 and an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) trigger selection bit 0: internal trigger 1: external trigger a-d conversion start flag 0: a-d conversion is stopped. a-d conversion frequency ( ad ) selection flag 0: f 2 /4 1: f 2 /2 selection of the single sweep mode v ref connection selection bit 0: pin v ref is connected. 0 note: writing to each bit (except bit 6) of the a-d control regis ter 0 and each bit of the a-d control register 1 must be performed while a-d con verter stops operating, in other words, before a trigger is generated. when the v ref connection selection bit is cleared from ??to ?,?wait f or an interval of 1 s or more passed, and then generate a trigger. setting of the interrupt priority level b7 b0 a-d/uart2 trans./rece. interrupt control register (address 7 0 16 ) interrupt priority level selection bits when using interrupts, one of levels 1 to 7 must be set. when disabling interrupts, level 0 must be set. an 5 an 1 an 2 an 3 an 4 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution 0 an 7 an 6 fig. 9.7.1 initial setting example for registers related to single sweep mode 9.7 single sweep mode 5 5 5
a-d converter 7733 group users manual 9C25 9.7.2 operation in single sweep mode figure 9.7.2 shows the conversion operation in the single sweep mode. (1) when internal trigger is selected when the a-d conversion start flag is set to 1, the a-d converter starts a-d conversion for an input voltage of pin an 0 . the a-d conversion for pin an 0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the a-d register 0. ?49 cycles of f ad have passed when resolution = 8 bits ?59 cycles of f ad have passed when resolution = 10 bits a a-d conversion is performed for all analog input pins selected. each time a-d conversion is completed for a pin, the conversion result is transferred to the a-d register i which corresponds to the pin. ? when a uart2 trans./rece. interrupt is not used, the a-d conversion interrupt request bit is set to 1 at completion of a . ? the a-d conversion start flag is cleared to 0, and the a-d converter stops operating. (2) when external trigger is selected ______ if pin ad trg s level goes from h to l when the a-d conversion start flag = 1, the a-d converter starts a-d conversion for the input voltage of pin an 0 . the a-d conversion for pin an 0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the a-d register 0. ?49 cycles of f ad have passed when resolution = 8 bits ?59 cycles of f ad have passed when resolution = 10 bits a a-d conversion is performed for all analog input pins selected. each time a-d conversion is completed for a pin, the conversion result is transferred to the a-d register i which corresponds to the pin. ? when a uart2 trans./rece. interrupt is not used, the a-d conversion interrupt request bit is set to 1 at completion of a . ? the a-d converter stops operating. ______ the a-d conversion start flag remains set to 1 after this. accordingly, when pin ad trg s level goes from ______ h to l, the a-d converter restarts conversion from . note that if pin ad trg s level goes from h to l during a-d conversion, the a-d converter quits the conversion which is performed at that time and restarts it from . 9.7 single sweep mode
a-d converter 7733 group users manual 9C26 a-d converter is stopped. a-d conversion interrupt request occurs. a-d register i trigger is generated. conversion result a-d register 0 input voltage of pin an 1 is converted. a-d register 1 input voltage of pin an 0 is converted. conversion result input voltage of pin an i is converted. conversion result fig. 9.7.2 conversion operation in single sweep mode 9.7 single sweep mode
a-d converter 7733 group users manual 9C27 9.8 repeat sweep mode ?a-d operation mode selection bits (bits 4 and 3 at address 1e 16 ) = 11 2 in this mode, a-d conversion is repeatedly performed for the input voltage of multiple analog input pins. a-d conversion is performed in order of an 0 , an 1 , an 2 , .... no a-d conversion interrupt request occurs in this mode. the a-d conversion start flag (bit 6 at address 1e 16 ) remains set to 1 until it is cleared to 0 by software. while the a-d conversion start flag is 1, the a-d converter repeats a-d conversion without a stop. 9.8.1 setting for repeat sweep mode figure 9.8.1 shows an initial setting example for registers related to the repeat sweep mode. 9.8 repeat sweep mode
a-d converter 7733 group users manual 9C28 a-d conversion is started. trigger is generated. falling edges input to pin ad trg when external trigger is selected when internal trigger is selected setting of the a-d conversion start flag to 1 b7 b0 a-d control register 0 (address 1e 16 ) a-d conversion start flag 1 note: writing to each bit (except bit 6) of the a-d control regis ter 0 and each bit of the a-d control register 1 must be pe rformed while a-d converter stops operating, in other words, be fore a trigger is generated. when the v ref connection selection bit is cleared from 1 to 0, wait for an period of 1 s or more passed, and then generate a trigger. setting of the a-d control registers 0, 1 b7 b0 a-d control register 0 (address 1e 16 ) 11 0 5 b7 b0 a-d control register 1 (address 1f 16 ) a-d sweep pin selection bits b1b0 0 0: an 0 and an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) 0 trigger selection bit 0: internal trigger 1: external trigger a-d conversion start flag 0: a-d conversion is stopped. 5 : it may be 0 or 1. f 2 : refer to chapter 14. clock generating circuit. a-d conversion frequency ( ad ) selection flag 0: f 2 /4 1: f 2 /2 v ref connection selection bit 0: pin v ref is connected. selection of the repeat sweep mode setting of the port p7 direction register b7 b0 port p7 direction register (address 11 16 ) set bits corresponding to selected analog input pins to 0. when an external trigger is selected, set bit 7 to 0. an 0 an 5 an 1 an 2 an 3 an 4 0 8-10 bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution an 7 an 6 9.8 repeat sweep mode fig. 9.8.1 initial setting example for registers related to repeat sweep mode 5 5
a-d converter 7733 group users manual 9C29 9.8.2 operation in repeat sweep mode figure 9.8.2 shows the conversion operation in the repeat sweep mode. (1) when internal trigger is selected when the a-d conversion start flag is set to 1, the a-d converter starts a-d conversion for an input voltage of pin an 0 . the a-d conversion for pin an 0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the a-d register 0. ?49 cycles of f ad have passed when resolution = 8 bits ?59 cycles of f ad have passed when resolution = 10 bits a a-d conversion is performed for all analog input pins selected. each time a-d conversion is completed for a pin, the conversion result is transferred to the a-d register i which corresponds to the pin. ? a-d conversion is repeatedly performed for all analog input pins selected. ? the a-d converter continues operating until the a-d conversion start flag is cleared to 0 by software. (2) when external trigger is selected ______ if pin ad trg s level goes from h to l when the a-d conversion start flag = 1, the a-d converter starts a-d conversion for the input voltage of pin an 0 . the a-d conversion for pin an 0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the a-d register 0. ?49 cycles of f ad have passed when resolution = 8 bits ?59 cycles of f ad have passed when resolution = 10 bits a a-d conversion is performed for all analog input pins selected. each time a-d conversion is completed for a pin, the conversion result is transferred to the a-d register i which corresponds to the pin. ? a-d conversion is repeatedly performed for all analog input pins selected. ? the a-d converter continues operating until the a-d conversion start flag is cleared to 0 by software. ______ note that when pin ad trg s level goes from h to l during a-d conversion, the a-d converter quits the conversion which is performed at that time and restarts it from . 9.8 repeat sweep mode
a-d converter 7733 group users manual 9C30 trigger is generated. a-d register i input voltage of pin an 0 is converted. conversion result a-d register 0 a-d register 1 conversion result conversion result input voltage of pin an 1 is converted. input voltage of pin an i is converted. 9.8 repeat sweep mode fig. 9.8.2 conversion operation in repeat sweep mode
a-d converter 7733 group users manual 9C31 9.9 precautions for a-d converter 9.9 precautions for a-d converter 1. writing to each bit (except bit 6) of the a-d control register 0 and each bit of the a-d control register 1 must be performed while the a-d converter stops operating, in other words, before a trigger is generated. when the v ref connection selection bit is cleared from 1 to 0, in other words, when pin v ref is disconnected from the resistor ladder network, wait for an period of 1 s or more, and then generate a trigger. 2. when an external trigger is selected, pin an 5 cannot be used as an analog input pin because this pin is disconnected from the comparator. if pin an 5 is selected as an analog input pin when an external trigger is selected, the a-d converter operates, but an undefined value is stored into the a-d register 5. 3. when using the a-d converter, refer to section appendix 8. countermeasures against noise, also.
a-d converter 7733 group users manual 9C32 memo 9.9 precautions for a-d converter
chapter 10 chapter 10 watchdog timer 10.1 block description 10.2 operation description 10.3 precautions for watchdog timer
instruction is executed, the watchdog timer is connected as follows; w a tchdog timer 7733 group users manual 10-2 the watchdog timer is described below and functions as follo ws: ? detects a program runaway. ? measures a certain time from when oscillation starts at te rmination of the stop mode. (refer to chapter 11. stop and wait modes. ) 10.1 block description figure 10.1.1 shows the block diagram of the watchdog timer. 10.1 block description fig. 10.1.1 block diagram of watchdog timer watchdog timer 2vcc detection circuit watchdog timer frequency selection flag f 32 f 512 value fff 16 is set. writing to the watchdog timer register (address 60 16 ) stp instruction hold request reset s q r watchdog timer interrupt request f 8 (note 1) clocks f 8 , f 32 , f 512 : refer to chapter 14. clock generating circuit. notes 1: only when the system clock selection bit (bit 3 at address 6c 16 ) = 1 and the stop mode is terminated by an interrupt request generated, the watchdog t imer is connected to clock f 8 . 2: clock f 16 is input when one of the following conditions is satisfied; ? the port-xc selection bit = 0 and the main clock externa l input selection bit = 1 ? the system clock selection bit = 0 and the main clock ex ternal input selection bit = 1 ? the port-xc selection bit = 1, the system clock selecti on bit = 1 and the sub clock external input selection bit = 1 when the stp ?connected to clock f 32 when the system clock selection bit = 0 ?connected to clock f 8 when the system clock selection bit = 1 (note 2) (note 3) 3:
watchdog timer 7733 group users manual 10-3 10.1.1 watchdog timer the watchdog timer is a 12-bit counter that down-counts a count source which is selected by the watchdog timer frequency selection flag (bit 0 at address 61 16 ). value fff 16 is automatically set in the watchdog timer in the following cases. note that an arbitrary value cannot be set in the watchdog timer. l when dummy data is written to the watchdog timer register (refer to figure 10.1.2. ) l when the most significant bit of the watchdog timer becomes 0 l when the stp instruction is executed (refer to chapter 11. stop and wait modes. ) l at reset fig. 10.1.2 structure of watchdog timer register 10.1 block description b7 b0 watchdog timer register (address 60 16 ) bit 7 to 0 watchdog timer is initialized. by writing dummy data to this register, watchdog timer? value is initialized to ?ff 16 ?(dummy data: 00 16 to ff 16 ). at reset un- defined wo rw functions
w a tchdog timer 7733 group users manual 10-4 10.1.2 watchdog timer frequency selection flag this is used to select a watchdog timers count source. figu re 10.1.3 shows the structure of the watchdog timer frequency selection flag. 10.1 block description fig. 10.1.3 structure of watchdog timer frequency selection flag 0 : clock f 512 1 : clock f 32 at reset un- defined 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 watchdog timer frequency selection flag (address 61 16 ) bit 7 to 1 not implemented. 0 watchdog timer frequency selection flag bit name clocks f 32 , f 512 : refer to chapter 14. clock generating circuit. rw
watchdog timer 7733 group users manual 10-5 10.2 operation description the watchdog timers operation is described below. for its operation in the stop and wait modes, refer to chapter 11. stop and wait modes. 10.2.1 basic operation the watchdog timer starts counting down from fff 16 . when the watchdog timers most significant bit becomes 0, in other words, when the countdown has been performed 2048 times, a watchdog timer interrupt request occurs. (refer to table 10.2.1. ) a when the interrupt request occurs ( ), value fff 16 is set to the watchdog timer. the watchdog timer interrupt is a non-maskable interrupt. when a watchdog timer interrupt request is accepted, the processor interrupt priority level (ipl) is set to 111 2 . table 10.2.1 occurrence interval of watchdog timer interrupt request 10.2 operation description when system clock = 32 khz ( note 2 ) 32768 ms 2048 ms occurrence interval of watchdog timer interrupt request when system clock = 12 mhz ( note 1 ) 87.4 ms 5.46 ms watchdog timers count source f 512 f 32 when system clock = 25 mhz ( note 1 ) 41.9 ms 2.62 ms clocks f 32 , f 512 , and system clock: refer to chapter 14. clock generating circuit. notes 1: this is applied when the system clock selection bit (bit 3 at address 6c 16 ; refer to figure 10.2.1. ) = 0 and the main clock division selection bit (bit 0 at address 6f 16 ; refer to figure 10.2.2. ) = 0. 2: this is applied when the port-xc selection bit (bit 4 at address 6c 16 ; refer to figure 10.2.1. ) = 1 and the system clock selection bit = 1. make sure that dummy data must be written to address 60 16 (watchdog timer register) by software before the most significant bit of the watchdog timer becomes 0. if writing to address 60 16 is not performed because of a program runaway and the most significant bit of the watchdog timer becomes 0, a watchdog timer interrupt request occurs. this means that a program runaway has occurred. when resetting the microcomputer after detecting a program runaway, write 1 to the software reset bit (bit 3 at address 5e 16 ) in the watchdog timer interrupt routine. (make sure that writing 1 to the software reset bit must be performed on the condition that the main clock is stably supplied.) (for details, refer to chapter 13. reset and section 17.3 watchdog timer. )
watchdog timer 7733 group users manual 10-6 10.2.2 operation in stop mode in the stop mode, the watchdog timer stops operating. immediately after the stop mode is terminated, the watchdog timer operates as follows. (1) when stop mode is terminated by a hardware reset supply of internal clock f starts immediately after the stop mode is terminated, and the microcomputer performs the operation after reset. (refer to chapter 13. reset. ) the watchdog timer frequency selection flag becomes 0, and the watchdog timer starts counting of the main clock ] 1 divided by 512 from fff 16 . main clock ] 1 : refer to chapter 14. clock generating circuit. (2) when stop mode is terminated by an interrupt request generated according to bit state listed in table 10.2.2, the watchdog timer operates as a or b described below. a. supply of internal clock f starts immediately after the stop mode is terminated, and the routine of the interrupt which is used to terminate the stop mode is executed. from fff 16 , the watchdog timer restarts counting of a count source which was counted just before the stp instruction is executed (note 1) . b. immediately after the stop mode is terminated, the watchdog timer starts counting of a count source (note 2) from fff 16 . supply of internal clock f starts when the watchdog timers most significant bit becomes 0. ( at this time, a watchdog timer interrupt request is not generated.) when supply of internal clock f starts, the microcomputer executes the routine of the interrupt which is used to terminate the stop mode. from fff 16 , the watchdog timer restarts counting of a count source which was counted just before the stp instruction is executed (note 1) . notes 1: clock f 32 or f 512 is counted. 2: when the system clock selection bit = 0, clock f 32 is counted. when the system clock selection bit = 1 and the port-xc selection bit = 0, clock f 8 is counted. 10.2 operation description
watchdog timer 7733 group users manual 10-7 table 10.2.2 watchdog timers operation and bit state related to oscillation circuit control bit state related to oscillation circuit control 10.2 operation description port-xc selection bit (bit 4 at address 6c 16 ) 0 1 system clock selection bit (bit 3 at address 6c 16 ) 0 1 0 1 main clock external input selection bit (bit 1 at address 6f 16 ) 0 1 0 1 0 1 0 1 sub clock external input selection bit (bit 2 at address 6f 16 ) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 watchdog timers operation b a b a b a b a b a note: for each bits function, refer to figures 10.2.1 and 10.2.2 . for the procedure of writing to the main clock external input selection bit and the sub clock external input selection bit, refer to figure 10.2.3. 10.2.3 operation in wait mode when the system clock stop bit at wait state (bit 5 at address 6c 16 ; refer to figure 10.2.1. ) = 1, the watchdog timer stops operating in the wait mode. furthermore, after the wait mode is terminated, the watchdog timer restarts counting from the same state as that before the watchdog timer stops. when the system clock stop bit at wait state = 0, the watchdog timer does not stop.
w a tchdog timer 7733 group users manual 10-8 10.2 operation description 10.2.4 operation in hold state the watchdog timer stops operating in the hold state. (refer to section 12.4 hold function. ) when the hold state is terminated, the watchdog timer restarts counti ng from the same state as that before the watchdog timer stops. fig. 10.2.1 structure of oscillation circuit control registe r 0 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 x cout drivability selection bit main clock stop bit system clock selection bit port-xc selection bit not implemented. 0 0 0 0 un- defined 0 0: drivability low 1: drivability high when the port-xc selection bit = 0, 0: main clock 1: main clock divided by 8 when the port-xc selection bit = 1, 0: main clock 1: sub clock 1 un- defined oscillation circuit control register 0 (address 6c 16 ) b1 b0 b2 b3 b4 b5 b6 b7 notes 0: main clock oscillation or external clock input is available. 1: main clock oscillation or external clock input is stopped. rw rw _ not implemented. _ rw ( note 1 ) 0: operate as i/o ports (p7 7 , p7 6 ). 1: operate as pins x cin and x cout . rw ( notes 2 and 3 ) rw ( note 2 ) system clock stop bit at wait state 0: output is enabled. 1: output is disabled. (refer to tables 12.1.2 and 12.1.5 ) 0: operates in the wait mode. 1: stopped in the wait mode. signal output disable selection bit rw ( note 1 ) 1: nothing can be written to this bit after reset. writing to this bit is enabled when the port-xc selection bit = 1. 2: when selecting the sub clock as the system clock, set bit 3 to 1 after setting bit 4 to 1. if the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to 1 . 3: although this bit can be set to 1, it cannot be cleared t o 0 after this bit is once set to 1. 4: represents that bits 0 to 2 and bit 7 are not us ed for the watchdog timer.
watchdog timer 7733 group users manual 10-9 fig. 10.2.2 structure of oscillation circuit control register 1 fig. 10.2.3 procedure for writing data to oscillation circuit control register 1 10.2 operation description aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa a aaaaaaaaaaaaa a a aaaaaaaaaaaaa a a aaaaaaaaaaaaa a a aaaaaaaaaaaaa a a aaaaaaaaaaaaa a aaaaaaaaaaaaaaa bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to ??in the one time prom and eprom versions (notes 1 and 2) . must be fixed to ?? (note 2) . clock prescaler reset bit 0 0 0 0 undefined 0 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input from the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. aa aa b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown in figure 10.2.3. by writing ??to this bit, clock prescaler is initialized. rw 1 (note 3) 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. ignored in the mask rom and external rom versions. 2: the case where data ?1010101 2 ?is written with the procedure shown in figure 10.2.3 is not included. 3: in the 7735 group, fix this bit to ?. 4: represents that bits 3 to 7 are not used for the watchdog timer. (note 1) (note 1) (note 1) write data ?1010101 2 .?( ldm instruction) ?when writing to bits 0 to 3 write data ?0001xxx 2. ?( ldm instruction) next instruction (b3 in figure 10.2.2) (b2 to b0 in figure 10.2.2)
watchdog timer 7733 group users manual 10-10 10.3 precautions for watchdog timer 10.3 precautions for watchdog timer 1. if dummy data is written to address 60 16 when the data length flag (m) is 0, writing to address 61 16 is simultaneously performed. accordingly, when a change of the watchdog timer frequency selection flags value (bit 0 at address 61 16 ) is not required, write the same value that is set. 2. in order to stop the watchdog timer in the hold state, the count source which is actually counted by the _____ watchdog timer is the logical product of two signals. one is the inverted signal input from pin hold, and the other is a count source which is selected by the watchdog timer frequency selection flag (clock f 32 or f 512 ). (refer to figure 10.1.1. ) accordingly, there is a possibility that counting is performed when pin _____ holds input signal level changes during a duration which is shorter than 1 cycle of the selected count source (clock f 32 or f 512) . pin hold ? input signal level changes during a duration which is shorter than 1 cycle of clock f 32 or f 512 . hold pin input signal clock f 32 or f 512 count source actually counted by watchdog timer fig. 10.3.1 watchdog timers count source 3. when the main clock is not stably supplied, do not use the software reset (that is, writing 1 to the software reset bit) as a means to reset the microcomputer at a program runaway. 4. when the stp instruction (refer to chapter 11. stop and wait modes ) is executed, the watchdog timer stops operating. for the system where the watchdog timer is used to detect a program runaway, select stp instruction disabled with stp instruction option on mask rom order confirmation form.
chapter 11 chapter 11 stop and wait modes 11.1 overview 11.2 clock generating circuit 11.3 stop mode 11.4 wait mode
stop and wait modes 7733 group users manual 11C2 the stop and wait modes are described below. when there is no need for operation of the central processing unit (cpu), the stop and wait modes are used to stop oscillation or internal clock f . the microcomputer enters the stop mode when the stp instruction is executed; the microcomputer enters the wait mode when the wit instruction is executed. 11.1 overview table 11.1.1 lists the differences between the stop and wait modes. the stop state of oscillation or internal clock f can be terminated by an interrupt request occurrence or hardware reset. table 11.1.1 differences between stop and wait modes 11.1 overview state in each mode operation after each mode is terminated state/operation stop mode wait mode item features stopped operating (note 1) stopped operating stopped operating clock timer *1 : refer to section 7.6 clock timer. clocks f 2 to f 512 , clock f 1 *2 : refer to figure 11.2.1. note 1: when the main clock external input selection bit = 1, the main-clock oscillation circuit stops operating; when the sub clock external input selection bit = 1, the sub-clock oscillation circuit stops operating. (note that, in this case, an external clock can be input.) 2: when the main clock is the system clock, pin x in is used; when the sub clock is the system clock, pin x cin is used. less than that when clocks f 2 to f 512 operate less than that when cpu operates supply of internal clock f starts after measuring a certain time by watchdog timer. supply of internal clock f starts after f 2 x 7 cycles. supply of internal clock f starts immediately after termination of the wait mode. less than that in the wait mode functions using the external clock are enabled. functions using clocks f 2 to f 512 are disabled. operating enabled from the exter- nal, a clock must stably be input to a clock input pin (note 2) . operation after hardware reset long short oscillation internal clock f clock timer *1 clocks f 2 to f 512 , clock f 1 *2 when terminated by interrupt request occurrence when terminated by hardware reset current consumption internal peripheral devices interval from termination of each mode until execution of instruction condition
stop and w ait modes 7733 group user? manual 11? 11.2 cloc k g enerating cir cuit figure 11.2.1 shows the block diagram of the clock generatin g circuit (with the stp and wit instructions). figures 11.2.2 and 11.2.3 show the structures of the oscilla tion circuit control register 0 and oscillation circuit control register 1, respectively. figure 11.2.4 shows the procedure for writing data to the os cillation circuit control register 1. fig. 11.2.1 block diagram of clock generating circuit (with stp and wit instructions) 11.2 clock generating circuit 1 1 0 0 1/8 0 cm 3 cm 4 1 1 cmi: bit i at address 6c 16 (refer to figure 11.2.2. ) cci: bit i at address 6f 16 (refer to figure 11.2.3. ) system clock s r q stp instruction 1/4 1/2 1/2 1/8 1/2 f 64 f 512 f 2 f 8 f 16 f 32 internal clock q r s wit instruction s r q reset watchdog timer frequency selection flag 1 1 0 0 wdc 12-bit watchdog timer 1/2 x in x out p7 7 /an 7 /x cin p7 6 /an 6 /x cout cc 1 cm 3 cm 5 cm 2 cm 3 cc 1 1 0 cm 4 cc 2 ? 1 0 1 0 p6 7 /tb2 in / sub 1 0 (port latch) timer b2 (event counter mode) (clock timer) (clock prescaler) 1/32 1 0 f c32 cm 4 pc 1 main clock sub clock (oscillation circuit control register 0: address 6c 16 ) cm 2 : main clock stop bit cm 3 : system clock selection bit cm 4 : port-xc selection bit cm 5 : system clock stop bit at wait state (oscillation circuit control register 1: address 6f 16 ) cc 0 : main clock division selection bit cc 1 : main clock external input selection bit cc 2 : sub clock external input selection bit (port function control register: address 6d 16 ) pc 1 : sub-clock output selection bit/timer b2 clock source selec tion bit cm 4 pc 1 1 cc 0 cm 3 cm 4 cm 3 0 interrupt request interrupt disable flag switch represented by is controlled by a signal repre sented by ? cm 4 cc 2 cm 4 stp instruction
stop and w ait modes 7733 group users manual 11C4 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 x cout drivability selection bit main clock stop bit system clock selection bit port-xc selection bit not implemented. 0 0 0 0 un- defined 0 0: drivability low 1: drivability high when the port-xc selection bit = 0, 0: main clock 1: main clock divided by 8 when the port-xc selection bit = 1, 0: main clock 1: sub clock 1 un- defined oscillation circuit control register 0 (address 6c 16 ) b1 b0 b2 b3 b4 b5 b6 b7 notes 0: main clock oscillation or external clock input is available. 1: main clock oscillation or external clock input is stopped. rw rw _ not implemented. _ rw ( note 1 ) 0: operate as i/o ports (p7 7 , p7 6 ). 1: operate as pins x cin and x cout . rw ( notes 2 and 3 ) rw ( note 2 ) system clock stop bit at wait state (note 4) 0: output is enabled. 1: output is disabled. (refer to tables 12.1.2 and 12.1.5 ) 0: operates in the wait mode. 1: stopped in the wait mode. signal output disable selection bit rw ( note 1 ) 1: nothing can be written to this bit after reset. writing to this bit is enabled when the port-xc selection bit = 1. 2: when selecting the sub clock as the system clock, set bit 3 to 1 after setting bit 4 to 1. if the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to 1 . 3: although this bit can be set to 1, it cannot be cleared t o 0 after this bit is once set to 1. 4: when setting the system clock stop bit at wait state to 1, perform it immediately before the wit instruction is executed. furthermore, clear this bit to 0 immediately after the wait mode is terminated. 11.2 clock generating circuit fig. 11.2.2 structure of oscillation circuit control registe r 0
stop and wait modes 7733 group users manual 11C5 write data ?1010101 2 .?( ldm instruction) ?when writing to bits 0 to 3 write data ?0001xxx 2 .?( ldm instruction) next instruction (b3 in figure 11.2.3) (b2 to b0 in figure 11.2.3) bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to ??in the one time prom and eprom versions (notes 1 and 2) . must be fixed to ?? (note 2) clock prescaler reset bit 0 0 0 0 undefined 0 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillati on circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is u sed when terminating stop mode. 1: sub clock is input fro m the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown in figure 11.2.4. by writing ??to this bit, clock prescaler is initialized. rw 1 (note 3) 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. ignored in the mask rom and external rom versions. 2: the case where data ?1010101 2 ?is written with the procedure shown in figure 11.2.4 is not included. 3: in the 7735 group, fix this bit to ?. 4: represents that bits 3 to 7 are not used for the stop and wait modes. (note 1) (note 1) (note 1) fig. 11.2.3 structure of oscillation circuit control register 1 fig. 11.2.4 procedure for writing data to oscillation circuit control register 1 11.2 clock generating circuit
stop and wait modes 7733 group users manual 11C6 11.3 stop mode when the stp instruction is executed, the main-clock and sub-clock oscillation circuits stop operating. this state is called stop mode. in the stop mode, even when oscillation stops, the contents of the internal ram can be retained if there is 2 v of vcc (power source voltage) or more. furthermore, because the cpu and all internal peripheral devices which use clocks f 2 to f 512 *1 stop operating, power consumption is lowered. refer to section 17.4 power saving for lowering the power consumption. table 11.3.1 lists the microcomputers state/operation in the stop mode and after the stop mode is terminated. table 11.3.2 lists the pin state in the stop mode. table 11.3.1 microcomputers state/operation in stop mode and after stop mode is terminated 11.3 stop mode state in stop mode operation after stop mode is terminated when terminated by interrupt request occurrence when terminated by hardware reset item f(x in )/32 f(x cin )/32 stopped stopped operating enabled only in the event counter mode operating enabled only when the external clock is selected stopped stopped refer to table 11.3.2 internal peripheral devices clocks f 2 to f 512 *1 , clock f 1 *2 : refer to figure 11.2.1. clock timer *3 : refer to section 7.6 clock timer. clock input pin *4 : when the system clock is the main clock, pin x in is used; when the system clock is the sub clock, pin x cin is used. h in order to select whether to use the watchdog timer or not when terminating the stop mode, specify the main clock external input selection bit (bit 1 at address 6f 16 ; when the main clock is used) or the sub clock external input selection bit (bit 2 at address 6f 16 ; when the sub clock is used). (refer to figure 11.2.3, sections 11.3.2 stop mode terminating operation by interrupt request occur- rence (when using watchdog timer) and 11.3.3 stop mode terminating operation by interrupt request occurrence (when not using watchdog timer). state/operation watchdog timer is used when terminating the stop mode watchdog timer is not used when terminating the stop mode supply of internal clock f starts after measuring a certain time by watchdog timer. operation after hardware reset supply of internal clock f starts after f 2 x 7 cycles. condition from the external, a clock must stably be input to a clock input pin *4 . oscillation internal clock f clocks f 2 to f 512 *1 , clock f 1 *2 clock timer *3 timer a, timer b serial i/o a-d converter watchdog timer pins
stop and wait modes 7733 group users manual 11C7 table 11.3.2 pin state in stop mode 11.3 stop mode state single-chip mode memory expansion microprocessor mode mode pins when the standby state selection bit * 1 = 0 when the standby state selection bit * 1 = 1 n when the signal output disable selection bit = 0, h level is output n when the signal output disable selection bit = 1, l level is output. n when the signal output disable selection bit = 0, h level is output. n when the signal output disable selection bit = 1, l level is output. same as in the micro- processor mode h level is output. __ e __ r/ w, ____ bhe, _____ hlda ale a 0 Ca 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 l level is output. retains the same state in which the stp instruction is executed. n when the clock f 1 output selection bit *2 = 1 f 1 : l level is output. n when the clock f 1 output selection bit = 0 p4 2 : retains the same state in which the stp instruction is executed. p0 to p8 (not including p4 2 ) : retains the same state in which the stp instruction is executed. p4 3 to p4 7 , p5 to p8 :retains the same state in which the stp instruction is executed. ports n when the signal output disable selection bit *3 = 0 f 1 : l level is output. n when the signal output disable selection bit = 1 p4 2 : bit 2s value of the port p4 register is output (note) . p4 2 / f 1 standby state selection bit *1 : bit 0 at address 6d 16 (refer to figure 11.3.1. ) clock f 1 output selection bit *2 : bit 7 at address 5e 16 (refer to section 12.1 signals required for accessing external devices. ) signal output disable selection bit *3 : bit 6 at address 6c 16 (refer to section 12.1 signals required for accessing external devices. ) note: make sure to set bit 2 of the port p4 direction register to 1. 11.3.1 output levels of external bus and bus control signals in stop mode in the memory expansion or microprocessor mode, the output levels of the external bus and bus control signals in the stop mode can be set by software. by setting the standby state selection bit (bit 0 at address 6d 16 ) to 1, these output levels become levels set by software. figure 11.3.1 shows an output level setting example in the stop mode. in the single-chip mode, do not set the standby state selection bit to 1. output levels can be set. (refer to section 11.3.1 output levels of external bus and bus control signals in stop mode. )
stop and w ait modes 7733 group users manual 11C8 stp instruction is executed. note 2: this bits value also affects the pin state in the wait mod e. (refer to figure 11.4.1. ) setting of the output levels for the external bus and bus co ntrol signals (not including e ) b7 b0 port p0 direction register (address 4 16 ) port p1 direction register (address 5 16 ) port p2 direction register (address 8 16 ) port p3 direction register (address 9 16 ) must be fixed to ff 16. 1 b7 b0 set output level by the bit which corresponds to each pin. 0: l level output 1: h level output note 3: this bit's value also affects the following: ? output state of bus control signals and other s after the stop mode is terminated (refer to chapter 12. connecting external devices ) ? pin state in the wait mode. (refer to figure 11.4.1. ) furthermore, description of pin p4 2 / 1 is applied only in the microprocessor mode. setting of e signals output level (setting of pin p4 2 / 1 s state) b7 b0 oscillation circuit control register 0 (address 6c 16 ) signal output disable selection bit ( note 3 ) 0: in the stop mode, pin e outputs h level, and pin p4 2 / 1 outputs l level. 1: in the stop mode, pin e outputs l level, and pin p4 2 / 1 outputs bit 2s value of port p4 register. port function control register (address 6d 16 ) standby state selection bit ( note 2 ) b7 b0 setting of the standby state selection bit to 1 01 b7 b0 port p4 direction register (address c 16 ) 1 b7 b0 port p4 register (address a 16 ) 0: l level output 1: h level output ? when setting the signal output disable selection bit to 1 in the microprocessor mode ? when setting the clock 1 output selection bit to 0 in the memory expansion mode ? when setting the signal output disable selection bit to 0 in the microprocessor mode ? when setting the clock 1 output selection bit to 1 in the memory expansion mode note 1: this is applied only in the microprocessor mode. in the memory expansion mode, it may be 0 or 1 because the i/o port function is selected. (note 1) port p0 register (address 2 16 ) port p1 register (address 3 16 ) port p2 register (address 6 16 ) port p3 register (address 7 16 ) 11.3 stop mode fig. 11.3.1 output level setting example in stop mode (memor y expansion or microprocessor mode) 1 1 1 1 1 1 1
stop and wait modes 7733 group users manual 11C9 11.3.2 stop mode terminating operation by interrupt request occurrence (when using watchdog timer) when there is little possibility that a clock is stably supplied from an oscillation circuit (note 1) in returning from the stop mode, instruction execution can be started after a certain time (note 2) measured by the watchdog timer. notes 1: a clock is supplied in one of the following ways: l an oscillation circuit operates by itself. l an external clock is input. 2: a certain time means an interval from occurrence of an interrupt request until stabilization of clock supply. when an interrupt request occurs, an oscillator starts oscillating. simultaneously, supply of clocks f 2 to f 512 starts. by start of oscillation, the watchdog timer starts counting. the watchdog timer counts f 32 when the system clock selection bit (bit 3 at address 6c 16 ; refer to figure 11.2.2. ) = 0 or f 8 when the system clock selection bit = 1. a when the watchdog timers msb becomes 0, supply of internal clock f starts. at the same time, the watchdog timers count source returns to a count source (clock f 32 or f 512 ) which is selected by the watchdog timer frequency selection flag (bit 0 at address 61 16 ). ? the interrupt request which occurs in is accepted. table 11.3.3 lists interrupts which can be used for termination of the stop mode. table 11.3.3 interrupts which can be used for termination of stop mode when the key input interrupt function is selected ____ int 2 interrupt: when the key input interrupt function is invalid. in the event counter mode when the external clock is selected interrupt conditions for each function which generates interrupt request key input interrupt ____ int i interrupt (i = 0 to 2) timer ai interrupt (i = 0 to 4) timer bi interrupt (i = 0 to 2) uarti transmission interrupt (i = 0, 1) uarti reception interrupt (i = 0, 1) uart2 transmission/reception interrupt note 1: because an oscillator has stopped oscillating, each function is available only in the conditions listed in table 11.3.3. note that the a-d converter and clock timer (refer to section 7.6 clock timer ) do not operate, also. 2: because an oscillator has stopped oscillating, interrupts not listed in table 11.3.3 cannot be used. 3: for each interrupt, refer to chapters 4. interrupts, 5. key input interrupt function, 6. timer a, 7. timer b, and 8. serial i/o. 11.3 stop mode
stop and wait modes 7733 group users manual 11C10 when using the watchdog timer in termination of the stop mode, make sure to set as follows before executing the stp instruction. n enable an interrupt which is used for termination. also, make sure that the interrupt priority level of an interrupt which is used for termination is higher than the processor interrupt priority level (ipl) of a routine where the stp instruction is executed. furthermore, when multiple interrupts in table 11.3.3 are enabled, the stop mode is terminated by the interrupt request which occurs first. after oscillation starts ( ), there is a possibility that an interrupt request occurs until the supply of internal clock f starts ( a ). interrupt requests which occur during this period are accepted in order of priority after the watchdog timers msb becomes 0. for interrupts which have no need to be accepted, set their interrupt priority levels to 0 (interrupt disabled) before executing the stp instruction. n when the system clock is the main clock or the main clock divided by 8, set the main clock external input selection bit (bit 1 at address 6f 16 ; refer to figure 11.2.3. ) to 0. when the system clock is the sub clock, set the sub clock external input selection bit (bit 2 at address 6f 16 ) to 0. 11.3.3 stop mode terminating operation by interrupt request occurrence (when not using watchdog timer) when a clock is stably input from the external to a clock input pin (refer to figures 14.2.2 and 14.2.4. ), instruction execution can be started immediately after the termination of the stop mode. when an interrupt request occurs, clock input from pin x in starts. simultaneously, supply of clocks f 2 to f 512 starts. supply of internal clock f starts after 7 cycles of f 2 . a the interrupt request which occurs in is accepted. table 11.3.3 lists interrupts which can be used for termination. when not using the watchdog timer in termination of the stop mode, make sure to set as follows before executing the stp instruction. n enable an interrupt which is used for termination. also, make sure that the interrupt priority level of an interrupt which is used for termination is higher than the processor interrupt priority level (ipl) of a routine where the stp instruction is executed. furthermore, when multiple interrupts in table 11.3.3 are enabled, the stop mode is terminated by the interrupt request which occurs first. n when the system clock is the main clock or the main clock divided by 8, set the main clock external input selection bit (bit 1 at address 6f 16 ; refer to figure 11.2.3. ) to 1. when the system clock is the sub clock, set the sub clock external input selection bit (bit 2 at address 6f 16 ) to 1. 11.3 stop mode
interrupt request which was used for stop and w ait modes 7733 group users manual 11C11 stopped stopped when not using watchdog timer l watchdog timer starts counting. l supply of cpu (internal clock ) starts. l interrupt request which was used for termination is accepted. internal clock cpu internal peripheral devices l stp instruction is executed l interrupt request which is used for termination occurs. l clock input from pin x in or x cin starts. value of watchdog timer fff 16 7ff 16 interrupt request which is used for termination (interrupt request bit) system clock : f(x in ) or f(x cin ) l interrupt request which is used for termination occurs. l oscillation starts. (when an external clock is input from pin x in , clock input starts.) watchdog timer starts counting. internal clock cpu internal peripheral devices l stp instruction is executed l watchdog timers msb = 0 (however, watchdog timer interrupt request does not occur.) supply of cpu (internal clock ) starts. l termination is accepted. value of watchdog timer fff 16 7ff 16 interrupt request which is used for termination (interrupt request bit) when using watchdog timer system clock : f(x in ) or f(x cin ) note 1: sub clock (f(x cin )) is stopped at l level in the stop mode. stopped 32/f(x in ) 5 2048 counts or 8/f(x cin ) 5 2048 counts stop mode (note 1) ....... operating operating operating operating operating 2/f(x in ) 5 7 counts stop mode ....... (note 2) stopped operating operating operating operating operating stopped stopped note 2: in the stop mode, clock input can be stopped. in order to stop clock input, be sure to generate an interru pt request after a clock is stably supplied when returning from the stop mode. 0 1 0 1 11.3 stop mode fig. 11.3.2 stop mode terminating sequence by interrupt requ est occurrence l l
stop and wait modes 7733 group users manual 11C12 11.3.4 stop mode terminating operation by hardware reset ______ when terminating the stop mode by hardware reset, input l level to pin reset from the external circuit until oscillation of an oscillator which is connected to the main-clock oscillation circuit is stabilized. the cpu and sfr area are initialized in the same way as at system reset. however, the internal ram area retains the same contents as that before the stp instruction was executed. the terminating sequence is the same as the internal processing sequence after reset. when determining whether hardware reset was applied for termination of the stop mode or system reset was applied, use software after reset. for reset, refer to chapter 13. reset. 11.3.5 precautions for stop mode 1. in the mask rom version, select stp instruction enabled with stp instruction option on mask rom order confirmation form. (in the built-in prom and external rom versions, stp instruction is always enabled.) 2. stop mode terminating operation by an interrupt request occurrence (when not using watchdog timer) can be selected only when an external clock is stably input to a clock input pin for a clock which is selected as the system clock. in one of the following cases, select stop mode terminating operation by an interrupt request occur- rence (when using watchdog timer): l when an oscillator is connected between input and output pins for a clock which is selected as the system clock l when there is a possibility that the above external clock is temporarily unstable in termination of the stop mode 11.3 stop mode
stop and wait modes 7733 group users manual 11C13 operating operating operating stopped stopped operating operating 11.4 wait mode when the wit instruction is executed, internal clock f stops. (the oscillator does not stop oscillating.) this state is called wait mode. in the wait mode, power consumption can be lowered with vcc (power source voltage) retained. refer to section 17.4 power saving for lowering the power consumption. table 11.4.1 lists the microcomputers state/operation in the wait mode and after the wait mode is terminated. table 11.4.2 lists the pin state in the wait mode. table 11.4.1 microcomputers state/operation in wait mode and after wait mode is terminated 11.4 wait mode when terminated by inter- rupt request occurrence when terminated by hardware reset supply of internal clock f starts immediately after termination. operation after hardware reset state in wait mode operation after wait mode is terminated stopped operating stopped operating refer to table 11.4.2. oscillation internal clock f clocks f 2 to f 512 *1 , clock f 1 *2 clock timer *3 timer a, timer b serial i/o a-d converter watchdog timer pins internal peripheral devices f(x in )/32 f(x cin )/32 stopped operating item clocks f 2 to f 512 * 1 , clock f 1 * 2 : refer to figure 11.2.1. clock timer * 3 : refer to section 7.6 clock timer. h in order to select the state of clocks f 2 to f 512 in the wait mode, specify the system clock stop bit at wait state (bit 5 at address 6c 16 ). (refer to figure 11.2.2 and section 11.4.1 state of clocks f 2 to f 512 in wait mode. ) state/operation when clocks f 2 to f 512 are stopped when clocks f 2 to f 512 are not stopped operating enabled only in the event counter mode. operating enabled only when the external clock is selected.
stop and wait modes 7733 group users manual 11C14 11.4 wait mode table 11.4.2 pin state in wait mode state single-chip mode memory expansion microprocessor mode mode pins when the standby state selection bit * 1 = 0 when the standby state selection bit * 1 = 1 n when the signal output disable selection bit = 0, h level is output. n when the signal output disable selection bit = 1, l level is output. n when the signal output disable selection bit = 0, h level is output. n when the signal output disable selection bit = 1, l level is output. same as in the micro- processor mode h level is output. __ e __ r/ w, ____ bhe, _____ hlda ale a 0 Ca 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 output levels can be set. (refer to section 11.4.2 output levels of external bus and bus control signals in wait mode ) l level is output. n when the signal output disable selection bit *3 = 0 f 1 : operating when the system clock stop bit at wait state = 0. l level is output when the system clock stop bit at wait state = 1. n when the signal output disable selection bit = 1 p4 2 : bit 2s value of port p4 register is output (note) . n when the clock f 1 output selection bit *2 = 1 f 1 : operating when the system clock stop bit at wait state *4 = 0. l level is output when the system clock stop bit at wait state = 1. n when the clock f 1 output selection bit = 0 p4 2 : retains the same state in which the wit instruction is executed. p4 2 / f 1 retains the same state in which the wit instruction is ex- ecuted. p4 3 to p4 7 , p5 to p8 : retains the same state in which the wit instruction is executed. ports p0 to p8 (not including p4 2 ) : retains the same state in which the wit instruction is executed. standby state selection bit *1 : bit 0 at address 6d 16 (refer to figure 11.4.1. ) clock f 1 output selection bit *2 : bit 7 at address 5e 16 (refer to section 12.1 signals required for accessing external devices. ) signal output disable selection bit *3 : bit 6 at address 6c 16 (refer to section 12.1 signals required for accessing external devices. ) system clock stop bit at wait state *4 : bit 5 at address 6c 16 (refer to section 11.4.1 state of clocks f 2 to f 512 in wait mode. ) note: make sure to set bit 2 of the port p4 direction register to 1.
stop and wait modes 7733 group users manual 11C15 11.4.1 state of clocks f 2 to f 512 in wait mode the state of clocks f 2 to f 512 in the wait mode can be selected by the system clock stop bit at wait state (bit 5 at address 6c 16 : refer to figure 11.2.2 .). when supply of clocks f 2 to f 512 is stopped in the wait mode, power consumption can further be lowered. when supply of clocks f 2 to f 512 is stopped, internal peripheral devices which use clocks f 2 to f 512 stop operating as in the stop mode. furthermore, when pin p4 2 / f 1 functions as a clock f 1 output pin, this pin outputs l level. (refer to table 11.4.2. ) when supply of clocks f 2 to f 512 is not stopped, both of the internal peripheral devices operation and clock f 1 output do not stop. note that, in the microprocessor mode, clock f 1 output stops when the signal output disable selection bit = 1. in both cases, internal clock f stops, so that the cpu does not operate. furthermore, because clock fc 32 does not stop operating, the clock timer continues operating. (refer to table 11.4.3. ) 11.4.2 output levels of external bus and bus control signals in wait mode in the memory expansion or microprocessor mode, the output levels of the external bus and bus control signals in the wait mode can be set by software. by setting the standby state selection bit (bit 0 at address 6d 16 ) to 1, these output levels become levels set by software. figure 11.4.1 shows an output level setting example in the wait mode. in the single-chip mode, do not set the standby state selection bit to 1. (fix this bit to 0.) 11.4 wait mode
stop and w ait modes 7733 group users manual 11C16 ? when setting the signal output disable selection bit to 1 in the microprocessor mode ? when setting the clock 1 output selection bit to 0 in the memory expansion mode note 2 : this bits value also affects the pin state in the stop mo de. (refer to figure 11.3.1 .) setting of the output levels for the external bus and bus co ntrol signals (not including e) b7 b0 port p0 direction register (address 4 16 ) must be fixed to ff 16 . 1 port p1 direction register (address 5 16 ) port p2 direction register (address 8 16 ) port p3 direction register (address 9 16 ) b7 b0 port p0 register (address 2 16 ) set output level by the bit which corresponds to each pin. 0: l level output 1: h level output port p1 register (address 3 16 ) port p2 register (address 6 16 ) port p3 register (address 7 16 ) setting of e signals output level (setting of pin p4 2 / 1 s state) b7 b0 oscillation circuit control register 0 (address 6c 16 ) signal output disable selection bit (note 3) 0: in the wait mode, pin e outputs h level. pin p4 2 / 1 operates when system clock stop bit at wait state = 0 and outputs l level when this bit = 1. 1: in the wait mode, pin e outputs l level. pin p4 2 / 1 outputs bit 2s value of port p4 register. port function control register (address 6d 16 ) standby state selection bit (note 2) b7 b0 setting of the standby state selection bit to 1 01 b7 b0 port p4 direction register (address c 16 ) 1 b7 b0 port p4 register (address a 16 ) 0: l level output 1: h level output wit instruction is executed. note 3 : this bits value also affects the following: ? output state of bus control signals and othe rs after the wait mode is terminated (refer to chapter 12. connecting external devices. ) ? pin state in the stop mode. (refer to figure 11.3.1. ) furthermore, description of pin p4 2 / 1 is applied only in the microprocessor mode. ? when setting the signal output disable selection bit to 0 in the microprocessor mode ? when setting the clock 1 output selection bit to 1 in the memory expansion mode note 1: this is applied only in the microprocessor mode. in the memory expansion mode, it may be 0 or 1 because the i/o port function is selected. (note 1) 11.4 wait mode fig. 11.4.1 output level setting example in wait mode (memor y expansion or microprocessor mode) 1 1 1 1 1 1 1
stop and wait modes 7733 group users manual 11C17 11.4.3 wait mode terminating operation by interrupt request occurrence when an interrupt request occurs with supply of clocks f 2 to f 512 stopped, the clock supply restarts. supply of internal clock f starts. a the interrupt request which occurs in is accepted. an interrupt which can be used for termination depends on the state of clocks f 2 to f 512 in the wait mode. (refer to table 11.4.3. ) table 11.4.3 interrupts which can be used for termination of wait mode 11.4 wait mode conditions for each function which generates interrupt request interrupt when the key input interrupt function is selected ____ int 2 interrupt: when the key input interrupt function is invalid. enabled only when the external clock is selected disabled when timer b2 functions as the clock timer disabled key input interrupt ____ int i interrupt (i = 0 to 2) timer ai interrupt (i = 0 to 4) timer bi interrupt (i = 0 to 2) uarti transmission interrupt (i = 0 to 2) uarti reception interrupt (i = 0 to 2) clock timer * (timer b2) interrupt a-d conversion interrupt when clocks f 2 to f 512 are not stopped in the event counter mode enabled in all modes always enabled f(x in )/32 f(x cin )/32 enabled in one-shot mode and single sweep mode clock timer * : refer to section 7.6 clock timer. h for each interrupt, refer to chapters 4. interrupts, 5. key input interrupt function, 6. timer a, 7. timer b, 8. serial i/o, and 9. a-d converter. before executing the wit instruction, be sure to enable an interrupt which is used for termination. also make sure that the interrupt priority level of an interrupt which is used for termination is higher than the processor interrupt priority level (ipl) of a routine where the wit instruction is executed. furthermore, when multiple interrupts in table 11.4.3 are enabled, the wait mode is terminated by the interrupt request which occurs first. 11.4.4 wait mode terminating operation by hardware reset the cpu and sfr area are initialized in the same way as at system reset. however, the internal ram area retains the same contents as that before the wit instruction was executed. the terminating sequence is the same as the internal processing sequence after reset. when determining whether hardware reset was applied for termination of the wait mode or system reset was applied, use software after reset. for reset, refer to chapter 13. reset. when clocks f 2 to f 512 are stopped
stop and wait modes 7733 group users manual 11C18 11.4 wait mode memo
chapter 12 chapter 12 connecting external devices 12.1 signals required for accessing external devices 12.2 software wait 12.3 ready function 12.4 hold function
connecting external devices 7733 group users manual 12C2 12.1 signals required for accessing external devices functions and operations of signals required for accessing external devices are described below. when connecting external devices which require a long access time, refer to sections 12.2 software wait, 12.3 ready function, and 12.4 hold function, also. when connecting external devices, make sure that the microcomputer operates in the memory expansion or microprocessor mode. (refer to section 2.5 processor modes. ) when the microcomputer operates in __ these modes, ports p0 to p4 and pin e function as i/o pins of signals required for accessing external devices. figure 12.1.1 shows the pin configuration in the memory expansion or microprocessor mode. table 12.1.1 __ lists the functions of ports p0 to p4 and pin e in the memory expansion or microprocessor mode. 12.1 signals required for accessing external devices
connecting external devices 7733 group users manual 12C3 h 1 in the microprocessor mode by setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pins level can be fixed in the stop or wait mode. when external data bus is 8 bits wide (byte = h) : external address bus, external data bus, and bus control signals when external data bus is 16 bits wide (byte = l) : external address bus, external data bus, and bus control signals a 20 /d 4 (p2 4 ) a 21 /d 5 (p2 5 ) a 22 /d 6 (p2 6 ) a 23 /d 7 (p2 7 ) r/w(p3 0 ) bhe(p3 1 ) ale(p3 2 ) hlda(p3 3 ) v ss e x out x in reset cnv ss byte hold a 11 /d 11 (p1 3 ) a 12 /d 12 (p1 4 ) a 13 /d 13 (p1 5 ) a 14 /d 14 (p1 6 ) a 15 /d 15 (p1 7 ) a 16 /d 0 (p2 0 ) a 17 /d 1 (p2 1 ) a 18 /d 2 (p2 2 ) a 19 /d 3 (p2 3 ) rdy p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 a 0 (p0 0 ) a 1 (p0 1 ) a 2 (p0 2 ) a 3 (p0 3 ) a 4 (p0 4 ) a 5 (p0 5 ) a 6 (p0 6 ) a 7 (p0 7 ) a 8 /d 8 (p1 0 ) a 9 /d 9 (p1 1 ) a 10 /d 10 (p1 2 ) p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 14 3 25 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 6 7 8 9 1 01 1 1 21 31 41 51 61 7 1 81 9 2 02 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 43 42 41 m37733mhbxxxfp 22 23 24 p4 7 p4 6 p4 5 p4 4 p4 3 h p4 2 / 1 a 20 /d 4 (p2 4 ) a 21 /d 5 (p2 5 ) a 22 /d 6 (p2 6 ) a 23 /d 7 (p2 7 ) r/w(p3 0 ) bhe(p3 1 ) ale(p3 2 ) hlda(p3 3 ) v ss e x out x in reset cnvss byte hold rdy a 11 (p1 3 ) a 12 (p1 4 ) a 13 (p1 5 ) a 14 (p1 6 ) a 15 (p1 7 ) a 16 /d 0 (p2 0 ) a 17 /d 1 (p2 1 ) a 18 /d 2 (p2 2 ) a 19 /d 3 (p2 3 ) p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 a 0 (p0 0 ) a 1 (p0 1 ) a 2 (p0 2 ) a 3 (p0 3 ) a 4 (p0 4 ) a 5 (p0 5 ) a 6 (p0 6 ) a 7 (p0 7 ) a 8 (p1 0 ) a 9 (p1 1 ) a 10 (p1 2 ) 14 3 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 43 42 41 m37733mhbxxxfp p4 7 p4 6 p4 5 p4 4 p4 3 h p4 2 / 1 h 1 in the microprocessor mode by setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pins level can be fixed in the stop or wait mode. fig. 12.1.1 pin configuration in memory expansion or micropr ocessor mode (top view) 12.1 signals required for accessing external devices
this signal is affected by the signal output disable select ion bit (bit 6 at address 6c connecting external devices 7733 group users manual 12C4 notes 1: in the memory expansion mode, this pin functions as a progr ammable i/o port. furthermore, it can be switched to be a cl ock 1 output pin when selected by software. in the microprocessor mode, t his pin is affected by the signal output disable selection b it (bit 6 at address 6 c 16 ). (refer to table 12.1.5 .) 2 : 16 ). (refer to table 12.1.2 .) pin name hlda ale 16 bits (byte = l) 8 bits (byte = h) external data bus width ale p rdy hold rdy 1 hold e (note 2) 1 p : functions as programmable i/o port p4 7 to p4 3 (note 1) hlda r/ w bhe 1 p4 7 to p4 3 hold rdy bhe ale r/ w hlda a 7 to a 0 a 7 to a 0 a 7 to a 0 a 15 /d 15 to a 8 /d 8 a 15 to a 8 d(odd) d(odd) : data at odd address a 15 /d 15 to a 8 /d 8 a 15 to a 8 a 15 to a 8 a 23 /d 7 to a 16 /d 0 a 23 to a 16 d(even) d(even) : data at even address a 23 /d 7 to a 16 /d 0 a 23 to a 16 a 23 /d 7 to a 16 /d 0 d d : data bhe r/w e __ table 12.1.1 functions of ports p0 to p4 and pin e in memory expansion or microprocessor mode 12.1 signals required for accessing external devices
connecting external devices 7733 group users manual 12C5 : external area 000000 16 internal ram area sfr area memory expansion mode 020000 16 ffffff 16 internal ram area sfr area microprocessor mode 001000 16 000000 16 ffffff 16 001000 16 000080 16 internal rom area (note) 000080 16 note: this is applied when the memory allocation selection bits (bits 2 to 0 at address 63 16 ) = ?00 2 .? for details, refer to section ?.4 memory allocation. 12.1.1 external bus (a 0 to a 7 , a 8 /d 8 to a 15 /d 15 , and a 16 /d 0 to a 23 /d 7 ) the address is output from pins a 0 to a 23 and specify the external area. figure 12.1.2 shows the external area. pins a 8 to a 23 of the external address bus and pins d 0 to d 15 of the external data bus share the same pins. when pin bytes level, which is described later, is l, in other words, when the external data bus is 16 bits wide, pins a 8 /d 8 to a 15 /d 15 and a 16 /d 0 to a 23 /d 7 perform address output and data input/ output with the time-sharing method. when pin bytes level is h, in other words, when the external data bus is 8 bits wide, pins a 16 /d 0 to a 23 /d 7 perform address output and data input/output with the time-sharing method and pins a 8 to a 15 output the address. fig. 12.1.2 external area 12.1 signals required for accessing external devices
connecting external devices 7733 group users manual 12C6 12.1.2 external data bus width selection signal (pin bytes level) this signal is used to select the external data bus width from 8 bits and 16 bits. when this signal level is l, the external data bus is 16 bits wide; when this signal level is h, the external data bus is 8 bits wide. (refer to table 12.1.1. ) this signal level must be fixed to either h or l. this signal is valid only for the external areas. (when the internal area is accessed, the data bus is always 16 bits wide.) __ 12.1.3 enable signal ( e ) when data is read or written, this signal level is l. this signal is affected by the signal output disable selection bit (bit 6 at address 6c 16 ). (refer to table 12.1.2 .) __ table 12.1.2 e state when the external area is accessed when the internal area is accessed when the standby state selection bit = 1 in the stop or wait mode when the standby state selection bit = 0 in the stop or wait mode when not in the stop or wait mode when in the stop or wait mode signal output disable selection bit 01 memory expansion or microprocessor mode single-chip mode processor mode conditions table 12.1.3 data bus state __ e __ r/ w data bus state h h not used l l h read l write h for the stop and wait modes and the standby state selection bit, refer to chapter 11. stop and wait modes. : not affected by the signal output disable selection bit. __ 12.1.4 read/write signal (r/ w ) this signal indicates data bus state. when data is written, this signal level is l. table 12.1.3 lists the data __ __ bus state indicated by signals e and r/ w . operating operating stopped at h level stopped at h level stopped at l level stopped at h level operating stopped at l level stopped at h level stopped at l level 12.1 signals required for accessing external devices
connecting external devices 7733 group users manual 12C7 ____ 12.1.5 byte high enable signal ( bhe ) this signal indicates access to an odd address. this signal level is l when accessing only an odd address or when simultaneously accessing both an odd address and an even address. this signal is used when connecting memory or i/o of which data bus is 8 bits wide with the 16-bit external data bus used. table 12.1.4 lists the relationship between signal a 0 of the external address bus, signal ____ bhe , and access address. ____ table 12.1.4 relationship between signals a 0 , bhe and access address a 0 ____ bhe access address odd address (1-byte access) h l even and odd addresses (simultaneous 2-byte access) l l l h even address (1-byte access) 12.1.6 address latch enable signal (ale) this signal is used to latch an address from a multiplexed signal. this multiplexed signal consists of the address and data and is input or output to or from pins a 8 /d 8 to a 15 /d 15 , a 16 /d 0 to a 23 /d 7 . when this signal level is h, take the address into a latch and output it simultaneously. when this signal level is l, retain the latched address. ____ 12.1.7 signal related to ready function ( rdy ) this signal is required to use the ready function. (refer to section 12.3 ready function. ) _____ _____ 12.1.8 signals related to hold function ( hold , hlda ) these signals are required to use the hold function. (refer to section 12.4 hold function. ) 12.1.9 clock f 1 this signal has the same period as internal clock f . whether to output or stop clock f 1 can be selected by software. however, the method of this selection depends on the processor mode. table 12.1.5 lists the method to select whether to output or stop clock f 1 . figure 12.1.3 shows the clock f 1 output start timing. table 12.1.5 method to select whether to output or stop clock f 1 clock f 1 output clock f 1 stopped remark processor mode single-chip or memory expansion mode microprocessor mode clear the signal output disable selection bit *2 to 0. set the signal output disable selection bit to 1. (note) clock f 1 is output after reset. the clock f 1 output selection bit is ignored. set the clock f 1 output selection bit *1 to 1. clear the clock f 1 output selection bit to 0. (pin p4 2 functions as a programmable i/o port.) clock f 1 is stopped after reset. the signal output disable selection bit is ignored. clock f 1 output selection bit *1 : bit 7 at address 5e 16 signal output disable selection bit *2 : bit 6 at address 6c 16 (refer to table 12.1.2 .) note: in this case, make sure that bit 2 at address c 16 (port p4 direction register) is set to 1. when bit 2 at address a 16 (port p4 register) = 0, l level is output: when this bit = 1, h level is output. 12.1 signals required for accessing external devices
connecting external devices 7733 group users manual 12C8 1: nothing can be written to this bit after reset. writing to this bit is enabled when the port-xc selection bit = 1. 2: when selecting the sub clock as the system clock, set bit 3 to 1 after setting bit 4 to 1. if the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to 1 . 3: although this bit can be set to 1, it cannot be cleared t o 0 after this bit is once set to 1. 4: when setting the system clock stop bit at wait state to 1, perform it immediately before the wit instruction is executed. furthermore, clear this bit to 0 immediately after the wait mode is terminated. 5: represents that bits 0 to 5 and 7 are not used for a ccess control of external area. (functions of these bits are valid.) bit bit name functions at reset rw 0 1 2 3 4 5 6 7 x cout drivability selection bit main clock stop bit system clock selection bit po rt-xc selection bit. not implemented. 0 0 0 0 un- defined 0 0: drivability low 1: drivability high when the port-xc selection bit = 0, 0: main clock 1: main clock divided by 8 when the port-xc selection bit = 1, 0: main clock 1: sub clock 1 un- defined oscillation circuit control register 0 (address 6c 16 ) b1 b0 b2 b3 b4 b5 b6 b7 notes 0: main clock oscillation or external clock input is available. 1: main clock oscillation or external clock input is stopped. rw rw C not implemented. rw ( note 1 ) 0: operate as i/o ports (p7 7 , p7 6 ). 1: operate as pins x cin and x cout . rw ( notes 2 and 3 ) rw ( note 2 ) system clock stop bit at wait state (note 4) 0: output is enabled. 1: output is disabled. (refer to tables 12.1.2 and 12.1.5 ) 0: operates in the wait mode. 1: stopped in the wait mode. signal output disable selection bit rw ( note 1 ) fig. 12.1.3 clock f 1 output start timing (when clock f 1 output selection bit is set from 0 to 1) fig. 12.1.4 structure of oscillation circuit control registe r 0 clock 1 e notes 1: there is a possibility that the first cycle of clock 1 output is not an exact square; the shaded section may be lost. 2: this is applied when 1 is written to the clock 1 output selection bit while pin p4 2 outputs l level. the clock 1 output selection bit is set to 1. 12.1 signals required for accessing external devices C
connecting external devices 7733 group users manual 12C9 signal is stopped. clock 1 (in the microprocessor mode) note: for conditions and signal levels, refer to tables 12.1.2 and 12.1.5. value 1 is written to the signal output disable selection bit. e (note) fig. 12.1.5 relationship between setting of signal output di sable selection bit and stop timing of __ clock f 1 and e 12.1 signals required for accessing external devices
connecting external devices 7733 group users manual 12C10 12.1.10 operation of bus interface unit (biu) figures 12.1.6 and 12.1.7 show operating waveform examples of signals which are input to or output from the external when accessing external devices. these waveforms are described in relation to the basic operating waveforms. (refer to section 2.2.3 operation of bus interface unit (biu). ) (1) when fetching an instruction into an instruction queue buffer when an instruction which is next fetched resides at an even address when the external data bus is 16 bits wide, the biu fetches two bytes of the instruction at a time with waveform (a). when the external data bus is 8 bits wide, the biu fetches only one byte of the instruction with the first half of waveform (e). when an instruction which is next fetched resides at an odd address when the external data bus is 16 bits wide, the biu fetches only one byte of the instruction with waveform (d). when the external data bus is 8 bits wide, the biu fetches only one byte of the instruction with the first half of waveform (f). when branched to an odd address by executing a branch instruction or others with the 16-bit external data bus, at first, the biu fetches one byte of an instruction with waveform (d) and then fetches instructions by the two bytes with waveform (a). (2) when reading or writing data from or to memory ? i/o when accessing 16-bit data which starts from an even address, waveform (a) or (e) is applied. when accessing 16-bit data which starts from an odd address, waveform (b) or (f) is applied. a when accessing 8-bit data which resides at an even address, waveform (c) or the first half of waveform (e) is applied. ? when accessing 8-bit data which resides at an odd address, waveform (d) or the first half of waveform (f) is applied. for instructions which are affected by data length flag (m) and index register length flag (x), an operation is applied as follows: ?when m or x = 0, operation or is applied. ?when m or x = 1, operation a or ? is applied. settings of flags m and x and selection of the external data bus width do not affect each other. 12.1 signals required for accessing external devices
connecting external devices 7733 group users manual 12C11 fig. 12.1.6 operating waveform examples of signals which are input to or output from the external (1) l when external data bus is 16 bits wide (byte = l ) <16-bit data access> a 0 to a 7 address a 8 /d 8 to a 15 /d 15 data (odd) bhe e a 0 (a) access starting from even address ale a 16 /d 0 to a 23 /d 7 data (even) a 0 to a 7 a 8 /d 8 to a 15 /d 15 e (b) access starting from odd address ale address address address address address address data (odd) <8-bit data access> a 0 to a 7 a 16 /d 0 to a 23 /d 7 e (d) access to odd address ale bhe a 0 a 8 /d 8 to a 15 /d 15 a 0 to a 7 a 16 /d 0 to a 23 /d 7 e (c) access to even address ale bhe a 0 a 8 /d 8 to a 15 /d 15 bhe a 0 a 16 /d 0 to a 23 /d 7 address address data (even) address address address address address address data (even) data (odd) 12.1 signals required for accessing external devices
connecting external devices 7733 group users manual 12C12 fig. 12.1.7 operating waveform examples of signals which are input to or output from the external (2) l when external data bus is 8 bits wide (byte = h ) <8/16-bit data access> note : when 16-bit data is accessed, the low-order 8 bits of data are accessed first, and then, the high-order 8 bits are accessed. e (f) access starting from odd address ale a 0 to a 7 bhe a 0 a 8 to a 15 a 16 /d 0 to a 23 /d 7 e (e) access starting from even address ale a 0 to a 7 address bhe a 0 a 8 to a 15 a 16 /d 0 to a 23 /d 7 data 8-bit data access 16-bit data access 8-bit data access 16-bit data access address address address address address data address address address address address address data data 12.1 signals required for accessing external devices
connecting external devices 7733 group users manual 12C13 12.2 software wait 12.2 software wait the software wait facilitates access to external devices which require a long access time. there are two types of software waits: wait 0 and wait 1. the software wait is set by the wait bit (bit 2 at address 5e 16 ) and the wait selection bit (bit 0 at address 5f 16 ). (refer to table 12.2.1. ) figure 12.2.1 shows the structures of the processor mode register 0 (address 5e 16 ) and processor mode register 1 (address 5f 16 ). figure 12.2.2 shows bus timing examples when the software wait is used. the software wait is valid only for the external area. (access to the internal areas is always performed with no wait.) table 12.2.1 setting method of software wait wait bit wait selection bit software wait bus cycle 1 0 0 invalid (no wait) wait 0 wait 1 cycle of internal clock f divided by 2 (clock f 1 s cycle 5 2) cycle in the no-wait state 5 2 (clock f 1 s cycle 5 4) cycle in the no-wait state 5 1.5 (clock f 1 s cycle 5 3) 0 0 1
represents that bits 3 to 6 are not used for access control of the external area. connecting external devices 7733 group users manual 12C14 b2 b3 b4 b5 b6 b7 b1 processor mode register 1 (address 5f 16 ) b0 bit bit name function at reset 0 7 to1 wait selection bit 0 : wait 0 1 : wait 1 0 not implemented. un- defined rw rw _ bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits wait bit software reset bit interrupt priority detection time selection bits must be fixed to 0. clock f 1 output selection bit (note 2) 0 0 0 0 0 0 00: single-chip mode 01: memory expansion mode 10: microprocessor mode 11: do not select. 0: software wait is inserted when accessing external area. 1: no software wait is inserted when accessing external area. microcomputer is reset by setting this bit to 1. this bit is 0 at reading. 00: 7 cycles of f 01: 4 cycles of f 10: 2 cycles of f 11: do not select. 0: clock f 1 output is disabled. (p4 2 functions as a programmable /o port.) 1: clock f 1 output is enabled. (port p4 2 functions as a clock f 1 output pin.) 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) (note 1) notes 1: when the vcc-level voltage is applied to pin cnvss, this bit is set to 1 after reset. (at reading, this bit is always 1.) this bit is ignored in the microprocessor mode. (it may be 0 or 1.) 3: (functions of these bits are valid.) b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw wo rw rw rw rw fig. 12.2.1 structures of processor mode register 0 and pro cessor mode register 1 12.2 software wait 2:
connecting external devices 7733 group users manual 12C15 clock 1 a 0 to a 7 a 8 /d 8 to a 15 /d 15, a 16 /d 0 to a 23 /d 7 ale address data 1-bus cycle (note) e l this waveform is always applied when the internal area is a ccessed. <> a 0 to a 7 a 8 /d 8 to a 15 /d 15, a 16 /d 0 to a 23 /d 7 ale <> clock 1 a 8 /d 8 to a 15 /d 15, a 16 /d 0 to a 23 /d 7 ale data 1-bus cycle note : when the external data bus is 8 bits wide (byte = h ), operating waveform of a 8 /d 8 to a 15 /d 15 is the same as that of a 0 to a 7 . e a 0 to a 7 e data address address address address <> address address address data 1-bus cycle clock 1 (note) address address address address data data (note) fig. 12.2.2 bus timing examples when software wait is used (byte = l ). 12.2 software wait
connecting external devices 7733 group users manual 12C16 p4 2 / f 1 timers a and b, serial i/o, a-d converter, watchdog timer item state 12.3 ready function the ready function facilitates access to external devices which require a long access time. ____ by applying l level to pin rdy in the memory expansion or microprocessor mode, the microcomputer ____ enters the ready state. while pin rdy s level is l, this state is retained. table 12.3.1 lists the microcomputers state in the ready state. in the ready state, oscillation of the oscillator does not stop. therefore, the internal peripheral devices can operate even in the ready state. the ready function is valid for the internal and external areas. table 12.3.1 microcomputers state in ready state clock f 1 output selection bit *1 : bit 7 at address 5e 16 signal output disable selection bit *2 : bit 6 at address 6c 16 ____ note: when l level which was input to pin rdy is sampled at one of the following timings, this signal is not accepted. (note that f cpu is stopped at l level.) __ l when the level of signal e is h while the bus is in use (refer to in figure 12.3.1 .) l immediately before a wait generated by the software wait (refer to ? in figure 12.3.1. ) oscillation f cpu operating stopped at l level ____ retains the same state in which rdy was accepted. _____ __ __ ____ hlda , e , r/ w , bhe , ale, a 0 to a 7 , a 8 /d 8 to a 15 /d 15 , a 16 / d 0 to a 23 /d 7 , p4 3 to p4 7 , p 5 to p 8 in the memory expansion mode n when the clock f 1 output selection bit *1 = 1 outputs clock f 1 . n when the clock f 1 output selection bit = 0 ____ retains the same state in which rdy was accepted. in the microprocessor mode n when the signal output disable selection bit *2 = 1 ____ retains the same state in which rdy was accepted. n when the signal output disable selection bit = 0 outputs clock f 1 . operating 12.3 ready function
connecting external devices 7733 group users manual 12C17 12.3 ready function 12.3.1 operation in ready state ____ when l level is input to pin rdy , this signal is accepted at the falling edge of clock f 1 and the microcomputer ____ enters the ready state. the ready state can be terminated by setting pin rdy s level to h again. when ____ h level is input to pin rdy , this signal is also accepted at the falling edge of clock f 1 and the ready state is terminated. figure 12.3.1 shows timings when the ready state is accepted and terminated. refer to section 17.1 memory expansion for the way to use the ready function.
connecting external devices 7733 group users manual 12C18 <> sampling timing clock 1 cpu e rdy ale ? a bus is not in use. bus is in use. ? ready state is terminated. l level which is input to pin rdy is accepted, so that signal e is stopped at h level for 1 cycle of clock 1 (area ), and cpu is stopped at l level. l level which is input to pin rdy is not accepted, but cpu is stopped at l level. a l level which is input to pin rdy is accepted, so that signal e is stopped at l level for 1 cycle of clock 1 (area ), and cpu is stopped at l level. ? l level which is input to pin rdy is not accepted because it is sampled immediately before a wait generated by software (area ), but cpu is stopped at l level. sampling timing clock 1 cpu rdy ale <> bus is in use. sampling timing clock 1 cpu rdy ale <> bus is in use. ?? a ?? a e e fig. 12.3.1 timings when ready state is accepted and termin ated 12.3 ready function
connecting external devices 7733 group users manual 12C19 12.4 hold function when an external circuit which accesses the bus without using the central processing unit (cpu), for example dma, is used, it is necessary to generate a timing for transferring the right to use of the bus from the cpu to the external circuit. the hold function is used to generate this timing. _____ by applying l level to pin hold in the memory expansion or microprocessor mode, the microcomputer _____ enters the hold state. while pin hold s level is l, this state is retained. table 12.4.1 lists the microcomputers state in the hold state. in the hold state, oscillation of the oscillator does not stop. therefore, the internal peripheral devices can operate even in the hold state. (note that the watchdog timer stops.) table 12.4.1 microcomputers state in hold state item state operating stopped at l floating oscillation f cpu a 0 to a 7 , a 8 /d 8 to a 15 /d 15 , __ ____ a 16 /d 0 to a 23 /d 7 , r/ w , bhe outputs l level. in the memory expansion mode n when the clock f 1 output selection bit *1 = 1 outputs clock f 1 . n when the clock f 1 output selection bit = 0 _____ retains the same state in which hold was accepted. in the microprocessor mode n when the signal output disable selection bit *2 = 1 _____ retains the same state in which hold was accepted. n when the signal output disable selection bit = 0 outputs clock f 1 . _____ retains the same state in which hold was accepted. operating stopped clock f 1 output selection bit *1 : bit 7 at address 5e 16 signal output disable selection bit *2 : bit 6 at address 6c 16 _____ hlda , ale p4 2 / f 1 p4 3 to p4 7 , p5 to p8 timers a and b, serial i/o, a-d converter watchdog timer 12.4 hold function
connecting external devices 7733 group users manual 12C20 12.4.1 operation in hold state _____ when l level is input to pin hold while the bus is not in use, this signal is accepted at the falling edge _____ of clock f 1 in each bus cycle. when l level is input to pin hold while the bus is in use, this signal is accepted at the last falling edge of clock f 1 . (refer to figures 12.4.2 to 12.4.6 .) when word data which starts from an odd address is accessed by the two bus cycles , determination is performed only in the second bus cycle. (refer to figure 12.4.1. ) _____ when l level which was input to pin hold is accepted, f cpu is stopped at the next rising edge of clock _____ f 1 . at this time, pin hlda outputs l level, and so the external is informed that the microcomputer is in _____ __ ____ the hold state. after one cycle of clock f 1 has passed since pin hlda s level becomes l, pins r/ w , bhe and the external bus enter the floating state. _____ the hold state can be terminated by setting pin hold s level to h again. when h level is input to pin _____ _____ hold , the signal is accepted at the falling edge of clock f 1 . when h level which was input to pin hold _____ is accepted, pin hlda s level goes from l to h. and then, the hold state is t erminated after one cycle of clock f 1 has passed. figures 12.4.2 to 12.4.6 show the timing when the hold state is accepted and terminated. _____ h in the ready state, determination of pin hold s input level is not performed. a clock 1 ale at reading at writing e l determination timing of pin hold s input level a not determined determined word data is accessed by the two bus cycles. (in this case, no wait) a a ww fig.12.4.1 determination when word data which starts from odd address i s accessed by the two bus cycles 12.4 hold function
connecting external devices 7733 group users manual 12C21 fig. 12.4.2 timing when hold state is accepted and terminate d (1) external data bus data length external data bus width software wait 16 8, 16 no wait, not in use l state when l level is input to pin hold wait 1, wait 0 8, 16 8 ale e external address bus/ external data bus hlda hold external address bus address b ? 1 5 1 ? 1 5 1 sampling timing bus is in use. bus is not in use. note: the same operation is performed independent of the software wait (no wait, wait 0, or wait 1). this diagram shows the operation when no wait is s elected. because the bus is not in use, the address which was output immediately before is output again, instead of a new address. r/w clock 1 address a data <> bhe floating address a floating floating bus is in use. hold state 12.4 hold function
connecting external devices 7733 group users manual 12C22 external data bus data length 8 16 8,16 16 (when accessed starting from even address) no wait in use ?? state when l level is input to pin hold external data bus width software wait ale e hlda hold r/w address a 1 5 1 1 5 1 hold state sampling timing bus is in use. <> when l level which is input to pin hold is accepted, the address which was output immediately before is output again, instead of a new add ress. external address bus/ external data bus external address bus clock 1 data floating bhe address a floating address b bus is in use. floating fig. 12.4.3 timing when hold state is accepted and terminate d (2) 12.4 hold function
connecting external devices 7733 group users manual 12C23 when l level which is input to pin hold is accepted, the address which was output immediately before is output again, instead of a new add ress. address a external address bus/ external data bus external data bus data length external data bus width software wait 8 16 8,16 16 (when accessed starting from even address) wait 1 in use l state when l level is input to pin hold ale e hlda hold r/w address a address b 1 5 1 1 5 1 hold state sampling timing bus is in use. <> external address bus clock 1 data floating floating floating bus is in use. bhe fig. 12.4.4 timing when hold state is accepted and terminate d (3) 12.4 hold function
connecting external devices 7733 group users manual 12C24 12.4 hold function when l level which is input to pin hold is accepted, the address which was output immediately before is output again, instead of a new add ress. external data bus data length external data bus width software wait 8 16 8,16 16 (when accessed starting from even address) wait 0 in use l state when l level is input to pin hold ale e hlda hold r/w address a address b 1 5 1 1 5 1 hold state data sampling timing bus is in use. <> external address bus/ external data bus external address bus clock 1 address a floating floating bus is in use. floating bhe fig. 12.4.5 timing when hold state is accepted and terminate d (4)
connecting external devices 7733 group users manual 12C25 when l level which is input to pin hold is accepted, the address which was output immediately before is output again, instead of a new add ress. sampling is not performed until 16-bit data input/output is finished. ( l level input to pin hold is not accepted.) external address bus/ external data bus ale e hlda hold r/w address 1 5 1 1 5 1 hold state not sampled external data bus data length external data bus width software wait 16 8 16 (when accessed starting from odd address) no wait in use l state when l level is input to pin hold sampling timing bus is in use. <> external address bus clock 1 data high-order address floating floating floating bus is in use. bhe data low-order address 12.4 hold function fig. 12.4.6 timing when hold state is accepted and terminate d (5)
connecting external devices 7733 group users manual 12C26 memo 12.4 hold function
chapter 13 chapter 13 reset 13.1 hardware reset 13.2 software reset
reset 7733 group users manual 13C2 reset a? h l 4 to 5 cycles of internal clock 2 s or more internal processing sequence after reset program executed 13.1 hardware reset how to reset the microcomputer is described below. there are two methods to reset the microcomputer: hardware reset and software reset. 13.1 hardware reset when the power source voltage satisfies the recommended oper ating conditions, the microcomputer is reset ______ by applying l level to pin reset . (this is called hardware reset.) figure 13.1.1 shows an example of hardware reset timing. the microcomputers operation during periods to ? is described below. ______ after l level is applied to pin reset , pins are initialized within a period of several ten ns. (r efer to table 13.1.1. ) ______ ______ while pin reset is at l level or within a period of 4 to 5 cycles of inte rnal clock f after pin reset s level changes from l to h, the central processing unit ( cpu) and sfr area are initialized. at this time, the contents of the internal ram area is undefined (except t he cases where the stop or wait mode is terminated.). refer to figures 13.1.2 to 13.1.6. a after , internal processing sequence after reset is performed. r efer to figure 13.1.7. ? a program is executed beginning with the address set in the reset vector addresses (addresses fffe 16 and ffff 16 ). fig. 13.1.1 example of hardware reset timing (when main cloc k is stably supplied.)
reset 7733 group users manual 13C3 13.1 hardware reset mask rom version built-in prom version external rom version pin cnv ss s level v ss or v cc v ss v cc v cc pin (port) name p0 to p8 _ e p0 to p8 _ e p0, p1, p3 to p8 p2 _ e a 0 to a 7 , ____ a 8 /d 8 to a 23 /d 7 , bhe __ _____ _ r/w , hlda , e , ale p4 to p8 pin state floating h level is output. floating h level is output. floating ?floating when h level is applied to both or one of pins p5 1 and p5 2 ?h or l level is output when l level is applied to both of pins p5 1 and p5 2 . h level is output. undefined value is output. h level is output. l level is output. floating 13.1.1 pin state ______ table 13.1.1 lists the pin state while pin reset is at l level. ______ table 13.1.1 pin state while pin reset is at l level
reset 7733 group users manual 13C4 13.1 hardware reset 13.1.2 state of cpu, sfr area, and internal ram area figure 13.1.2 shows the state of the cpu registers immediate ly after reset. figures 13.1.3 to 13.1.6 show the state of the sfr area and internal ram area immediately after reset. fig. 13.1.2 state of cpu registers immediately after reset processor status register (ps) 0 00 0 00 0 0 00 0 1 b7 b0 b15 b8 nv mx d iz c ipl ? ?? ? 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : nothing is allocated. always 0 at reading contents of address fffe 16 contents of address ffff 16 00 16 00 16 direct page register (dpr) b7 b0 b15 b8 program counter (pc) b7 b0 b15 b8 program bank register (pg) b7 b0 data bank register (dt) b7 b0 0 register name state immediately after reset 00 16 00 16
reset 7733 group users manual 13C5 13.1 hardware reset fig. 13.1.3 state of sfr area and internal ram area immediately after reset (1) : ??immediately after reset. : ??immediately after reset. : undefined immediately after reset. 0 1 ? : always ??at reading 0 0 : always undefined at reading : ??immediately after reset. must be fixed to ?. 10 16 11 16 12 16 13 16 port p8 direction register 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 address port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register a-d control register 0 a-d control register 1 port p0 register port p1 register port p2 register port p3 register port p0 direction register port p1 direction register port p2 direction register port p3 direction register register name access characteristics state immediately after reset rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 00 16 00 16 ? ? 00 16 00 16 00 16 0000 00000000 00 16 0 0 000 ? 00 11 b7 b0 b7 b0 : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : not implemented. it is impossible to read the bit state. the written value becomes invalid. rw ro wo n sfr area (addresses 0 16 to 7f 16 ) rw ? ? ? ? ? 00 16 ? ? ? ] do not write data to addresses 1c 16 and 1d 16 . abbreviations and symbols which represent access characteristics rw rw ?? 0 ? ??? ? 00 16 ? ? ? ? ? (reserved area) ] (reserved area) ] ? ? ? ? ? ?
reset 7733 group users manual 13C6 13.1 hardware reset fig. 13.1.4 state of sfr area and internal ram area immediately after reset (2) uart0 transmit/receive control register 0 uart0 transmit/receive mode register uart0 baud rate register uart0 transmission buffer register uart1 receive buffer register register name uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register uart1 transmission buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 30 16 31 16 32 16 33 16 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 28 16 29 16 2b 16 2c 16 2d 16 2e 16 2f 16 2a 16 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 3f 16 address access characteristics rw wo wo ro ro b7 b0 wo rw ro ro ro rw rw ro ro rw wo wo wo rw ro ro ro rw rw state immediately after reset 0 01000 00 16 0 000 00 0 ? b7 b0 00 16 0000 0 0 1 0 0000000 0 01000 00000010 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a-d register 5 a-d register 1 a-d register 3 a-d register 2 a-d register 4 a-d register 0 a-d register 6 a-d register 7 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro rw rw 00 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
reset 7733 group users manual 13C7 timer b2 register 40 16 41 16 42 16 43 16 44 16 45 16 46 16 47 16 48 16 49 16 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5c 16 5d 16 5e 16 5f 16 4b 16 4c 16 4d 16 4e 16 4f 16 4a 16 address timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register processor mode register 0 one-shot start flag timer a0 register up-down flag timer a1 register register name count start flag timer a1 mode register timer a2 mode register timer a3 mode register timer b0 mode register timer b1 mode register timer b2 mode register access characteristics wo rw b7 b0 rw rw rw rw rw rw rw wo rw state immediately after reset 00 16 00 16 00 16 00 16 ? 00 16 b7 b0 00 16 00 0 000 00 0 0 0 0 wo rw rw rw timer a0 mode register timer a4 mode register rw rw rw 0000 0 0 0 0 0000 0 0 00000 00 0 0 0 0 0 rw rw ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 processor mode register 10 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 1 ] 2 ] 2 ] 2 ] 3 ] 3 ] 1 access characteristics at addresses 46 16 to 55 16 vary according to the timer? operating mode. (refer to chapters ?. timer a and ?. timer b. ) ] 2 access characteristics for bit 5 at addresses 5b 16 to 5d 16 vary according to the timer b? operating mode. (refer to chapter ?. timer b. ) ] 3 access characteristics for bit 1 at address 5e 16 and its state immediately after reset vary according to the voltage level applied to pin cnv ss . (refer to section ?.5 processor modes. ) 13.1 hardware reset fig. 13.1.5 state of sfr area and internal ram area immediately after reset (3)
reset 7733 group users manual 13C8 0 ro uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address oscillation circuit control register 0 serial transmit control register a-d / uart2 trans./rece. interrupt control register uart0 transmission interrupt control register uart1 transmission interrupt control register int 2 /key input interrupt control register watchdog timer frequency selection flag register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw( ] 2) rw rw rw rw b7 b0 wo rw rw rw rw rw rw rw rw rw rw state immediately after reset ? ? ? ? ? 0 00 0 ? 0 ? ( ] 1) b7 b0 ? 0 0 0 0 0 00 0 0 0 0 0 00 0 00 0 port function control register uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register rw rw wo rw rw rw 00 0 0 0 1 00 0 0 00 0 0 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 0 0 0 0 00 0 0 00 0 0 00 0 ? ? ? 0 0 0 00 0 00 0 00 0 value fff 16 is set to the watchdog timer. (refer to chapter 10. watchdog timer. ) for access characteristics at address 6c 16 , also refer to figure 14.3.2. state immediately after reset for bit 3 at address 6f 16 vary according to the microcomputer. (refer to figure 14.3.3. ) do not write data to address 62 16 . n internal ram area (m37733mhbxxxfp: addresses 80 16 to fff 16 ) at hardware reset (not including the case where the stop or wait mode is te rminated)...undefined. at software reset...retains the state immediately before res et . when the stop or wait mode is terminated (when hardware reset is applied)...retains the state imme diately before the stp or wit in struction was executed. ? rw ] 3 00 0 ] 1 ] 2 ] 3 ] 4 (reserved area) ] 4 memory allocation control register uart2 transmit/receive mode register uart2 baud rate register (brg2) uart2 transmission buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register oscillation circuit control register 1 rw ? 0 00 0 rw ? 00 0 000 0 wo wo wo rw ro 1 00 0 rw ro rw ro 00 0 0 0 1 0 0 ro 0 0 0 00 0 ? rw ? ? 0 00 0 0 00 0 ? 0 13.1 hardware reset fig. 13.1.6 state of sfr area and internal ram area immediat ely after reset (4)
reset 7733 group users manual 13C9 (1) single-chip and memory expansion modes (2) microprocessor mode cpu a p a h a l data e 00 16 fffe 16 ad h , ad l 00 16 next op-code ipl, vector address internal clock cpu a p a h a l data e internal clock 0000 16 ad h , ad l unused 0000 16 fffe 16 ad h , ad l ad h , ad l unused next op-code ipl, vector address cpu : cpus standard clock a p : high-order 8 bits of cpu address bus a h a l : low-order 16 bits of cpu address bus data : cpu data bus ad h , ad l : contents of reset vector addresses (addresses fffe 16 and ffff 16 ) unused unused 13.1.3 internal processing sequence after a reset figure 13.1.7 shows the internal processing sequence after r eset. 13.1 hardware reset fig. 13.1.7 internal processing sequence after reset
reset 7733 group users manual 13C10 0v 0v v cc reset powered on here 4.5v 0.9v note: for the low voltage version, refer to figure 18.3.1 . ______ 13.1.4 time required for applying l level to pin reset ______ time required for applying l level to pin reset varies according to the main clock oscillation circuits state. n the case where an oscillator is stably oscillating or an external clock is stably input from pin x in apply l level for 2 m s or more. n the case where an oscillator is not stably oscillating (including the cases where power-on reset is applied and where the microcomputer operates in the stop mode) apply l level until oscillation is stabilized. the time required for stabilizing oscillation varies according to the oscillator. for details, contact with the oscillator manufacturer. figure 13.1.8 shows power-on reset conditions. figure 13.1.9 shows an example of a power-on reset circuit. h for the stop mode, refer to chapter 11. stop mode and wait modes. for clocks, refer to chapter 14. clock generating circuit. 13.1 hardware reset fig. 13.1.8 power-on reset conditions
reset 7733 group users manual 13C11 1 v cc in out gnd delay capacity reset v cc v ss 47 w sw c d gnd 3 25 5 v m51957al m37733mhbxxxfp 27 k w 10 k w 4 h delay time td is about 11 ms when c d = 0.033 m f. t d ? 0.34 5 c d [ m s], c d : [ pf ] note: for the low voltage version, refer to figure 18.3.2 . 13.1 hardware reset fig. 13.1.9 example of power-on reset circuit
represents that bits 0 to 2 and bits 4 to 7 are not used for software reset. functions as a output pin.) reset 7733 group users manual 13C12 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits wait bit software reset bit must be fixed to 0. clock 1 output selection bit (note 2) 0 0 0 0 0 0 0 0: single-chip mode 0 1: memory expansion mode 1 0: microprocessor mode 1 1: do not select. 0: software wait is inserted when accessing external area. 1: no software wait is inserted when accessing external area. microcomputer is reset by setting this bit to 1. this bit is 0 at reading. 0 0: 7 cycles of 0 1: 4 cycles of 1 0: 2 cycles of 1 1: do not select. 0: clock 1 output is disabled. (p4 programmable i/o port.) 1: clock 1 output is enabled. (port p4 2 functions as a clock 1 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) (note 1) notes 1: when the vcc-level voltage is applied to pin cnvss, this bit is set to 1 after reset. (at reading, this bit is always 1.) this bit is ignored in the microprocessor mode. (it may be 0 or 1.) 3: b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw wo rw rw rw rw interrupt priority detection time selection bits 13.2 software reset 13.2 software reset when the power source voltage satisfies the recommended oper ating conditions and the main clock is stably supplied ( note ), the microcomputer is reset by writing 1 to the software reset bit (bit 3 at address 5e 16 ). (this is called software reset.) in this case, the microco mputer initializes pins, cpu, and sfr area as in the case of a hardware reset. however, the microcomputer ret ains the contents of the internal ram area. (refer to table 13.1.1 and figures 13.1.2. to 13.1.6. ) after completing initialization, the microcomputer performs internal processing sequence after reset. (refer to figure 13.1.7. ) then, a program is executed beginning with the address set in the reset vector addresses (addresses fffe 16 and ffff 16 ). note: this means when a oscillator is stably oscillating or when an external clock is stably input from pin x in . for clocks, refer to chapter 14. clock generating circuit. fig. 13.2.1 structure of processor mode register 0 2 2:
chapter 14 chapter 14 clock generating circuit 14.1 overview 14.2 oscillation circuit example 14.3 clock control
clock generating circuit 7733 group users manual 14C2 14.1 overview quartz-crystal oscillator pins x cin and x cout not available stopped (note 1) ? a clock which is externally generated can be input. ? sub clock can be input to external devices. (refer to 14.3.1. ) usage of clock resonator/oscillator which can be connected pins which are connected to resonator/oscillator oscillation stop/restart (note 2) oscillators state just after reset remarks ? operating clock source of cpu ? operating clock source of internal peripheral devices ? operating clock source of clock timer ? ceramic resonator ? quartz-crystal oscillator pins x in and x out available operating a clock which is externally generated can be input. main-clock oscillation circuit sub-clock oscillation circuit notes 1: immediately after reset, pins x cin and x cout function as ports p7 7 and p7 6 , respectively. the oscillator starts operating when pins function is switched by the port-x c selection bit (bit 4 at address 6c 16 ). 2: whether oscillation is stopped or restarted is set by the main clock stop bit (bit 2 at address 6c 16 ). in the main-clock/sub-clock oscillation circuit, oscillation can be stopped by the stp instruction; oscillation can be restarted by an interrupt request generated. (refer to figure 14.3.9. ) the clock generating circuit is described below. 14.1 overview this clock generating circuit includes two oscillation circuits, which are main-clock and sub-clock oscillation circuits. each of the main and sub clocks can be used as an operating clock for the cpu, internal peripheral devices, and clock timer. table 14.1.1 main-clock and sub-clock oscillation circuits
clock generating circuit 7733 group users manual 14C3 m37733mhbxxxfp externally generated clock open x in x out v cc v ss m37733mhbxxxfp x in x out r f c in c out r d 14.2 oscillation circuit example 14.2 oscillation circuit example main-clock and sub-clock oscillation circuits examples are described below. fig. 14.2.1 connection example of resonator/oscillator fig. 14.2.2 externally generated clock input example 14.2.1 main-clock oscillation circuit example to the main-clock oscillation circuit, a resonator/ oscillator can be connected, or a clock which is externally generated can be input. (1) connection example of resonator/oscillator figure 14.2.1 shows an example where pins x in and x out connect across a ceramic resonator/quartz-crystal oscillator. circuit constants such as rf, rd, c in , and c out (shown in figure 14.2.1) depend on the resonator/oscillator. these values shall be set to the resonator/oscillator manufacturers recommended values. (2) input example of clock which is externally generated figure 14.2.2 shows an input example of a clock which is externally generated. when inputting a main clock from an external circuit, set 1 to bit 1 of the main-clock oscillation circuit control register 1. (refer to figure 14.3.3. ) by this setting, the main-clock oscillation circuit stops operating and power consumption can be held down. note that this bit has a function to select return conditions from the stop mode. (refer to chapter 11. stop and wait modes. ) furthermore, when writing to the oscillation circuit control register 1, follow the procedure shown in figure 14.3.4. when inputting a main clock from an external circuit, that the external clock must be input from pin x in , and pin x out must be left open.
clock generating circuit 7733 group users manual 14C4 m37733mhbxxxfp externally generated clock x cin p7 6 /an 6 v cc v ss external circuit m37733mhbxxxfp x cin x cout r cf c cin c cout r cd 14.2 oscillation circuit example fig. 14.2.3 connection example of quartz-crystal oscillator fig. 14.2.4 externally generated clock input example 14.2.2 sub-clock oscillation circuit example to the sub-clock oscillation circuit, an oscillator can be connected, or a clock which is externally generated can be input. (1) connection example of oscillator when using an oscillator, connect a quartz- crystal oscillator between pins x cin and x cout . (a ceramic resonator cannot be connected.) figure 14.2.3 shows a quartz-crystal oscillator connection example. circuit constants such as rcf, rcd, c cin , and c cout (shown in figure 14.2.3) depend on the oscillator. these values shall be set to the oscillator manufacturers recommended values. when connecting an oscillator to the sub-clock oscillation circuit, set the port-xc selection bit (bit 4 at address 6c 16 ) to 1 and the sub clock external input selection bit (bit 2 at address 6f 16 ) to 0. note that the sub clock external input selection bit has a function to select return conditions from the stop mode. (refer to chapter 11. stop and wait modes. ) (2) input example of clock which is externally generated figure 14.2.4 shows an input example of a clock which is generated in an external circuit. when inputting a sub clock from an external circuit, be sure to set the sub clock external input selection bit to 1, and then, select pins x cin and x cout by the port-xc selection bit. in this case, an externally generated clock is input to pin x in , and pin x out functions as pin p7 6 /an 6 . note that the sub clock external input selection bit has a function to select return conditions from the stop mode. (refer to chapter 11. stop and wait modes. ) if the sub-clock output selection bit (bit 1 at address 6d 16 ) is set to 1 when the port-xc selection bit = 1 (note) , sub clock f sub is output from port p6 7 . accordingly, a 32-khz sub clock can be supplied to external gates. note: at this time, a sub clock is used.
clock genera ting circuit 7733 group users manual 14C5 14.3 clock control figure 14.3.1 shows the clock generating circuit block diagr am. 14.3 clock control fig. 14.3.1 clock generating circuit block diagram 1 1 0 0 1/8 0 cm 3 cm 4 1 1 cmi: bit i at address 6c 16 (refer to figure 11.2.2. ) cci: bit i at address 6f 16 (refer to figure 11.2.3. ) system clock s r q stp instruction 1/4 1/2 1/2 1/8 1/2 f 64 f 512 f 2 f 8 f 16 f 32 internal clock q r s wit instruction s r q reset watchdog timer frequency selection flag 1 1 0 0 wdc 12-bit watchdog timer 1/2 x in x out p7 7 /an 7 /x cin p7 6 /an 6 /x cout cc 1 cm 3 cm 5 cm 2 cm 3 cc 1 1 0 cm 4 cc 2 1 0 1 0 p6 7 /tb2 in / sub 1 0 (port latch) timer b2 (event counter mode) (clock timer) (clock prescaler) 1/32 1 0 f c32 cm 4 pc 1 main clock sub clock (oscillation circuit control register 0: address 6c 16 ) cm 2 : main clock stop bit cm 3 : system clock selection bit cm 4 : port-xc selection bit cm 5 : system clock stop bit at wait state (oscillation circuit control register 1: address 6f 16 ) cc 0 : main clock division selection bit cc 1 : main clock external input selection bit cc 2 : sub clock external input selection bit (port function control register: address 6d 16 ) pc 1 : sub-clock output selection bit/timer b2 clock source selec tion bit cm 4 pc 1 1 cc 0 cm 3 cm 4 cm 3 0 interrupt request interrupt disable flag switch represented by is controlled by a signal repre sented by . cm 4 cc 2 cm 4 stp instruction
clock generating circuit 7733 group users manual 14C6 14.3 clock control 14.3.1 clock generated in clock generating circuit (1) system clock it is the clock source of the system clock divided by 2, internal clock f , clock f 1 , and clocks f 2 to f 512 . (refer to figure 14.3.1. ) each of the main clock, main clock divided by 8, and the sub clock can be selected as the system clock by the system clock selection bit (bit 3 at address 6c 16 ). table 14.3.1 lists clock combinations of the system clock, internal clock f , f 1 , and f 2 . 0 1 0 1 port-xc selection bit (bit 4 at 6c16) system clock selection bit (bit 3 at 6c 16 ) main clock division selection bit (bit 0 at 6c 16 ) system clock table 14.3.1 clock combinations of system clock, internal clock f , f 1 , and f 2 internal clock f , f 1 , f 2 (sub clock is not used.) main clock main clock main clock divided by 8 main clock divided by 8 main clock main clock sub clock 0 1 0 1 0 1 0 1 main clock divided by 2 main clock main clock divided by 16 main clock divided by 8 main clock divided by 2 main clock sub clock divided by 2 (sub clock is used.) 0 1 (2) main clock it is the clock supplied by the main-clock oscillation circuit. this clock is selected as the system clock immediately after reset. after the sub clock is selected as the system clock, the main-clock supply is stopped/restarted by the main clock stop bit (bits 2 at address 6c 16 ). (refer to figures 14.3.6 and 14.3.7. ) by stopping the main-clock supply, power consumption can be held down. figure 14.3.5 shows the clock f 2 state transition when a sub clock is not used because the port-xc selection bit (bit 4 at address 6c 16 ) = 0. during reset and till after reset state is terminated, the main clock divided by 2 is selected as clock f 2 . if the system clock selection bit (bit 3 at address 6c 16 ) is set to 1, at this time, the main clock divided by 16 is selected as clock f 2 , and the clock frequency which is supplied to the cpu and peripheral devices becomes 1/8. though this slow down the processing speed, current consumption is held down. furthermore, by setting 1 to both of the main clock division selection bit (bit 0 at address 6f 16 ) and system clock selection bit, the main clock divided by 8 is selected as clock f 2 . when the port-xc selection bit = 0, clock f c32 , which is the main clock divided by 32, is connected as the timer b2s count source if the timer b2 clock source selection bit (bit 1 at address 6d 16 ) = 1 and timer b2 is used as a clock timer. by this, even when the main clocks ratio is changed, the clock timer can use the same clock source. (refer to figure 14.3.1. )
clock generating circuit 7733 group users manual 14C7 14.3 clock control (3) sub clock it is the clock supplied by the sub-clock oscillation circuit. the sub-clock supply is stopped immediately after reset ( note ). when the port-xc selection bit (bit 4 at address 6c 16 ) is set to 1, the sub-clock oscillation circuit starts operating, in other words, oscillation starts or an external clock is input. furthermore, in this case, f c32 (sub clock divided by 32) is connected. (refer to section 7.6 clock timer. ) furthermore, a sub clock can be the system clock by specifying the system clock selection bit after the oscillation is stabilized. (refer to figure 14.3.6. ) the x cout pins drivability can be lowered by the x cout drivability selection bit (bit 0 at address 6c 16 ) after oscillation of the sub-clock oscillation circuit is stabilized. by lowering the x cout pins drivability, power consumption is held down. when a sub clock is used, in other words, bit 4 at address 6c 16 = 1, sub clock f sub is output from pin p6 7 /tb2 in / f sub if the sub-clock output selection bit (bit 1 at address 6d 16 ) is set to 1. note: at this time, the oscillator which is connected to the sub-clock oscillation circuit stops operating, and pins x cin and x cout function as ports p7 6 and p7 7 . (4) internal clock f it is the cpus operating clock source, and its clock source is the system clock. (5) clocks f 2 to f 512 each of them is the internal peripheral devices operating clock, and its clock source is the system clock. (6) clock f 1 it is output to external circuits and has the same period as internal clock f , and its clock source is the system clock. (7) f c32 it is the main clock/sub clock divided by 32 (refer to figure 14.3.1. ) and the count source of the clock timer. (refer to 7.6 clock timer. ) (8) sub clock f sub sub clock f sub is output from port p6 7 if the sub clock output selection bit (bit 1 at address 6d 16 ) is set to 1 when the port xc selection bit = 1, in other words, when the sub clock is used. therefore, the 32-khz sub clock can be supplied to the external gate.
clock genera ting circuit 7733 group user? manual 14? bit bit name functions at reset rw 0 1 2 3 4 5 6 7 x cout drivability selection bit main clock stop bit system clock selection bit port-xc selection bit not implemented. 0 0 0 0 un- defined 0 0: drivability ?ow 1: drivability ?igh when the port-xc selection bit = ?, 0: main clock 1: main clock divided by 8 when the port-xc selection bit = ?, 0: main clock 1: sub clock 1 un- defined oscillation circuit control register 0 (address 6c 16 ) b1 b0 b2 b3 b4 b5 b6 b7 notes 0: main clock oscillation or external clock input is available. 1: main clock oscillation or external clock input is stopped. rw rw not implemented. rw ( note 1 ) 0: operate as i/o ports (p7 7 , p7 6 ). 1: operate as pins x cin and x cout . rw ( notes 2 and 3 ) rw ( note 2 ) system clock stop bit at wait state (note 4) 0: output is enabled. 1: output is disabled. (refer to tables 12.1.2 and 12.1.5 ) 0: operates in the wait mode. 1: stopped in the wait mode. signal output disable selection bit rw ( note 1 ) 1: nothing can be written to this bit after reset. writing to this bit is enabled when the port-xc selection bit = ?.? 2: when selecting the sub clock as the system clock, set bit 3 to ??after setting bit 4 to ?. if the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to ? . 3: although this bit can be set to ?,?it cannot be cleared t o ??after this bit is once set to ?. 4: when setting the system clock stop bit at wait state to ?, ?perform it immediately before the wit instruction is executed. furthermore, clear this bit to ? immediately after the wait mode is terminated. 14.3 clock control fig. 14.3.2 structure of oscillation circuit control registe r 0
clock genera ting circuit 7733 group users manual 14C9 write data 01010101 2 . ( ldm instruction) ? when writing to bits 0 to 3 write data 00001xxx 2 . ( ldm instruction) next instruction (b3 in figure 14.3.3) (b2 to b0 in figure 14.3.3) bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to 1 in the one time prom and eprom versions (notes 1 and 2) . must be fixed to 0 (note 2) . clock prescaler reset bit 0 0 0 0 undefined 0 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input from the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown in figure 14.3.4. by writing 1 to this bit, clock prescaler is initialized. rw 1 (note 3) 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. ignored in the mask rom and external rom versions. 2: the case where data 01010101 2 is written with the procedure shown in figure 14.3.4 is not included. 3: in the 7735 group, fix this bit to 0. 4: represents that bits 3 to 7 are not used for the cloc k generating circuit (note 1) (note 1) (note 1) 14.3 clock control fig. 14.3.3 structure of oscillation circuit control registe r 1 fig. 14.3.4 procedure for writing data to oscillation circui t control register 1
clock genera ting circuit 7733 group users manual 14C10 14.3 clock control fig. 14.3.5 clock f2 state transition (when sub clock is not used) f 2 = f(x in )/2 f 2 = f(x in )/16 f 2 = f(x in ) f 2 = f(x in )/8 cc 0 = 1 cc 0 = 0 cc 0 = 1 cc 0 = 0 cm 3 = 0 cm 3 = 1 cm 3 = 1 cm 3 = 0 (note 1) (note 2) notes 1: f 2 = f(x in )/2 represents that clock f 2 is the main clock divided by 2. 2: f 2 = f(x in ) represents that clock f 2 is the main clock not divided. reset cc 0 : main clock division selection bit cm 3 : system clock selection bit cm 4 : port-xc selection bit ? when the sub clock is not used (cm 4 = 0 )
clock generating circuit 7733 group users manual 14C11 14.3.2 system clock switching procedure figures 14.3.6 to 14.3.8 show the system clock switching procedure. 14.3 clock control fig. 14.3.6 system clock switching procedure (1) state of bits 4 to 1 of the oscillation circuit control register 0 when switching the system clock stopped operating operating port-xc selection bit (bit 4) system clock selection bit (bit 3) main clock stop bit (bit 2) (sub-clock oscillation circuit: oscillating) (main clock) (sub clock) (main clock) (stopped) (oscillating) ab ? ? ? ? ? ? system clock main clock sub clock main clock (main-clock oscillation circuit: oscillating) oscillation of the main-clock oscillation circuit oscillation stabilizing time stopped operating oscillation of the sub-clock oscillation circuit oscillation stabilizing time notes 1: before selecting the sub clock, make sure that oscillation of the sub clock is fully stabilized after oscillation starts. 2: before selecting the main clock, make sure that oscillation of the main clock is fully stabilized after oscillation restarts. (note 1) (note 2)
clock generating circuit 7733 group users manual 14C12 14.3 clock control fig. 14.3.7 system clock switching procedure (2) system clock switching procedure in order to stop the main clock supply when oscillator connected to the sub-clock oscillation circuit stops operating. (refer to ??in figure 14.3.6. ) b7 b0 operation start of the sub-clock oscillation circuit port-x c selection bit 1: function as pins x cin and x cout : oscillation circuit control register 0 (address 6c 16 ) 1 0 10 b7 b0 system clock switching : oscillation circuit control register 0 (address 6c 16 ) system clock selection bit 1: sub clock 0 11 b7 b0 stop of the the main-clock supply : oscillation circuit control register 0 (address 6c 16 ) main clock stop bit 1: stopped 1 11 (waiting for oscillation stabilized in the sub-clock oscillation circuit)
clock generating circuit 7733 group users manual 14C13 14.3 clock control fig. 14.3.8 system clock switching procedure (3) (waiting for oscillation stabilized in the main-clock oscillation circuit) system clock switching system clock selection bit 0: main clock : oscillation circuit control register 0 (address 6c 16 ) b7 b0 0 10 operation start of the main-clock oscillation circuit b7 b0 main clock stop bit 0: oscillator operates (or clock which is externally generated is input). : oscillation circuit control register 0 (address 6c 16 ) 0 11 system clock switching procedure in order to select the main clock as the system clock when the main clock supply stops. (refer to ??in figure 14.3.6. ) 1
clock generating circuit 7733 group user? manual 14?4 14.3.3 clock transition figure 14.3.9 shows the clock transition. 14.3 clock control fig. 14.3.9 clock transition main-clock oscillation circuit: stopped sub-clock oscillation circuit: oscillating system clock: sub clock main-clock oscillation circuit: oscillating sub-clock oscillation circuit: oscillating system clock: sub clock main-clock oscillation circuit: oscillating sub-clock oscillation circuit: oscillating system clock: main clock main-clock oscillation circuit: stopped sub-clock oscillation circuit: oscillating f 2 ?f 512 (note 2) internal clock f : stopped main-clock oscillation circuit: oscillating sub-clock oscillation circuit: oscillating f 2 ?f 512 (note 2) internal clock f : stopped main-clock oscillation circuit: oscillating sub-clock oscillation circuit: oscillating f 2 ?f 512 (note 2) internal clock f : stopped wait mode main-clock oscillation circuit: oscillating sub-clock oscillation circuit: stopped f 2 ?f 512 (note 2) internal clock f : stopped main-clock oscillation circuit: oscillating sub-clock oscillation circuit: stopped system clock: main clock wit instruction interrupt request generated port-xc selection bit: ? stp instruction reset system clock selection bit: ?? (note 1) system clock selection bit: ?? (note 1) main clock stop bit: ? stop mode main clock stop bit: ? wit instruction wit instruction wit instruction stp instruction stp instruction main-clock oscillation circuit: stopped sub-clock oscillation circuit: stopped system clock: stopped main-clock oscillation circuit: stopped sub-clock oscillation circuit: stopped system clock: stopped main-clock oscillation circuit: stopped sub-clock oscillation circuit: stopped system clock: stopped interrupt request generated interrupt request generated interrupt request generated interrupt request generated interrupt request generated interrupt request generated h for the stop and wait modes, refer to chapter ?1. stop and wait modes. notes 1: before selecting the system clock, make sure that operation of the oscillator is fully stabilized. additionally, genera te oscillation stabilizing time by software. 2: in the wait mode, whether clocks f 2 to f 512 are supplied or stopped can be specified by the system cloc k stop bit at wait state. stp instruction interrupt request generated main-clock oscillation circuit: stopped sub-clock oscillation circuit: stopped system clock: stopped
clock generating circuit 7733 group users manual 14C15 14.3 clock control 14.3.4 clock prescaler reset the clock prescaler, which divides a sub clock by 32, is reset by writing 1 to the clock prescaler reset bit (bit 7 at address 6f 16 ). by this function, the count source (f c32 ) error immediately after the clock timer starts counting can be held down. figure 14.3.10 shows the operation timing of the clock prescaler and timer b2. figure 14.3.10 operation timing of clock prescaler and timer b2 clock prescaler reset bit write pulse x cin clock timer clock source f c32 timer b2 count value timer b2 count start flag x cin divided by 31 (note) n (set value) n? the above is applied when the main clock is selected as the system clock, in other words, when the system clock selection bit (cm 3 ) = ?. note: only in this period, x cin divided by 31 is selected. after this period, x cin divided by 32 is selected. x cin divided by 32
clock generating circuit 7733 group users manual 14C16 memo 14.3 clock control
chapter 15 chapter 15 electrical characteristics 15.1 absolute maximum ratings 15.2 recommended operating conditions 15.3 electrical characteristics 15.4 a-d converter characteristics 15.5 internal peripheral devices 15.6 ready and hold 15.7 single-chip mode 15.8 memory expansion mode and microprocessor mode : with no wait 15.9 memory expansion mode and microprocessor mode : with wait 1 15.10 memory expansion mode and microprocessor mode : with wait 0 15.11 measuring circuit for ports p0 to p8 and pins f 1 and _ e
electrical characteristics 7733 group users manual 15C2 m37733mhbxxxfps electrical characteristics are described below. for low voltage version, refer to section 18.4 electrical characteristics. for the latest data, inquire of addresses described last ( + contact addresses for further information) . 15.1 absolute maximum ratings absolute maximum ratings 15.1 absolute maximum ratings parameter power source voltage analog power source voltage input voltage input voltage output voltage power dissipation operating temperature storage temperature conditions ta = 25 c unit v v v v v mw c c symbol vcc avcc v i v i v o p d t opr t stg ratings C0.3 to 7 C0.3 to 7 C0.3 to 12 C0.3 to vcc+0.3 C0.3 to vcc+0.3 300 C20 to 85 C40 to 150 reset , cnvss, byte p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , v ref , x in p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x out , e
electrical characteristics 7733 group users manual 15C3 15.2 recommended operating conditions recommended operating conditions (vcc = 5 v 10 %, ta = C20 to 85 c, unless otherwise noted) 15.2 recommended operating conditions f(x in ) :operating f(x in ) :stopped, f(x cin ) = 32.768 khz p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnvss, byte, x cin (note 3) p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnvss, byte, x cin (note 3) p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 3 , p5 4 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p4 4 Cp4 7 , p5 0 Cp5 3 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 3 , p5 4 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p4 4 Cp4 7 , p5 0 Cp5 3 parameter symbol limits min. max. 5.5 5.5 4.5 2.7 5.0 vcc 0 0 32.768 typ. unit 0.8 vcc 0.8 vcc vcc vcc vcc 0.2 vcc 0.2 vcc 0.16 vcc C10 C5 10 20 5 15 25 50 0.5 vcc 0 0 0 power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage high-level input voltage high-level input voltage low-level input voltage low-level input voltage low-level input voltage high-level peak output current high-level average output current low-level peak output current low-level peak output current low-level average output current low-level average output current main-clock oscillation frequency (note 4) sub-clock oscillation frequency vcc avcc vss avss v ih v ih v ih v il v il v il i oh (peak) i oh (avg) i ol (peak) i ol (peak) i ol (avg) i ol (avg) f(x in ) f(x cin ) v v v v v v v v v v ma ma ma ma ma ma mhz khz notes 1: average output current is the average value of a 100 ms interval. 2: the sum of i ol (peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i oh (peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i ol (peak) for ports p4, p5, p6, and p7 must be 100 ma or less, and the sum of i oh (peak) for ports p4, p5, p6, and p7 must be 80 ma or less. 3: limits v ih and v il for x cin are applied when the sub clock external input selection bit = 1. 4: the maximum value of f(x in ) = 12.5 mhz when the main clock division selection bit = 1.
electrical characteristics 7733 group users manual 15C4 high-level output voltage high-level output voltage high-level output voltage high-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage hysteresis hysteresis reset hysteresis x in hysteresis x cin (when external clock is input) high-level input current low-level input current low-level input current ram hold voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 p3 0 Cp3 2 e p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 , p4 0 Cp4 3 , p5 4 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 5 , p8 0 Cp8 7 p4 4 Cp4 7 , p5 0 Cp5 3 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 p3 0 Cp3 2 e p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnvss, byte p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 3 , p6 0 , p6 1 , p6 5 C p6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnvss, byte p5 4 Cp5 7 , p6 2 Cp6 4 15.3 electrical characteristics electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) 15.3 electrical characteristics v oh v oh v oh v oh v ol v ol v ol v ol v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i il i il v ram symbol parameter measuring conditions min. max. v v v v v v v v v v v v v m a m a m a ma v limits unit 2 2 0.45 1.9 0.43 1.6 0.4 1 0.5 0.4 0.4 5 C5 C5 C1.0 C0.25 typ. C0.5 hold , rdy , ta0 in Cta4 in , tb0 in Ctb2 in , int 0 C int 2 , ad trg , cts 0 , cts 1 , cts 2 , clk 0 , clk 1 , clk 2 , ki 0 C ki 3 i oh = C10 ma i oh = C400 a i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i ol = 10 ma i ol = 20 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5 v v i = 0 v v i = 0 v, without a pull-up transistor v i = 0 v, with a pull-up transistor when clock is stopped 3 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 0.1 2
electrical characteristics 7733 group users manual 15C5 max. 19 2.6 20 100 10 1 20 limits vcc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 12.5 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 5v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 1.5625 mhz), f(x cin ) : stopped, in operating (note 1) vcc = 5v, f(x in ) = 25 mhz (square waveform), f(x cin ) = 32.768 khz, when the wit instruction is executed (note 2) vcc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) vcc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when the wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped 15.3 electrical characteristics 15.4 a-d converter characte ristics electrical characteristics (vcc= 5 v, vss = 0 v, ta = C20 to 85 c, unless otherwise noted) unit measuring conditions symbol parameter i cc power source current min. typ. 9.5 1.3 10 50 5 ma ma a a a a a in single-chip mode, output pins are open, and the other pins are con- nected to vss. notes 1: this is applied when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output disable selection bit = 1. 2: this is applied when the main clock external input selection bit = 1 and the system clock stop selection bit at wait state = 1. 3: this is applied when the cpu and the clock timer are operati ng with the sub clock (32.768 khz) selected as the system clock. 4: this is applied when the x cout drivability selection bit = 0 and the system clock stop b it at wait state = 1. 15.4 a-d converter characteristics a-d converter characteristics (vcc = avcc = 5 v, vss = avss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note) , unless otherwise noted) limits min. typ. max. resolution v ref = vcc 10 bits absolute accuracy v ref = vcc 3 lsb r ladder ladder resistance v ref = vcc 10 25 k t conv conversion time 9.44 s v ref reference voltage 2 vcc v v ia analog input voltage 0 v ref v symbol parameter measuring conditions unit note : this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz.
electrical characteristics 7733 group users manual 15C6 limits ns ns ns ns ns ns 320 160 160 limits limits 15.5 internal peripheral devices timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. 15.5 internal peripheral devices t c(ta) t w(tah) t w(tal) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width min. 80 40 40 max. ns ns ns unit symbol parameter t c(ta) t w(tah) t w(tal) tai in input cycle time (note 3) tai in input high-level pulse width (note 3) tai in input low-level pulse width (note 3) min. max. unit symbol parameter timer a input (gating input in timer mode) parameter limits timer a input (external trigger input in one-shot pulse mode) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width max. unit symbol min. 320 80 80 t c(ta) t w(tah) t w(tal) limits tai in input high-level pulse width tai in input low-level pulse width ns ns min. 80 80 max. t w(tah) t w(tal) unit parameter symbol t c(up) t w(uph) t w(upl) t su(upCt in ) t h(t in Cup) tai out input cycle time tai out input high-level pulse width tai out input low-level pulse width tai out input setup time tai out input hold time ns ns ns ns ns min. max. unit symbol parameter timer a input (up-down input in event counter mode) timer a input (external trigger input in pulse width modulation mode) 2000 1000 1000 400 400 timer a input (count input in event counter mode) data formula (min.) data formula (min.) 8 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) (note 2) (note 2) (note 2) 8 5 10 9 2 5 f(f 2 ) (note 2) notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 3: the tai in input cycle time must be 4 cycles of a count source or more . the tai in input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively.
electrical characteristics 7733 group users manual 15C7 15.5 internal peripheral devices limits max. ns ns ns ns ns ns ns ns ns unit symbol parameter timer a input (two-phase pulse input in event counter mode) min. 800 800 800 500 250 200 500 250 200 measuring conditions f(x in ) = 8 mhz f(x in ) = 16 mhz f(x in ) = 25 mhz f(x in ) = 8 mhz f(x in ) = 16 mhz f(x in ) = 25 mhz f(x in ) = 8 mhz f(x in ) = 16 mhz f(x in ) = 25 mhz taj in input cycle time taj in input setup time taj out input setup time t c(ta) t su(taj in -taj out ) t su(taj out -taj in ) note: this is applied when the main clock division selection bit = 0.
electrical characteristics 7733 group users manual 15C8 15.5 internal peripheral devices internal peripheral devices tai in input t c(ta) t w(tah) t w(tal) tai out input (up-down input) t c(up) t w(uph) t w(upl) tai in input (when fall count is selected) tai in input (when rise count is selected) tai out input (up-down input) t h(t in Cup) t su(upCt in ) l count input in event counter mode l gating input in timer mode l external trigger input in one-shot pulse mode l external trigger input in pulse width modulation mode l up-down input and count input in event counter mode measuring conditions ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v t su(taj in Ctaj out ) taj in input taj out input t su(taj out Ctaj in ) t su(taj in Ctaj out ) t su(taj out Ctaj in ) l two-phase pulse input in event counter mode t c(ta)
electrical characteristics 7733 group users manual 15C9 ns ns ns ns ns ns ns ns ns ns min. 320 160 160 max. min. 320 160 160 timer b input (count input in event counter mode) t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) min. max. ns ns ns ns ns ns limits unit symbol tbi in input cycle time (note 1) tbi in input high-level pulse width (note 1) tbi in input low-level pulse width (note 1) t c(tb) t w(tbh) t w(tbl) ns ns ns limits unit symbol parameter timer b input (pulse period measurement mode) parameter tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edges count) tbi in input high-level pulse width (both edges count) tbi in input low-level pulse width (both edges count) 80 40 40 160 80 80 timer b input (pulse width measurement mode) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width limits unit symbol parameter max. ad trg input cycle time (minimum allowable trigger) ad trg input low-level pulse width min. max. ns ns limits unit parameter symbol t c(ad) t w(adl) a-d trigger input 1000 125 serial i/o clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width txd i output delay time txd i hold time rxd i input setup time rxd i input hold time t c(ck) t w(ckh) t w(ckl) t d(cCq) t h(cCq) t su(dCc) t h(cCd) min. max. 80 limits unit symbol parameter 200 100 100 0 30 90 data formula (min.) data formula (min.) 8 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) (note 2) (note 2) (note 2) 8 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) (note 2) (note 2) (note 2) notes 1: the tbi in input cycle time must be 4 cycles of a count source or more . the tbi in input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 15.5 internal peripheral devices
electrical characteristics 7733 group users manual 15C10 ns ns ns min. 250 250 250 ____ __ external interrupt int i input, key input interrupt ki i input int i input high-level pulse width int i input low-level pulse width ki i input low-level pulse width t w(inh) t w(inl) t w(kil) max. limits unit symbol parameter measuring conditions ? v cc = 5 v 10 % ? input timing voltage ? output timing voltage : v il = 1.0 v, v ih = 4.0 v : v ol = 0.8 v, v oh = 2.0 v tbi in input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) ad trg input t w(inl) t w(inh) int i input t c(ck) t w(ckh) t w(ckl) t h(cCq) t su(dCc) clk i input txd i output rxd i input t d(cCq) t h(cCd) t w(kil) ki i input internal peripheral devices 15.5 internal peripheral devices
electrical characteristics 7733 group users manual 15C11 15.6 ready and hold timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. hold input setup time rdy input hold time hold input hold time limits t su(rdyC f 1 ) t su(holdC f 1 ) t h( f 1 Crdy) t h( f 1 Chold) rdy input setup time max. ns ns ns ns min. parameter symbol unit 55 55 0 0 note: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) hlda output delay time t d( f 1 Chlda) ns min. max. 50 limits unit conditions parameter fig. 15.11.1 symbol 15.5 internal peripheral devices
electrical characteristics 7733 group users manual 15C12 15.6 ready and hold 1 with no wait 1 with wait rdy input ready e output e output rdy input t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) measuring conditions ? v cc = 5 v 10 % ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 hold input hlda output t h( 1 Chold) t d( 1 Chlda) t su(holdC 1 ) hold t d( 1 Chlda)
electrical characteristics 7733 group users manual 15C13 15.7 single-chip mode 15.7 single-chip mode timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. t c t w(h) t w(l) t r t f t su(p0dCe) t su(p1dCe) t su(p2dCe) t su(p3dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp0d) t h(eCp1d) t h(eCp2d) t h(eCp3d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits unit parameter 40 15 15 60 60 60 60 60 60 60 60 60 0 0 0 0 0 0 0 0 0 external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time port p0 input setup time port p1 input setup time port p2 input setup time port p3 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p0 input hold time port p1 input hold time port p2 input hold time port p3 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time symbol max. 8 8 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: when the main clock division selection bit = 1, the minimum value of tc = 80 ns. 3: when the main clock division selection bit = 1, values of tw (h) /tc and tw (l) /tc must be set to values from 0.45 through 0.55. t d(eCp0q) t d(eCp1q) t d(eCp2q) t d(eCp3q) t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) port p0 data output delay time port p1 data output delay time port p2 data output delay time port p3 data output delay time port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time ns ns ns ns ns ns ns ns ns unit symbol max. 80 80 80 80 80 80 80 80 80 min. limits parameter switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) conditions fig. 15.11.1 note: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz.
electrical characteristics 7733 group users manual 15C14 15.7 single-chip mode t d(e?0q) t su(p0d?) t h(e?0d) t d(e?1q) t su(p1d?) t h(e?1d) t d(e?2q) t su(p2d?) t h(e?2d) t d(e?3q) t su(p3d?) t h(e?3d) t w(h) t c t r t f e port p0 output port p0 input port p1 output port p1 input port p2 output port p2 input port p3 output port p3 input x in t d(e?4q) t su(p4d?) t h(e?4d) t d(e?5q) t su(p5d?) t h(e?5d) t d(e?6q) t su(p6d?) t h(e?6d) t d(e?7q) t su(p7d?) t h(e?7d) t d(e?8q) t su(p8d?) t h(e?8d) port p4 output port p4 input port p5 output port p5 input port p6 output port p6 input port p7 output port p7 input port p8 output port p8 input t w(l) single-chip mode measuring conditions ? cc = 5 v 10 % ?nput timing voltage ?utput timing voltage : v il = 1.0 v, v ih = 4.0 v : v ol = 0.8 v, v oh = 2.0 v
electrical characteristics 7733 group users manual 15C15 15.8 memory expansion mode and microprocessor mode : with no wait 15.8 memory expansion mode and microprocessor mode : with no wait timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. t c t w(h) t w(l) t r t f t su(dCe) t h(eCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 40 15 15 32 0 parameter max. 8 8 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: when the main clock division selection bit = 1, the minimu m value of tc = 80 ns. 3: when the main clock division selection bit = 1, values of tw (h) /tc and tw (l) /tc must be set to values from 0.45 through 0.55. switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits max. data formula (min.) min. 12 12 18 22 5 9 4 18 50 20 12 12 18 18 0 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) C 28 C 28 C 22 C 18 C 35 symbol t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1 ) 45 5 18 parameter address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time e pulse width floating start delay time floating release delay time bhe output delay time r/ w output delay time bhe hold time r/ w hold time f 1 output delay time conditions fig. 15.11.1 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 2 5 10 9 2 5 f(f 2 ) C 22 C 30 C 20 C 28 C 28 C 22 C 22
electrical characteristics 7733 group users manual 15C16 15.8 memory expansion mode and microprocessor mode : with no wait t h(aleCa) t h(eCdq) t d(eCdq) address/data output a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 (byte = l) data address t d(aCe) t pxz(eCdz) t pzx(eCdz) t d(eC f 1 ) t w(el) t h(eCan) t d(eC f 1 ) t w(ale) t d(bheCe) t h(eCbhe) t d(r/wCe) t h(eCr/w) x in 1 e address output a 0 Ca 7 a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l), d 0 Cd 7 (byte = h) ale output bhe output r/w output address measuring conditions ( 1 , e, ports p0Cp3) ?v cc = 5 v 10 % ?output timing voltage ?port p1, p2 input : v ol = 0.8 v, v oh = 2.0 v : v il = 0.8 v, v ih = 2.5 v with no wait (wait bit = 1) t d(eC f 1 ) t d(anCe) t su(dCe) t h(eCd) t d(aleCe) t d(bheCe) t d(r/wCe) address memory expansion mode and microprocessor mode : t w(h) t w(l) t c t f t r port pi output (i = 4C8) port pi input (i = 4C8) t d(eCpiq) t su(pidCe) t h(eCpid) t w(ale) t w(el) t d(anCe) t d(aleCe) t h(eCan) t h(eCbhe) t h(eCr/w) t f t r t c t w(h) t w(l) (write) (read) t d(eC f 1 ) measuring conditions (ports p4Cp8) ?v cc = 5 v 10 % ?input timing voltage ?output timing voltage : v il = 1.0 v, v ih = 4.0 v : v ol = 0.8 v, v oh = 2.0 v t su(aCale) address
electrical characteristics 7733 group users manual 15C17 15.9 memory expansion mode and microprocessor mode : with wa it 1 15.9 memory expansion mode and microprocessor mode : with wa it 1 timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. t c t w(h) t w(l) t r t f t su(dCe) t h(eCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 40 15 15 32 0 parameter max. 8 8 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: when the main clock division selection bit = 1, the minimu m value of tc = 80 ns. 3: when the main clock division selection bit = 1, values of tw (h) /tc and tw (l) /tc must be set to values from 0.45 through 0.55. switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits max. data formula (min.) min. 12 12 18 22 5 9 4 18 130 20 12 12 18 18 0 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) C 28 C 28 C 22 C 18 C 35 symbol t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1 ) 1 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) 45 5 18 parameter address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time e pulse width floating start delay time floating release delay time bhe output delay time r/ w output delay time bhe hold time r/ w hold time f 1 output delay time conditions fig. 15.11.1 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) C 22 C 30 C 20 C 28 C 28 C 22 C 22
electrical characteristics 7733 group users manual 15C18 15.9 memory expansion mode and microprocessor mode : with wa it 1 when external memory area is accessed with wait 1 (wait bit = 0 and wait selection bit = 1) t c t h(eC r/w) t d(r/wCe) t d(bheCe) t h(eC bhe) t w(ale) t h(eCan) t w(el) t d(eC f 1 ) t d(eC f 1 ) address x in 1 e address output a 0C a 7 , a 8C a 15 (byte = h) data input d 8C d 15 (byte = l) d 0C d 7 (byte = h) ale output bhe output r/w output t h(eC bhe) t d(aleCe) t su(dCe) t h(eCd) t d(anCe) t d(eC f 1 ) address memory expansion mode and microprocessor mode : port pi output (i = 4C8) port pi input (i = 4C8) t d(eCpiq) t su(pidCe) t h(eCpid) t w(h) t w(l) t d(eCdq) t h(aleCa) t h(eCdq) address/data output a 16 /d 0C a 23 /d 7 , a 8 /d 8C a 15 /d 15 (byte = l) data t pxz(eCdz) t pzx(eCdz) (write) (read) t d(eC f 1 ) t w(el) t h(eCan) t d(anCe) t d(aleCe) t w(ale) t r t f t w(l) t w(h) t r t f t c t d(r/wCe) t d(bheCe) t h(eC r/w) measuring conditions (ports p4Cp8) ? v cc = 5 v 10 % ? input timing voltage ? output timing voltage : v il = 1.0 v, v ih = 4.0 v : v ol = 0.8 v, v oh = 2.0 v measuring conditions ( 1 , e, ports p0Cp3) ? v cc = 5 v 10 % ? output timing voltage ? ports p1, p2 input : v ol = 0.8 v, v oh = 2.0 v : v il = 0.8 v, v ih = 2.5 v t su(aCale) t d(aCe) address address
electrical characteristics 7733 group users manual 15C19 15.10 memory expansion mode and microprocessor mode : with w ait 0 15.10 memory expansion mode and microprocessor mode : with w ait 0 timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. t c t w(h) t w(l) t r t f t su(dCe) t h(eCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 40 15 15 32 0 parameter max. 8 8 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: when the main clock division selection bit = 1, the minimu m value of tc = 80 ns. 3: when the main clock division selection bit = 1, values of tw (h) /tc and tw (l) /tc must be set to values from 0.45 through 0.55. switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits max. data formula (min.) min. 87 75 18 57 45 15 10 18 130 20 87 87 18 18 0 3 5 10 9 2 5 f(f 2 ) 3 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 2 5 10 9 2 5 f(f 2 ) 2 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) C 33 C 45 C 22 C 23 C 35 C 25 C 30 symbol t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1 ) 45 5 18 parameter address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time e pulse width floating start delay time floating release delay time bhe output delay time r/ w output delay time bhe hold time r/ w hold time f 1 output delay time conditions fig. 15.11.1 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 1 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 3 5 10 9 2 5 f(f 2 ) 3 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) C 22 C 30 C 20 C 33 C 33 C 22 C 22
electrical characteristics 7733 group users manual 15C20 15.10 memory expansion mode and microprocessor mode : with w ait 0 x in 1 address output a 0 Ca 7 , a 8 Ca 15 (byte = h) ale output e bhe output r/w output t c data input d 8 Cd 15 (byte = l) d 0 Cd 7 (byte = h) t d(eC f 1 ) t d(eC f 1 ) t w(el) t h(eCan) t w(ale) t d(bheCe) t h(eCbhe) t d(r/wCe) t h(eCr/w) address measuring conditions ( 1 , e, ports p0Cp3) ? v cc = 5 v 10 % ? output timing voltage ? ports p1, p2 input : v ol = 0.8 v, v oh = 2.0 v : v il = 0.8 v, v ih = 2.5 v t d( e C 1 ) t d( an C e) t su ( d C e) t h( e C d) t d( al e C e) t h( e C bh e) t h( e C r/ w) address/data output a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 (byte = l) t h(eCdq) t h(aleCa) t d(eCdq) t su(aCale) data t p xz( e C dz ) t p zx( e C dz ) a ddr es s a ddr es s port pi output (i = 4C8) port pi input (i = 4C8) t d(eCpiq) t su(pidCe) t h(eCpid) t w(l) t w(h) t r t f t w( el ) t f t r t w( l) t w( h) t c t d( e C 1 ) t d(anCe) t d(aleCe) t h( e C an ) t w( al e) t d( bh e C e) t d( r/ w C e) measuring conditions (ports p4Cp8) ? v cc = 5 v 10 % ? input timing voltage ? output timing voltage : v il = 1.0 v, v ih = 4.0 v : v ol = 0.8 v, v oh = 2.0 v t d(aCe) when external memory area is accessed with wait 0 (wait bit = 0 and wait selection bit = 0) memory expansion mode and microprocessor mode : address
electrical characteristics 7733 group users manual 15C21 __ 15.11 measuring circuit for ports p0 to p8 and pins f 1 and e __ 15.1 1 measuring circuit for ports p0 to p8 and pins f 1 and e p0 p1 p2 p3 p4 p5 p6 p7 p8 50 pf e 1 __ fig. 15.11.1 measuring circuit for ports p0 to p8 and pins f 1 and e
electrical characteristics 7733 group users manual 15C22 __ 15.11 measuring circuit for ports p0 to p8 and pins f 1 and e memo
chapter 16 chapter 16 standard characteristics 16.1 standard characteristics
standard characteristics 16.1 standard characteristics 7733 group users manual 16C2 16.1 standard characteristics standard characteristics described below are characteristic examples of the m37733mhbxxxfp and are not guaranteed. for each parameters limits, refer to chapter 15. electrical characteristics. 16.1.1 programmable i/o port (cmos output) standard characteristics: p0 to p3, p4 0 to p4 3 , p5 4 to p5 7 , p6, p7, and p8 (1) p-channel i oh Cv oh characteristics (2) n-channel i ol Cv ol characteristics 50.0 40.0 30.0 10.0 20.0 0 1.0 2.0 3.0 4.0 5.0 ta = 25 c ta = 85 c power source voltage v cc = 5 v v oh [ v ] i oh [ ma ] p channel 50.0 40.0 30.0 20.0 10.0 0 1.0 2.0 3.0 4.0 5.0 ta = 25 c ta = 85 c power source voltage v cc = 5 v v ol [ v ] i ol [ ma ] n channel
standard characteristics 16.1 standard characteristics 7733 group users manual 16C3 16.1.2 programmable i/o port (cmos output) standard characteristics: p4 4 to p4 7 and p5 0 to p5 3 (1) p-channel i oh Cv oh characteristics (2) n-channel i ol Cv ol characteristics power source voltage v cc = 5 v v oh [ v ] i oh [ ma ] p channel power source voltage v cc = 5 v v ol [ v ] i ol [ ma ] n channel 50.0 40.0 30.0 10.0 20.0 0 1.0 2.0 3.0 4.0 5.0 ta = 25 c ta = 85 c 50.0 40.0 30.0 20.0 10.0 0 1.0 2.0 3.0 4.0 5.0 ta = 25 c ta = 85 c
standard characteristics 16.1 standard characteristics 7733 group users manual 16C4 16.1.3 iccCf(x in ) standard characteristics (1) iccCf(x in ) characteristics on operating and at reset (2) iccCf(x in ) characteristics in wait mode measurement condition vcc = 5v,ta = 25 c, f(x in ): square waveform input, single-chip mode register setting condition oscillation circuit control register 0 = ?0 16 ?(in the wait mode, clocks f 2 to f 512 are stopped.) oscillation circuit control register 1 = ?2 16 ?(main clock is input from the external.) or ?0 16 ?(main-clock oscillation circuit is operating by itself) measurement condition vcc = 5v,ta = 25 c, f(x in ): square waveform input, single-chip mode register setting condition oscillation circuit control register 1 = ?2 16 ?(main clock is input from the external.) 0 2 4 6 8 10 12 14 0 4 8 1216202428 f(x in ) [mhz] icc [ma] on operating (cpu) cc1 = 0 0 0.5 1 1.5 2 2.5 3 0 4 8 1216202428 f(x in ) [mhz] icc [ma] cc1 = 1 cc1: main clock external input selection bit (b1 of the oscillation circuit control register 1) on operating (cpu + peripheral devices)
standard characteristics 16.1 standard characteristics 7733 group users manual 16C5 16.1.4 a-d converter standard characteristics the lower lines of the graph indicate the absolute precision errors. these are expressed as the deviation from the ideal value when the output code changes. for example, the change in output code from 0e 16 to 0f 16 should occur at 72.5 mv, but the measured value is 0.6 mv. accordingly, the measured point of change is 72.5 + 0.6 = 73.1 mv. the upper lines of the graph indicate the input voltage width for which the output code is constant. for example, the measured input voltage width for which the output code is 0f 16 is 4.7 mv. accordingly, the differential non-linear error is 4.7 C 5.0 = C0.3 mv (C0.06lsb). [measurement condition] ? v cc = av cc = 5 v, ? v ref = 5.12 v, ? f(x in ) = 25 mhz, ? ta = 25 c
standard characteristics 16.1 standard characteristics 7733 group users manual 16C6
chapter 17 chapter 17 applications 17.1 memory expansion 17.2 serial i/o 17.3 watchdog timer 17.4 power saving 17.5 timer b
applica tions 7733 group users manual 17C2 some application examples are described below. applications shown here are just examples. modify the desire d application to suit the users need and make sufficient evaluation before actually using it. 17.1 memory expansion memory ? i/o expansion examples are described below. ? for functions and operations of pins used in memory ? i/o expansion, refer to chapter 12. connecting external devices. ? for timing characteristics, refer to chapter 15. electrical characteristics. ? for timing characteristics and applications of the low vol tage version, refer to chapter 18. low voltage version. 17.1.1 memory expansion model memory expansion to the external is enabled in the memory ex pansion or microprocessor mode. in the 7733 group, the desired memory expansion model can be select ed from four models listed in table 17.1.1. this selection depends on the level of the external data bus width selection signal (byte). (1) minimum model the external data bus is 8 bits wide and the accessible area can be expanded up to 64 kbytes. no external address latch is necessary, so this model gives priority to cost and is most suitable when connecting a memory of which data bus is 8 bits wide. (2) medium model a the external data bus is 8 bits wide and the accessible area can be expanded up to 16 mbytes. the high-order 8 bits of the external address bus (a 23 to a 16 ) are multiplexed with the external data bus. therefore, one n-bit (n 8) address latch is necessary in order to latch n bits of a ddress in a 23 to a 16 . (3) medium model b the external data bus is 16 bits wide and the accessible are a can be expanded up to 64 kbytes. this model gives priority to speed. the middle-order 8 bits of the external address bus (a 15 to a 8 ) are multiplexed with the external data bus. therefore, one 8-bit address latch is necessary in order to latch a 15 to a 8 . (4) maximum model the external data bus is 16 bits wide and the accessible are a can be expanded up to 16 mbytes. the high- and middle- order 16 bits of the external address bus (a 23 to a 8 ) are multiplexed with the external data bus. therefore, both of the following latches are necessary: ? one 8-bit address latch used for latching a 15 to a 8 ? one n-bit (n 8) address latch used for latching n bits of address in a 23 to a 16 17.1 memory expansion
applica tions 7733 group users manual 17C3 table 17.1.1 memory expansion models h for functions and operations of pins used in memory expansi on, refer to chapter 12. connecting external devices. for timing characteristics, refer to chapter 15. electrical characteristics. h in memory expansion, the address bus can be expanded up to 24 bits wide. accordingly, be sure to strengthen the 7733 groups vss line on the system. (refer t o section appendix 8.countermeasure examples against noise. ) accessible area memory expansion model 64 kbytes (max.) 16 mbytes (max.) external data bus byte byte 7733 group byte 7733 group byte 7733 group 8 bits wide byte = h 16 bits wide byte = l minimum model medium model a maximum model memory expansion model medium model b memory expansion model memory expansion model a 0 to a 15 16 d 0 to d 7 8 a 0 to a 15 latch e d 0 to d 15 8 16 16 dq a 0 to a 15+n d 0 to d 7 8 16+n e n dq latch latch latch e a 0 to a 15+n d 0 to d 15 8 16 n 16+n dq e dq p0 p1 p2 ale bhe 7733 group p0 p1 p2 p0 p1 p2 ale ale bhe p0 p1 p2 17.1 memory expansion
applica tions 7733 group users manual 17C4 17.1.2 calculation ways for timing when expanding memory, use a memory of which specifications satisfy the following timing requirements: address access time (t a(ad) ) and data setup time for writing data (t su(d) ). calculation ways for t a(ad) and t su(d) are described below. address access time of external memory [t a(ad) ] t a(ad) = t d(an/a-e) + t w(el) C t su(d-e) C (address decode time ] 1 + address latch delay time ] 2 ) t d(an/a-e) : t d(an-e) or t d(a-e) address decode time ] 1 : time necessary for validating a chip select signal after a n address is decoded address latch delay time ] 2 : delay time necesarry for latching an address (this is not necessary on the minimum model.) data setup time of external memory for writing data [t su(d) ] t su(d) = t w(el) C t d(e-d) table 17.1.2 lists the calculation formulas and constants fo r each parameter in the above formulas. figure 17.1.1 shows bus timing diagrams. figure 17.1.2 shows the re lationship between t a(ad) and 2 ? f(f 2 ). figure 17.1.3 shows the relationship between t su(d) and 2?f(f 2 ). table 17.1.2 calculation formulas and constants for each par ameter (unit: ns) software wait wait bit wait selection bit t d(a-e) t d(an-e) t w(el) t su(d-e) t d(e-dq) wait 1 0 1 wait 0 0 0 no wait 1 0 or 1 C 30 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) C 28 3 5 10 9 2 ? f(f 2 ) C 45 32 45 4 5 10 9 2 ? f(f 2 ) C 30 wait bit: bit 2 at address 5e 16 wait selection bit: bit 0 at address 5f 16 note: the above is applied when the system clock selection bit (b it 3 at address 6c 16 ) = 0. 17.1 memory expansion
applica tions 7733 group users manual 17C5 fig. 17.1.1 bus timing diagrams t su(d-e) when byte = l (external data bus = 16 bits wide) e ale high-order address low-order address t d(an-e) t d(a-e) t su(d-e) t w(el) when data is written high-order address low-order data t d(e-dq) low-order address when data is read middle-order address t d(a-e) middle-order address high-order data t d(e-dq) r/ w when byte = h (external data bus = 8 bits wide) middle-order address e ale high-order address low-order address t d(an-e) t d(an-e) t d(a-e) t su(d-e) t w(el) a 0 to a 7 a 8 to a 15 a 16 /d 0 to a 23 /d 7 high-order address data t d(e-dq) middle-order address low-order address when data is written when data is read r/ w data data data t a(ad) t su(d) t w(el) t a(ad) t su(d) t w(el) a 0 to a 7 a 8 /d 8 to a 15 /d 15 a 16 /d 0 to a 23 /d 7 : specifications of the 7733 group (the others are specifications of external memory.) 17.1 memory expansion
applica tions 7733 group users manual 17C6 fig. 17.1.3 relationship between tsu (d) and 2 ? f(f 2 ) fig. 17.1.2 relationship between ta (ad) and 2 ? f(f 2 ) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 100 200 300 400 500 600 700 800 900 893 768 670 593 529 476 431 393 359 330 304 281 261 243 226 211 197 184 173 624 535 465 410 364 326 294 267 243 222 204 187 173 160 148 137 127 118 110 338 285 243 210 182 160 140 124 110 97 86 76 67 60 52 46 40 35 30 no wait wait 1 is valid. wait 0 is valid. address access time ta (ad) [ns] external clock input frequency 2 ? f(f 2 ) [mhz] h address decode time and address latch delay time are not co nsidered. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 100 200 300 400 500 496 425 369 325 288 258 232 210 191 175 160 147 135 125 115 106 98 91 85 175 147 125 106 91 78 67 58 50 42 36 30 25 20 15 11 8 5 no wait wait 1 or wait 0 is valid. external clock input frequency 2 ? f(f 2 ) [mhz] data setup time tsu (d) [ns] 210 17.1 memory expansion
applica tions 7733 group users manual 17C7 17.1.3 points in memory expansion (1) timing for reading data figure 17.1.4 shows the timing at which data is read from an external memory. when data is read, the external data bus enters a floating s tate and reads data from the external memory. the floating state of the external data bus is retai ned from when an interval of t pxz(e-dz) has _ _ passed after signal es falling edge until an interval of t pzx(e-dz) has passed after signal es rising edge. table 17.1.3 lists the value of t pxz(e-dz) and the calculation formula for t pzx(e-dz) . note that the external data bus is multiplexed with the exte rnal address bus. therefore, when reading data, it is necessary to consider timing to avoid collision between data being read-in and an address which is output preceding or following the data. (refer to (3) precautions on memory expansion. ) h 1 this is applied when the external data bus = 16 bits wide (byte = l). h 2 when the external memorys specifications are smaller tha n t pxz (e-dz) , there is a possibility that the tail of address collides with the head of data. ? refer to (3) precautions on memory expansion. h 3 when the external memorys specifications are greater than t pzx (e-dz) , there is a possibility that the tail of data collides with the head of address. ? refer to (3) precautions on memory expansion. t en (oe) address address t pzx (e-dz) t su (d-e) t a (oe) t a (ce) , t a (s) t df , t dis (oe) h 2 h 3 t w(el) data t pxz (e-dz) t en (ce) , t en (s) external memory data output external memory output enable signal (read signal) oe e external memory chip select signals ce, s address output and data input a 8 / d 8 to a 15 /d 15 a 16 /d 0 to a 23 /d 7 h 1 : specifications of the 7733 group (the others are specifications of external memory.) fig. 17.1.4 timing at which data is read from external memor y 17.1 memory expansion
applica tions 7733 group users manual 17C8 table 17.1.3 value of t pxz(e-dz) and calculation formula for t pzx(e-dz) (unit: ns) wait 0 0 0 wait 1 0 1 5 1 5 10 9 2 ? f(f 2 ) C 20 software wait wait bit wait selection bit t pxz(e-dz) t pzx(e-dz) no wait 1 0 or 1 wait bit: bit 2 at address 5e 16 wait selection bit: bit 0 at address 5f 16 note: the above is applied when the system clock selection bit (b it 3 at address 6c 16 ) = 0. 17.1 memory expansion
applications 7733 group users manual 17C9 (2) timing for writing data figure 17.1.5 shows the timing for writing data to an external memory. _ when data is written, the data is output from when an interval of t d ( e-dq ) has passed after signal es _ falling edge until an interval of t h ( e-dq ) has passed after signal es rising edge. table 17.1.4 lists the value of t d ( e-dq ) and the calculation formula for t h ( e-dq ). make sure that the data output timing for writing data satisfies the following specifications of the external memory: data setup time (t su ( d )) and data hold time (t h ( d )) for writing data. fig. 17.1.5 timing at which data is written to external memory table 17.1.4 value of t d(e-dq) and calculation formula for t h(e-dq) (unit: ns) wait 0 0 0 wait 1 0 1 45 C 22 1 5 10 9 2 ? f(f 2 ) no wait 1 0 or 1 wait bit: bit 2 at address 5e 16 wait selection bit: bit 0 at address 5f 16 note: the above is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0. 17.1 memory expansion external memory write signals w, we external memory chip select signals ce, s (the others are specifications of external memory.) : specifications of the 7733 group h this is applied when the external data bus = 16 bits wide (byte = ??). e address and data output h a 8 / d 8 to a 15 /d 15 a 16 /d 0 to a 23 /d 7 t su (d) t h (d) address data address t w(el) t h (e-dq) t d (e-dq) software wait wait bit wait selection bit t d ( e-dq ) t h ( e-dq )
applications 7733 group users manual 17C10 (3) precautions on memory expansion when specifications of the 7733 group do not match those of an external memory as described in the following to a , some considerations about the circuit are necessary: when using an external memory which requires a long address access time (t a(ad) ) _ when using an external memory which outputs data within an interval of t pxz(e-dz) after signal es falling edge. a when using an external memory which outputs data for more than an interval of t pzx(e-dz) after _ signal es rising edge when using an external memory which requires a long address access time (t a (ad) ) when an external memory requires a long address access time (t a(ad) ) which does not satisfy the 7733 groups t su(d-e), try to carry out the following: l lower 2 ? f(f 2 ) l select software wait is inserted. (refer to section 12.2 software wait. ) l use the ready function. (refer to section 12.3 ready function. ) figure 17.1.6 shows a ready generating circuit example (with no wait). figure 17.1.7 shows a ready generating circuit example (with wait 1). note that the ready function is also valid for the internal area. therefore, in figures 17.1.6 and 17.1.7, ___ areas where the ready function is valid are specified by using the chip select signal ( cs 2 ) which is externally generated. 17.1 memory expansion
applica tions 7733 group users manual 17C11 fig. 17.1.6 ready generating circuit example (with no wait) 17.1 memory expansion 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) f(x cin ) or wait generated by the ready function is inserted only to an area where accessed by signal cs 2 . m37733mhbxxxfp cs 1 a 8 to a 23 (d 0 to d 15 ) a 0 to a 7 ac74 d t q 1 rdy e ac32 ac32 ac04 address bus data bus address latch circuit address decode circuit cs 2 circuit conditions: f (x in ) 15.7 mhz, no wait 1 e 1 cs 2 q rdy t c t d(e- 1 ) t su(rdy- 1 ) propagation delay time of ac32 (max.: 8.5 ns) h h condition to satisfy the relationship of t su ( rdy- 1 ) 3 55 ns in the left timing chart is tc 3 63.5 ns. accordingly, when f(x in ) 15.7 mhz, this example satisfies the relationship of t su ( rdy- 1 ) 3 55 ns. : wait generated by the ready function 2
applica tions 7733 group users manual 17C12 fig. 17.1.7 ready generating circuit example (with wait 1) 17.1 memory expansion wait generated by the ready function is inserted only to an area where accessed by signal cs 2 . m37733mhbxxxfp cs 1 a 8 to a 23 (d 0 to d 15 ) a 0 to a 7 1d 1t 1q 1 rdy e f32 f32 address bus data bus address latch circuit address decode circuit cs 2 2d 2t 2q rd f04 f04 f74 h 1 h 2 h 3 1 e cs 2 1q rdy t h( 1 -rdy) 2q : wait generated by the ready function : software wait t su(rdy- 1 ) 1 h 1 to h 3 make sure that the sum of propagation delay time is within (when 2 ? f(f 2 ) = 25 mhz, 25 ns). 2 5 10 2 ? f(f 2 ) C t su(rdyC 1 ) 9 circuit conditions: f (x in ) 25 mhz, wait 1 is valid, 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) 2 f(x cin ) or
applica tions 7733 group users manual 17C13 when using an external memory which outputs data within an i nterval of t pxz(e-dz) after signal _ es falling edge when there is a possibility that the tail of an address coll ides with the head of data because the _ external memory outputs data within an interval of t pxz(e-dz) after signal es falling edge, delay only _ ___ the es front falling edge. in this case, the fall ing edge of the read signal ( oe ) for the memory, which __ is generated from signal e , is delayed. (refer to figure 17.1.8. ) 17.1 memory expansion fig. 17.1.8 timing example when data output is delayed external memory output enable signal (read signal) address output external memory data output t pxz ( e-dz ) e oe d address address data t en ( oe ) t a ( oe ) satisfy the following conditions: ? t pxz(e-dz) t en(oe) +d ? when t en(oe) t pxz(e-dz) (= 5 ns), make sure that signal es falling edge precedes signal oes falling edge and an interval of d is secured . note: (the others are specifications of external memory.) : specifications of 7733 group
applications 7733 group users manual 17C14 a when using an external memory which outputs data for more than an interval of t pzx (e-dz) after _ signal es rising edge when there is a possibility that the tail of data collides with the head of an address because the _ external memory outputs the data for more than an interval of t pzx(e-dz) after signal es rising edge, try to carry out the following: l by using bus buffers and others, delete the tail of data which is output from the memory. l use a memory which is made by mitsubishi electric corporation and can be connected without bus buffers. figures 17.1.9 to 17.1.12 show bus buffer usage examples and the corresponding timing diagrams. table 17.1.5 lists memories which can be connected without bus buffers (made by mitsubishi elec- tric corporation). the reason why these memories do not need buffers is that timing parameters _ t df or t dis(oe) is guaranteed. (make sure that the read signal rises within 10 ns after signal es rising edge.) table 17.1.5 memories which can be connected without bus buffers (made by mitsubishi electric corporation) 17.1 memory expansion memory m5m27c256ak-85, -10, -12, -15 m5m27c512ak-10, -12, -15 m5m27c100k-12, -15 m5m27c101k-12, -15 m5m27c102k-12, -15 m5m27c201k, jk-10, -12, -15 m5m27c202k, jk-10, -12, -15 m5m27c256ap, fp, vp, rv-12, -15 m5m27c512ap, fp-15 m5m27c100p-15 m5m27c101p, fp, j, vp, rv-15 m5m27c102p, fp, j, vp, rv-15 m5m27c201p, fp, j, vp, rv-12, -15 m5m27c202p, fp, j, vp, rv-12, -15 m5m28f101p, fp, j, vp, rv-10, -12, -15 m5m28f102fp, j, vp, rv-10, -12, -15 m5m5256cp, fp, kp, vp, rv-55ll, -55xl, -70ll, -70xl, -85ll, -85xl, -10ll, -10xl m5m5278cp, fp, j-20, -20l m5m5278cp, fp, j-25, -25l m5m5278dp, j-12 m5m5278dp, fp, j-15, -15l m5m5278dp, fp, j-20, -20l type usage condition t df /t dis(oe) (max.) 15 ns (when guaranteed as kit) ( note ) 8 ns 10 ns 6 ns 7 ns 8 ns 2 ? f(f 2 ) 20 mhz 2 ? f(f 2 ) 25 mhz eprom one time prom frash memory sram note: specifications of the above memories are available if a comment of t df/ t dis(oe) = 15 ns, microcomputer and kit is added.
applica tions 7733 group users manual 17C15 fig. 17.1.9 bus buffer usage example (1) 17.1 memory expansion circuit conditions: wait 1 is valid, 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) 2 f(x cin ) f245 byte a 8 /d 8 to a 1 5 /d 15 25 mhz data bus (even) data bus (odd) le dq oe ac573 dir ab le dq oe ac573 ale a 1 to a 7 address bus m37733mhbxxxfp dir ab e a 0 r/w bhe bc32 ac04 rd wo we ac32 x in x out f245 h 2 h 2 h 3 a 16 /d 0 to a 23 /d 7 h 1 cnv ss h 4 oc oc h 1 make sure that the propagation delay time is 12 ns or le ss. h 2, h 3 make sure that the following relationships are satisfied: l the sum of output disable time of h 2 and propagation delay time of h 3 is 20 ns or less. l the sum of output enable time of h 2 and propagation delay time of h 3 is 5 ns or more. h 4 make sure that the propagation delay time is 12 ns or le ss. or
applications 7733 group users manual 17C16 fig. 17.1.10 timing diagram for bus buffer usage example (1) 17.1 memory expansion a 8 /d 8 to a 15 /d 15 a 16 /d 0 to a 23 /d 7 data output a from external memory (f245) e oc (f245) , rd 5 (max.) 130 (min.) 20 (min.) bc32 (t phl ) bc32 (t plh ) d aa f245 (t phz /t plz ) f245 (t pzh /t pzl ) a 8 /d 8 to a 15 /d 15 a 16 /d 0 to a 23 /d 7 data output b to external memory (f245) e 130 (min.) bc32 (t plh ) d aa d f245 (t phl /t plh ) (unit: ns) f245 (t phz /t plz ) oc (f245) , wo , we 45 (max.) bc32 (t phl )
applica tions 7733 group users manual 17C17 fig. 17.1.11 bus buffer u sage example (2) ( when a memory which requires a long data hold time for writing is connected ) 17.1 memory expansion h 1 make sure that the propagation delay time is 40.5 ns or less. h 2 make sure that the output enable time is 5 ns or more and the output disable time is 42.5 ns or less. circuit conditions: wait 1 is valid, 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) 2 f(x cin ) or als245a byte e 16 mhz data bus (even) data bus (odd) le dq oe ac573 oc dir ab le dq oe ac573 ale a 1 to a 7 address bus dir ab a 0 r/w bhe ac32 ac04 rd we wo 1d 1q 1t 2d 2q 2t 1 ac74 ac32 ac04 x in x out als245a a 8 /d 8 to a 15 /d 15 m37733mhbxxxfp a 16 /d 0 to a 23 /d 7 h 1 h 2 cnv ss h 2 oc 1 these circuits make the rising edge of the write signal earlier by 1/2 1 , so that the write hold time is extended.
applica tions 7733 group users manual 17C18 fig. 17.1.12 timing diagram for bus buffer usage example (2) 17.1 memory expansion a 8 /d 8 to a 15 /d 15 a 16 /d 0 to a 23 /d 7 data output a from external memory (als245a) rd 5 (max.) 220 (min.) 42.5 (min.) ac32 (t phl ) ac32 (t plh ) d a als245a (t phz /t plz ) e, oc (als245a) als245a (t pzh /t pzl ) (unit: ns) d a d ac32 5 2 (t plh ) write hold time als245a (t phz /t plz ) a 8 /d 8 to a 15 /d 15 a 16 /d 0 to a 23 /d 7 data output b to external memory (als245a) wo , we 2q(ac74) 1q (ac74) e, oc (als245a) ac04 (t plh )+ac74 (t plh ) 70 (max.) als245a (t phl /t plh ) 220 (min.) 1 1 ac04 (t plh )+ac74 (t phl ) 5 2 (t phl ) ac32 a
applica tions 7733 group users manual 17C19 17.1.4 memory expansion example (1) rom expansion example on minimum model figure 17.1.3 shows a rom expansion example on the minimum m odel (with a 32-kbyte rom, memory expansion mode). figure 17.1.4 shows the correspondin g timing diagram. 17.1 memory expansion fig. 17.1.13 rom expansion example on minimum model circuit conditions: wait 1 is valid, a 0 to a 14 d 0 to d 7 ac00 25 mhz x in x out m37733s4bfp byte r/w e bhe a 0 to a 14 d 0 to d 7 oe ce m5m27c256ak-10 a 15 h open 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) 2 f(x cin ) h make sure that the propagation delay time is 10 ns or less. 0000 16 0080 16 0880 16 8000 16 external rom area (m5m27c256ak) sfr area internal ram area not used memory map ffff 16 or
applications 7733 group users manual 17C20 17.1 memory expansion fig. 17.1.14 timing diagram for rom expansion example on minimum model d 0 to d 7 external rom data output (a) (a) d ce t a (ad) 130 (min.) 12 (min.) 5 (max.) 20 (min.) t a (oe) t su (d-e) 3 32 15 (max.) (guaranteed as kit.) e , oe ac00 (t plh ) ac00 (t phl ) t a (ce) (unit: ns) a 0 to a 14 a
applica tions 7733 group users manual 17C21 (2) rom expansion example on maximum model figure 17.1.5 shows a rom expansion example on the maximum m odel (with a 2-mbit rom, micro- processor mode). figure 17.1.6 shows the corresponding timin g diagram. 17.1 memory expansion fig. 17.1.15 rom expansion example on maximum model m5m27c202k-10 a 0 to a 16 oe a 1 to a 7 ac04 25 mhz x in x out m37733s4bfp byte data bus a 1 to a 17 address bus a 16 /d 0 , a 17 /d 1 ale d 1 to d 7 e r/w a 8 /d 8 to a 15 /d 15 ac573 ce d 0 to d 15 d 0 to d 15 a 8 to a 15 0000 16 0080 16 sfr area internal ram area external rom area (m5m27c202k) memory map q le d cnvss h 1, h 2 make sure that the propagation delay time is 10 ns or less. h 2 h 1 ac573 q le d a 16 , a 17 3ffff 16 0880 16 circuit conditions: wait 1 is valid, 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) 2 f(x cin ) or
applications 7733 group users manual 17C22 fig. 17.1.16 timing diagram for rom expansion example on maximum model 17.1 memory expansion a 8 /d 8 to a 15 /d 15 a 16 /d 0 a 130 (min.) 12 (min.) t a (ad) +ac573 (t phl /t plh ) external rom data output ce t a (oe) r/w 12 (min.) t a (ce) ac04 (t phl ) 20 (min.) a 5 (max.) d (guaranteed as kit.) t su (d-e) 3 32 (unit: ns) 18 (max.) e , oe ac04 (t plh ) 15 (max.)
applica tions 7733 group users manual 17C23 (3) rom and sram expansion example on maximum model figure 17.1.17 shows an expansion example for rom and sram o n the maximum model (with two 32-kbyte roms and two 32-kbyte srams, microprocessor mode). figure 17.1.18 shows the corre- sponding timing diagram. 17.1 memory expansion fig. 17.1.17 expansion example for rom and sram on maximum m odel 0000 16 0080 16 external rom area (m5m27c256ak 5 2) sfr area internal ram area external ram area (m5m5256cp 5 2) memory map 1ffff 16 10000 16 0880 16 ac32 ac04 20 mhz x in x out m37733s4bfp byte a16 a8 to a15 data bus (even) data bus (odd) ac573 dq le ac32 ac04 rd d0 to d7 d8 to d15 address bus wo a 0 to a 14 d 0 to d 7 m5m27c256ak-15 a1 to a15 d 0 to d 7 oe a 0 to a 14 ce a1 to a15 s s a 0 to a 14 a 0 to a 14 dq 1 to dq 8 dq 1 to dq 8 oe w oe w a1 to a15 a1 to a15 d0 to d7 m5m5256cp-70ll oe d8 to d15 ce we a 1 to a 7 a 8 /d 8 to a 15 /d 15 ale a 16 /d 0 d 1 to d 7 r/w e a 0 bhe cnv ss h 2 h 1 h 3 ac573 dq le h 2 circuit conditions: wait 1 is valid, 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) 2 f(x cin ) or h 1, h 2 make sure that the following relationship is satisfied: l the sum of propagation delay time of h 1 and that of h 2 is 90 ns or less. h 2 make sure that the propagation delay time is 10 ns or le ss. h 3 make sure that the propagation delay time is 15 ns or le ss.
applica tions 7733 group users manual 17C24 fig. 17.1.18 timing diagram for rom and sram expansion examp le on maximum model 17.1 memory expansion a 1 to a 7 a e a 8 / d 8 to a 15 / d 15 a 16 / d 0 , d 1 to d 7 s a d 170 (min.) 45 (max.) 22 (min.) ac32 (t phl ) t su (d) 3 30 (unit: ns) we , wo ac573 (t phl )+ac04 (t phl ) ac32 (t plh ) a 8 / d 8 to a 15 / d 15 a 16 / d 0 external memory data output a d e 170 (min.) 22 (min.) 5 (max.) 30 (min.) (guaranteed as kit.) t a (ad) , t a (ce) t su (d-e) 3 32 t a (s) oe ac32 (t plh ) a 1 to a 7 a ce , s t a (oe) ac04 (t phl ) ac573 (t phl ) ce s ac32 (t phl ) 15 (max.) 23 (min.) a a a a
applications 7733 group users manual 17C25 17.1.5 i/o expansion example (1) port expansion example where the m66010fp is used fig. 17.1.19 shows a port expansion example where the m66010fp is used. the frequency of a transmit clock for serial i/o must be 1.923 mhz or less. serial i/o control in this expansion example is described below. in this expansion example, 8-bit data transmission/reception is performed three times by using uart0, and so ports expand by 24 bits. uart0 is set as follows: l clock synchronous serial i/o mode is selected. transmission/reception is enabled. l an internal clock is selected. transfer rate = 1.5625 mhz l lsb first is selected. the control procedure is as follows: l level is output from port p4 5 . (by this signal, the expanded i/o ports of the m66010fp enter a floating state.) h level is output from port p4 5 . a l level is output from port p4 4 . ? 24-bit data is transmitted/received using uart0. ? h level is output from port p4 4 . fig. 17.1.20 shows the timing of serial transfer between the m37733mhbxxxfp and m66010fp. 17.1 memory expansion
applica tions 7733 group users manual 17C26 fig. 17.1.19 port expansion example where m66010fp is used 17.1 memory expansion circuit conditions: uart0 is used in clock synchronous seria l i/o mode. internal clock is selected. transfer clock frequency 25 mhz txd 0 rxd 0 clk 0 p4 4 p4 5 rts 0 m37733mhbxxxfp x in x out di do clk cs s vcc gnd cnvss byte m66010fp expanded i/o ports d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 a 0 to a 7 a 8 /d 8 to a 15 /d 15 a 16 /d 0 to a 23 /d 7 ale e 1 r/w bhe open f 2 2 (3 + 1) = = 1.5625 mhz
applications 7733 group users manual 17C27 17.1 memory expansion fig. 17.1.20 timing of serial transfer between m37733mhbxxxfp and m66010fp do1 do2 do3 do4 do5 do6 do7 do8 do20 do21 do22 do23 do24 di1 di2 di3 di4 di5 di6 di7 di8 di20 di21 di22 di23 di24 di1 di2 di24 s cs clk di do expanded i/o port expanded i/o port expanded i/o port data of expanded i/o ports are input to the shift register 1. expanded i/o ports are released from the floating state. data of the shift register 1 is output in serial. serial data is input to the shift register 2. do24 do2 do1 data of the shift register 2 is output to expanded i/o ports. d1 d2 d24 p4 5 p4 4 clk 0 t x d 0 r x d 0 h output structure of expanded i/o ports is n-channel open drain output. : pins?names of the 7733 group. the others are pins?names or operations of the m66010fp. to
applications 7733 group users manual 17C28 17.2 serial i/o examples for serial i/o are described below: ?examples where the microcomputer is connected with an external device by using serial i/o ?examples where serial data is transmitted and received 17.2.1 connection examples with external device (clock synchronous serial i/o mode) (1) connection with peripheral ics 17.2 serial i/o fig. 17.2.2 example where transmission/recep- tion is performed fig. 17.2.1 example where only transmission is performed fig. 17.2.3 example where transmission/reception is performed (connection example with wired- or) clk i t x d i clk in m37733mhbxxxfp peripheral ic (osd controller and so on) clk i t x d i r x d i clk in out m37733mhbxxxfp peripheral ic (e prom and so on) 2 clk i t x d i r x d i clk in out m37733mhbxxxfp peripheral ic (e prom and so on) 2 h set pin txd i to n-channel open - drain output. uart0: data output selection bit ( bit 5 at address 34 16 ) ? uart1: data output selection bit ( bit 5 at address 3c 16 ) ? when receiving, be sure to set pin txd i ? output to ??level. (pin rxd i is in a floating state.)
applications 7733 group users manual 17C29 17.2 serial i/o fig. 17.2.5 case where internal clock is selected fig. 17.2.6 case where external clock is selected m37733mhbxxxfp clk 0 clk in peripheral ic 1 clks 0 clk in peripheral ic 2 clks 1 t x d 0 clk in peripheral ic 3 one of three transmit clock output pins, which is selected by software, outputs a transmit clock. multiple transmit clock output pins can be used only when the following conditions are satisfied: l clock synchronous serial i/o mode is selected. l internal clock is selected. l only transmission is performed with uart0 used. h clk i cts i r x d i clk port out m37733mhbxxxfp microcomputer t x d i in i = 0 to 2 i = 0 to 2, j = 0 and 1 clk i rts i r x d i clk port out m37733mhbxxxfp microcomputer t x d i in note: the rts output function is not assigned for uart2. fig. 17.2.4 case where transmission for several peripheral devices is performed with 1-channel serial i/o used (2) connection with microcomputer
applications 7733 group users manual 17C30 17.2.2 examples of transmission for several peripheral ics (clock synchronous serial i/o mode) in this example, transmission for three peripheral ics is performed with uart0 used. (note that simulta- neous transmission for several peripheral ics is disabled.) (1) specifications clock synchronous serial i/o mode is selected. an internal clock is selected. transfer rate = 2 mhz a msb first is selected. ? transmit data is output at the falling edge of the transfer clock. ? pin txd 0 s output structure: cmos output ? completion of transmission is determined by checking the transmission register empty flag. fig. 17.2.7 connection example 17.2 serial i/o clk 0 clk in m37733mhbxxxfp peripheral ic 1 clks 0 clk in peripheral ic 2 clks 1 t x d 0 clk in peripheral ic 3
applications 7733 group users manual 17C31 (2) initial settings for related registers 17.2 serial i/o x: it may be ?? or ?. clock synchronous serial i/o mode b7 b0 uart0 transmit/receive mode register (address 30 16 ) 0x x internal clock is selected. x0001 must be fixed to ?. cts / rts function is disabled. brg0 count source: f 2 b7 b0 uart0 transmit/receive control register 0 (address 34 16 ) 10 1 0xx00 pin t x d 0 ? output structure: cmos output transmit data is output at the falling edge of the transfer clock. msb first when the system clock (main clock) frequency = 16 mhz, transfer rate = 2 mhz b7 b0 uart0 baud rate register (brg0) (address 31 16 ) 01 16 transmission is enabled. b7 b0 uart0 transmit/receive control register 1 (address 35 16 ) xx x reception is disabled. xx0x1 0 00 x b7 b0 uart0 transmission interrupt control register (address 71 16 ) uart0 transmission interrupt is disabled. pin clks 1 is in the output mode when not transferring. b7 b0 port p8 direction register (address 14 16 ) xx1 pin clks 1 outputs ??level when not transferring. b7 b0 port p8 register (address 12 16 ) x xx 1 by this setting, pin clks 1 functions as port p8 0 and outputs ??level when not transferring, in other words, when no clock is output. h 1 pin clks 0 do the processing of ?utput when not transferring. (??level is output.) h h 0 fig. 17.2.8 initial settings for related registers
applications 7733 group users manual 17C32 (3) approximate flowchart transmission buffer empty flag = ??? (bit 1 at address 35 16 ) serial transmit control register ?x01xxxx 2 (address 6e 16 ) main routine transfer clock is output from pin clk 0 . (data is transmitted to peripheral ic1.) uart0 transmission buffer register [transmit data 1] (address 32 16 ) transmission register empty flag = ??? (bit 3 at address 34 16 ) 1: transfer is completed. serial transmit control register ?x10xxxx 2 (address 6e 16 ) uart0 transmission buffer register [transmit data 2] (address 32 16 ) transmission register empty flag = ??? (bit 3 at address 34 16 ) 1: transfer is completed. 1: transmission is completed. 1: transmission is completed. 0 0 0 0 at first, transmit data 1 is transmitted to peripheral ic1, and then transmit data 2 is transmitted to peripheral ic2. transmit data is set. waiting for the completion of transmission waiting for the start of transmission transfer clock is output from pin clks 0 . (data is transmitted to peripheral ic2.) transmit data is set. waiting for the completion of transmission waiting for the start of transmission transmission buffer empty flag = ??? (bit 1 at address 35 16 ) x: it may be ??or ?. fig. 17.2.9 approximate flowchart 17.2 serial i/o
applications 7733 group users manual 17C33 17.2.3 transmission/reception example (uart mode, transfer data length = 8 bits) in this example, transmission/reception is performed with uart1 used (transfer data length = 8 bits). (1) specifications uart mode is selected (transfer data length = 8 bits) an internal clock is selected. baud rate = 9,600 bps a parity is disabled. ? 1 stop bit is selected. ? pin txd 1 s output structure: cmos output ? the sleep mode is invalid. ? transmission start is determined by using a uart1 transmission interrupt. ? receive data is read out by using a uart1 reception interrupt. fig. 17.2.10 connection example 17.2 serial i/o rts 1 t x d 1 r x d 1 port in out m37733mhbxxxfp peripheral ic
applications 7733 group users manual 17C34 (2) initial settings for related registers fig. 17.2.11 initial settings for related registers 17.2 serial i/o x : it may be ??or ?. when the system clock (main clock) frequency = 16 mhz, baud rate = 9,600 bps b7 b0 uart1 baud rate register (brg1) (address 39 16 ) 33 16 b7 b0 uart1 transmit/receive control register 1 (address 3d 16 ) transmission is enabled. xx x reception is enabled. xx1x1 pin r x d 1 : input mode b7 b0 port p8 direction register (address 14 16 ) x0 x x uart mode (transfer data length = 8 bits) b7 b0 uart1 transmit/receive mode register (address 38 16 ) 00 0 internal clock is selected. x0101 1 stop bit parity is disabled. sleep mode is invalid. must be fixed to ?. brg1 count source: f 2 b7 b0 uart1 transmit/receive control register 0 (address 3c 16 ) 00 0 rts function is selected. 0x100 cts / rts function is enabled. pin t x d 1 ? output structure: cmos output b7 b0 uart1 transmission interrupt control register (address 73 16 ) interrupt priority level is set. (note that a value other than ?00 2 ?is set.) 0 interrupt request bit: 0 (initialized) b7 b0 uart1 receive interrupt control register (address 74 16 ) 0 interrupt request bit: 0 (initialized) interrupt disable flag (i) ?? interrupt is enabled. interrupt priority level is set. (note that a value other than ?00 2 ?is set.)
applications 7733 group users manual 17C35 (3) approximate flowchart 17.2 serial i/o fig. 17.2.12 approximate flowchart (1) whether transmission of the preceding data has started or not is determined. (whether the next data can be set to the uart1 transmission buffer register or not is determined.) register save processing uart1 transmission interrupt routine [f_dataout] ? flag used to determine whether a transmission interrupt request has occurred or not: ? register return processing rti [f_dataout]: flag used to determine whether a transmission interrupt request has occurred or not. [tra_data]: ram where transmit data is stored. main routine [f_dataout] = ??? [f_dataout] ? uart1 transmission buffer register [tra_data] ( address 3a 16 ) 1: transmission interrupt request has occurred. 0 the flag used to determine whether a transmission interrupt request has occurred or not is initialized. transmit data is set.
applications 7733 group users manual 17C36 17.2 serial i/o fig. 17.2.13 approximate flowchart (2) main routine [f_datain] = ??? [f_datain] 0 1: reception interrupt request has occurred. 0 whether reception has been completed or not is determined. the flag used to determine whether a reception interrupt request has occurred or not is initialized. [f_datain]: flag used to determine whether a reception interrupt request has occurred or not [f_error]: flag used to determine whether a data reception error has occurred or not [f_error] ? 0: no error is found. 1: error is found. whether data has been correctly received or not is determined. error processing (note) received data processing when an error occurs, reception is disabled in a reception interrupt routine. therefore, when restarting reception after error processing is completed in the main routine, make reception enabled again. note:
applica tions 7733 group users manual 17C37 fig. 17.2.14 approximate flowchart (3) 17.2 serial i/o flag used to determine whether a data reception error has occurred or not = 0 confirmed receive data is stored in [rec_data] [f_error] 0 0: no error is found. 1: error is found. whether data has been correctly received or not is determined. [f_error]: flag used for determination of data reception err or [work_ram]: ram where receive data is temporarily stored [rec_data]: ram where confirmed receive data is stored [f_datain]: flag used to determine whether a reception inter rupt request has occurred or not [rec_data] [work_ram] 0: no error is found. (note) [work_ram] uart1 receive buffer register (address 3e 16 ) [f_datain] 1 flag used to determine whether a reception interrupt request has occurred or not = 1 register return processing rti register save processing uart1 reception interrupt routine error sum flag? (bit 7 at address 3d 16 ) overrun error flag? (bit 4 at address 3d 16 ) 1: error is found. [f_error] 1 reception enable bit 0 ( bit 2 at address 3d 16 ) all of error flags = 0 (reception is disabled.) receive data is temporarily stored in [work_ram] framing error flag = 0 parity error flag = 0 if the next data is received from when the error sum flag is checked until the contents of the uart1 receive buffer register is transferred to [work_ram], an overrun error occu rs. therefore, at this timing, the content of the overrun error flag is checked again. note: flag used to determine whether a data reception error has occurred or not = 1
applications 7733 group users manual 17C38 17.2.4 8-bit transmission example (clock synchronous serial i/o mode) in this example, after 8-bit data is transmitted with uart1 used, a strobe signal is output. (1) specifications clock synchronous serial i/o mode is selected. an internal clock is selected. transfer rate = 2 mhz a lsb first is selected. ? transmit data is output at the falling edge of the transfer clock. ? pin t x d 1 s output structure: cmos output ? a strobe signal is output from port p4 3 each time 8-bit data is transmitted. (refer to figure 17.2.16. ) ? completion of the transmission is determined by checking the transmission register empty flag. fig. 17.2.15 connection example fig. 17.2.16 strobe signal output timing 17.2 serial i/o clk 1 p4 3 (strobe signal) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d 1 clk 1 t x d 1 p4 3 clk in stb m37733mhbxxxfp peripheral ic
applications 7733 group users manual 17C39 (2) initial settings for related registers fig. 17.2.17 initial settings for related registers 17.2 serial i/o b7 b0 when the system clock (main clock) frequency = 16 mhz, transfer rate = 2 mhz. uart1 baud rate register (brg1) (address 39 16 ) 01 16 transmission is enabled. b7 b0 uart1 transmit/receive control register 1 (address 3d 16 ) xx x reception is disabled. xx0x1 b7 b0 uart1 transmission interrupt control register (address 73 16 ) 0 00 uart1 transmission interrupt is disabled. x pin p4 3 : output mode b7 b0 port p4 direction register (address c 16 ) 1 must be fixed to ?. clock synchronous serial i/o mode b7 b0 uart1 transmit/receive mode register (address 38 16 ) 0x x internal clock is selected. x0001 uart1 transmit/receive control register 0 (address 3c 16 ) cts / rts function is disabled. pin t x d 1 s output structure: cmos output transmit data is output at the falling edge of the transfer clock. lsb first brg1 count source: f 2 b7 b0 0 01 0 55 00 x: it may be ??or ?. pin p4 3 ? output level: ? b7 b0 port p4 register (address a 16 ) 0
applications 7733 group users manual 17C40 (3) approximate flowchart port p4 register 5555 1 555 2 ( address a 16 ) waiting for the start of transmission transmit data is set. main routine transmission buffer empty flag = ??? (bit 1 at address 3d 16 ) transmission register empty flag = ??? (bit 3 at address 3c 16 ) 1: transfer is completed. uart1 transmission buffer register [transmit data 2] ( address 3a 16 ) transmission buffer empty flag = ??? (bit 1 at address 3d 16 ) 1: transfer is completed. 1: transmission is completed. 1: transmission is completed. 0 0 0 0 16-bit data is transmitted by the 8 bits in two operations. waiting for the completion of transmission strobe signal? level: ?? transmit data is set. waiting for the completion of transmission waiting for the start of transmission uart1 transmission buffer register [transmit data 1] ( address 3a 16 ) waiting port p4 register ?xxx0xxx 2 (address a 16 ) strobe signal? level: ?? port p4 register ?xxx1xxx 2 (address a 16 ) strobe signal? level: ?? waiting port p4 register ?xxx0xxx 2 (address a 16 ) strobe signal? level: ?? nop instruction or others are used. ??level output time for a strobe signal is set. nop instruction or others are used. ??level output time for a strobe signal is set. transmission register empty flag = ?? (bit 3 at address 3c 16 ) x: it may be ??or ?. 17.2 serial i/o fig. 17.2.18 approximate flowchart
applications 7733 group users manual 17C41 17.3 watchdog timer a program runaway detection example with using the watchdog timer is described below. 17.3.1 program runaway detection example in this example, when the watchdog timer detect a program runaway, the microcomputer is reset. (1) specifications the main clock is the system clock and f(x in ) = 16 mhz. when an interval of 4.09 ms has passed after value fff 16 is set, the watchdog timer issues an interrupt request. (when writing to address 60 16 is not performed because of a program runa- way.) a when a watchdog timer interrupt request occurs, the microcomputer is reset. (software reset is applied.) (2) initial setting for related register 17.3 watchdog timer fig. 17.3.1 initial setting for related register watchdog timer count source: clock f 32 (in the case where f(x in ) = 16 mhz, a watchdog timer interrupt request occurs when an interval of 4.09 ms has passed after value ?ff 16 ?is set.) b7 b0 ?@ watchdog timer frequency selection flag (address 61 16 ) 1
applica tions 7733 group users manual 17C42 (3) approximate flowchart 17.3 watchdog timer fig. 17.3.2 approximate flowchart watchdog timer register 8-bit dummy data (address 60 16 ) main routine watchdog timer is initialized. watchdog timers value: fff 16 (note 1) watchdog timer interrupt routine software reset bit 1 (bit 3 at address 5e 16 ) rti watchdog timer interrupt request occurs. (detection of a program runaway) (note 2) microcomputer is resset. notes 1: the watchdog timer is initialized again from when the watch dog timer is initialized until the most significant bit of the watchdog timer becomes 0, in other words, until a watchdog timer interrupt request occurs. 2: when a program runaway occurs, there is a possibility that values of data bank register (dt), direct page register (dpr), and others are incorrect. when accessing the software reset bit by using an addressing mode which uses dt, dpr, and others, be sure to set values of dt, dpr, and others again.
applications 7733 group users manual 17C43 (4) precautions 1. the watchdog timer stops counting when the stp instruction is executed. for systems which use the watchdog timer, select stp instruction disabled with stp instruction option on mask rom order confirmation form. 2. the watchdog timer stops counting when the wit instruction is executed after the system clock stop bit at wait state (bit 5 at address 6c 16 ) is set to 1. 3. the contents of the processor interrupt priority level (ipl) is not initialized in the following cases: l when a value which is the same as the reset vector addresss contents is set to the watchdog timers vector address l when a program branches to the destination address at reset in a watchdog timer interrupt routine. reset of the microcomputer is realized by applying the software reset. 17.3 watchdog timer
applications 7733 group users manual 17C44 17.4 power saving power saving examples (in other words, examples to save power consumption) with the stop or wait mode used are described below. 17.4.1 power saving example with stop mode used in this example, power saving is realized by using the stop mode. the stop mode is terminated by using the key input interrupt function. (1) specifications the microcomputer operates in the single-chip mode. pins p5 0 to p5 3 are used as output pins for the key matrix scanning. input pins ( ki 0 to ki 3 ) for the key input interrupt function are used as key input pins. pins ki 0 to ki 3 are pulled high by using the pull-up function. a the initial output levels of pins p5 0 to p5 3 are l. ? when a key input interrupt request occurs owing to a key push, the key data is read-in. (this reading is surely performed independent of power saving.) ? in the stop mode, interrupts other than a key input interrupt are disabled. ? an external clock is used as the main clock. 17.4 power saving
applica tions 7733 group users manual 17C45 (2) initial settings for related registers 17.4 power saving fig. 17.4.1 initial settings for related registers pins ki 0 to ki 3 are pulled high. port p5 direction register (address d 16 ) pins p5 0 to p5 3 : output mode b7 b0 00 0 pins p5 4 to p5 7 ( ki 0 to ki 3 ): input mode 01 1 1 1 x: it may be 0 or 1. pins p5 0 to p5 3 s output (scan output) level: l b7 b0 port p5 register (address b 16 ) 00 0 0 key input interrupt function is selected. must be fixed to 0. b7 b0 port function control register (address 6d 16 ) 11 0 interrupt disable flag (i) b7 b0 int 2 /key input interrupt control register (address 7f 16 ) 0 00 interrupt priority level is set. (note that a value other th an 000 2 is set.) interrupt request bit: 0 (initialized) must be fixed to 0. 0: interrupt is enabled. must be fixed to 0. an external clock is selected as the main clock. watchdog timer is not used when the stop mode is terminated. oscillation circuit control register 1 (address 6f 16 ) (note) in the one time prom version or eprom version of the 7733 gr oup, this bit must be fixed to 1. (in the 7735 group, this bit must be fixed to 0. ) b7 b0 1 0 1 0 pin p6 4 /i nt 2 is not used for the key input interrupt. note: when writing a value to this register, write a value of 55 16 by executing the ldm instruction, and then write a desired value. (refer to figure 11.2.4. ) x x x x x
applica tions 7733 group users manual 17C46 fig. 17.4.2 approximate flowchart 17.4 power saving (3) approximate flowchart interrupts other than a key input interrupt are disabled. notes 1: when pin v ref and resistor ladder network are connected, current flows in to the resistor ladder network. when using the a-d converter after the stop mode is terminat ed, do as follows: q reconnect pin v ref and resistor ladder network. w and then, start a-d conversion after a period of 1 s or more passed. when a port is connected to an external device and so on, th ere is a possibility that current consumption increases according to the ports level. in order to avoid t his problem, do as follows: ?when output mode is selected: fix the ports level to a lev el where no current flows into the external. ?when input mode is selected : pull the port high or low vi a a resistor. (floating state is disabled.) key input interrupt request occurs. (key is pushed.) main routine stp v ref connection selection bit 1 (bit 5 at address 1f 16 ) pin v ref is disconnected from resistor ladder network. (note 1) port level is fixed. (note 2) stop mode is selected. bits 2 to 0 at addresses 70 16 to 7e 16 000 2 2: key input ( int 2 ) interrupt routine key data is read-in. register return processing rti port p5 registers bits which correspond to pins p5 0 to p5 3 0 (bits 0 to 3 at address b 16 ) scan output: l level port p5 registers bits which correspond to pins p5 0 to p5 3 0 (bits 0 to 3 at address b 16 ) scan output: l level register save processing
applications 7733 group users manual 17C47 (4) settings for performing power saving in memory expansion or microprocessor mode in the memory expansion or microprocessor mode, when saving power consumption, it is necessary to fix the i/o pins levels of the external bus and bus control signals in the stop mode. for this purpose, set the standby state selection bit to 1. 17.4 power saving
applica tions 7733 group users manual 17C48 note: regardless of this setting, in the following cases, pin 1 outputs l level in the stop mode: l when the signal output disable selection bit is set to 0 in the microprocessor mode l when the clock 1 output selection bit is set to 1 in the memory expansion mode stp v ref connection selection bit 1 (bit 5 at address 1f 16 ) pin v ref is disconnected from resistor ladder network. stop mode is selected. interrupt request occurs. port p0 register 00111111 2 (address 2 16 ) port p1 register 00000000 2 (address 3 16 ) port p2 register 00000000 2 (address 6 16 ) port p3 register 00001011 2 (address 7 16 ) levels of ports other than the above are fixed. signal output disable selection bit 1 (bit 6 at address 6c 16 ) i/o pins levels of external bus and bus control signals in the stop mode are set. (these levels can be set by the corresponding port registers bits.) in this example, i/o pins for l-active signals are set to h and the other pins are set to l. ports which correspond to i/o pins of external bus and bus control signals: output mode (this setting is done in order to output a value set to a port register in the stop mode) pin 1 s state in the stop mode is set (note) . in this example, l level output is set. pin e s output level in the stop mode is set. in this example, it is set to l. port p0 direction register ff 16 (address 4 16 ) port p1 direction register ff 16 (address 5 16 ) port p2 direction register ff 16 (address 8 16 ) port p3 direction register ff 16 (address 9 16 ) main routine port p4 registers bit which corresponds to p4 2 pin 0 (bit 2 at address a 16 ) port p4 direction registers bit which corresponds to p4 2 pin 1 (bit 2 at address c 16 ) standby state selection bit 1 (bit 0 at address 6d 16 ) standby state selection bit: 1 (in the stop mode, a value which is set to the corresponding port register is output from an i/o pin of the external bus or bus control signals.) fig. 17.4.3 fixing i/o pins levels of external bus and bus control signals (microprocessor mode) 17.4 power saving
applica tions 7733 group users manual 17C49 17.4.2 power saving example with wait mode used in this example, power saving is realized by using the wait mode. while power is saved, the clock function is realized by using the clock timer (timer b2). (1) specifications the microcomputer operates in the single-chip mode. the frequency of the sub clock (f(x cin )) = 32.768 khz. an external clock is used as the sub clock. a clock counting is performed by using the clock timer. (an i nterrupt request occurs every second.) ? when an int 0 interrupt request occurs (note) , the wait mode is terminated. note: an interrupt request occurs at every falling edge of the si gnal input from pin int 0 . ? in the wait mode, interrupts other than the following inter rupts are disabled. ?timer b2 interrupt ? int 0 interrupt ? an external input is used as the main clock. 17.4 power saving
applica tions 7733 group users manual 17C50 (2) initial settings for related registers fig. 17.4.4 initial settings for related registers x: it may be 0 or 1. b7 b0 timer b2 interrupt control register (address 7c 16 ) interrupt priority level is set. (note that a value other th an 000 2 is set.) 0 interrupt request bit: 0 (initialized) interrupt disable flag (i) 0: interrupt is enabled. b7 b0 int 0 interrupt control register (address 7d 16 ) interrupt priority level is set. (note that a value other th an 000 2 is set.) 0 interrupt request bit: 0 (initialized) 0 0 an interrupt request occurs at the falling edge. interval of the clock timers interrupt request occurrence: 1 second b15 b8 timer b2 register (addresses 55 16 and 54 16 ) 03 16 b7 b0 ff 16 settings for the clock timer b7 b0 timer b2 mode register (address 5d 16 ) x 01 0 1 x cin -x cout is selected. (sub clock is used.) b7 b0 oscillation circuit control register 0 (address 6c 16 ) 1 in the wait mode, clocks 2 to 512 are stopped. 1 x xx an external clock is selected as the main clock. watchdog timer is not used when the stop mode is terminated. b7 b0 oscillation circuit control register 1 (address 6f 16 ) 0 x1 1 1 an external clock is selected as the sub clock and p7 6 functions as a port. watchdog timer is not used when the stop mode is terminated. in the one time prom version or eprom version of the 7733 gr oup, this bit must be fixed to 1. (in 7735 group, this bit must be fixed to 0. ) must be fixed to 0. note: when writing a value to this register, write a value of 55 16 by executing the ldm instruction, and then write a desired value. (refer to figure 11.2.4. ) 17.4 power saving
applications 7733 group users manual 17C51 (3) approximate flowchart fig. 17.4.5 approximate flowchart (1) [f_wit]: flag used to determine whether an int 0 interrupt request has occurred or not main clock oscillation circuit: oscillating <> main routine system clock selection bit ? (bit 3 at address 6c 16 ) system clock: main clock sub clock <> v ref connection selection bit ? (bit 5 at address 1f 16 ) pin v ref is disconnected from resistor ladder network. (note 1) port level is fixed. (note 2) wait mode is selected. main clock stop bit ? (bit 2 at address 6c 16 ) main clock oscillation circuit: stopped <> main clock stop bit ? (bit 2 at address 6c 16 ) 0: int 0 interrupt [f_wit] ? clock timer interrupt request occurs. [f_wit] = ?? ? ?? clock timer interrupt wit int 0 interrupt request occurs. (by this setting, the wait mode is terminated only when an int 0 interrupt request occurs.) bits 2 to 0 at addresses 70 16 to 7b 16 , 7e 16 , and 7f 16 ?00 2 interrupts other than timer b2 and int 0 interrupts are disabled. timer b2 count start flag ? (bit 7 at address 40 16 ) clock timer starts counting . system clock selection bit ? (bit 3 at address 6c 16 ) system clock: sub clock main clock (note 3) <> <> <> <> <>: refer to figure 17.4.8. for notes 1 to 3 , refer to the next page. 17.4 power saving
applica tions 7733 group users manual 17C52 fig. 17.4.6 approximate flowchart (2) notes 1: when pin v ref and resistor ladder network are connected, current flows in to the resistor ladder network. when using the a-d converter after the wait mode is terminat ed, do as follows: reconnect pin v ref and resistor ladder network. and then, start a-d conversion after a period of 1 s or more passed. 2: when a port is connected to an external device and so on, th ere is a possibility that current consumption increases according to the ports level. in order to avoid this problem, do as follows: ?when output mode is selected: fix the ports level to a lev el where no current flows into the external. ?when input mode is selected: pull the port high or low via a resistor. (floating state is disabled.) 3: do not switch the system clock until oscillation of a clock which is input from the external is stabilized. timer b2 interrupt routine register save processing clock count register return processing rti int 0 interrupt routine register save processing [f_wit] 0 register return processing rti [f_wit]: flag used to determine whether an int 0 interrupt request has occurred or not 17.4 power saving
applica tions 7733 group users manual 17C52 fig. 17.4.6 approximate flowchart (2) notes 1: when pin v ref and resistor ladder network are connected, current flows in to the resistor ladder network. when using the a-d converter after the wait mode is terminat ed, do as follows: q reconnect pin v ref and resistor ladder network. and then, start a-d conversion after a period of 1 s or more passed. 2: when a port is connected to an external device and so on, th ere is a possibility that current consumption increases according to the ports level. in order to avoid this problem, do as follows: ?when output mode is selected: fix the ports level to a lev el where no current flows into the external. ?when input mode is selected: pull the port high or low via a resistor. (floating state is disabled.) 3: do not switch the system clock until oscillation of a clock which is input from the external is stabilized. timer b2 interrupt routine register save processing clock count register return processing rti int 0 interrupt routine register save processing [f_wit] 0 register return processing rti [f_wit]: flag used to determine whether an int 0 interrupt request has occurred or not 17.4 power saving w
applications 7733 group users manual 17C53 main clock sub clock system clock system clock selection bit main clock stop bit <> <> <> <> ? ? ? ? main clock sub clock main clock fig. 17.4.7 state of main clock, sub clock, and system clock 17.4 power saving
applica tions 7733 group users manual 17C54 17.5 timer b an application example of the clock timer (timer b) is descr ibed below. 17.5.1 application example of clock timer in this example, the clock timer is controlled by a clock of 32.768 khz. when the main power source is off, the clock timer can continue counting for the maximum o f approximate 45 days by using the backup power source and the internal connect function between timer s b1 and b2. (1) specifications main power source = 5 v to 2.75 v. backup power source = 2. 75 v to 2.2 v timer b2 uses the sub clock (32.768 khz) divided by 32 as t he count source and counts the time up to 1 minute. a timer b2 counts the power-source-off time up to the maximum of approximate 45 days, checking the timer b2s overflow signal. ? the clock counter is counted up each time timer b2 interrup t occurs, in other words, every 1 minute. ? when vcc is less than 2.75 v, in other words, when the main power source is off, the int 0 inputs level changes from h to l and the microcomputer enters t he wait mode at this falling edge. (refer to a in figure 17.5.2. ) ? in the wait mode (vcc = 2.2 v or more), only timers b2 and b1 do counting. (in this case, note that clock display is disabled and the timer b2 and b1 interrupts are disabled.) ? when vcc = 2.75 v or more in the wait mode, in other words, when the main power source is on, the int 0 inputs level changes from l to h and the wait mode is terminated at the int 0 inputs rise. (refer to b in figure 17.5.2. ) at this time, the following is done according to the timer b1s state. ?when no overflow has occurred in timer b1 (timer b1 interru pt request bit = 0), timer b1s value is added to the clock counters value which was obtained im mediately before the wait mode. ?when an overflow has occurred in timer b1, in other words, when a period of approximate 45 days or more has passed, a message for resetting time is display ed. ? when vcc = 2.2 v or less, the microcomputer enters the rese t state owing to the power source detection circuit. (refer to c in figure 17.5.2. ) and then, when vcc = 2.75 v or more, the microcomputer is released from reset state. (refer to d in figure 17.5.2. ) fig. 17.5.1 connection example detection voltage vcc reset int 0 vss x cin x cout 32.768 khz m37733mhbxxxfp power source detection circuit reset signal control signal clock display main power source (5 v) backup power source 17.5 timer b
applica tions 7733 group users manual 17C55 fig. 17.5.2 timing chart (2) structure of timer b block where timers b1 and b2 are in ternally connected figure 17.5.3 shows the structure of the timer b block. fig. 17.5.3 structure of timer b block 5 v 2.75 v 2.2 v 0 v vcc reset int 0 wait mode approx. 45.5 days (max.) ab c d main power source backup power source main clock : f(x in ) sub clock : f(x cin ) 1/32 clock timer fc 32 timer b2 reload register timer b1 reload register timer b1 counter timer b1 interrupt request bit timer b2 interrupt request bit event counter mode timer b1 internal connect selection bit clock prescaler (timer b2 counter) system clock (clock source for clocks f 2 to f 512 and internal clock ) 17.5 timer b
applications 7733 group users manual 17C56 (3) initial settings for related registers fig. 17.5.4 initial settings for related registers b15 b0 efff 16 clocks f 2 to f 512 are operating in the wait mode. (note 2) b7 b0 oscillation circuit control register 0 (address 6c 16 ) xx sub clock is used. (note 1) x 01 timer b1 mode register (address 5c 16 ) timer b2 mode register (address 5d 16 ) 01: count at the rising edge 01: event counter mode b7 b0 xx 1 x x 01 0 timer b1 interrupt control register (address 7b 16 ) no interrupt is requested. interrupt is disabled. b7 b0 0 0 00 timer b2 interrupt control register (address 7c 16 ) interrupt priority level (any value other than ?00 2 ? is set. no interrupt is requested. b7 b0 00 01 port function control register (address 6d 16 ) timers b1 and b2 are connected internally. must be fixed to ?. b7 b0 1 xxx x 0xx int 0 interrupt control register (address 7d 16 ) b7 b0 1 0 interrupt priority level (any value other than ?00 2 ? is set. 00 00 edge sense interrupt request bit is set at the falling edge ( ??to ??. no interrupt is requested. timer b2 register (addresses 55 16 and 54 16 ) b15 b0 ffff 16 timer b1 register (addresses 53 16 and 52 16 ) x: it may be ??or ?. notes 1: once this bit is set to ?,?it cannot be cleared to ?.? 2: when setting this bit to ?,?set ??to this bit immediately before the wit instruction is executed. furthermore, clear this bit to ??immediately after the wait mode is terminated. 17.5 timer b
applications 7733 group users manual 17C57 (4) approximate flowchart fig. 17.5.5 approximate flowchart clock prescaler is initialized. a value of ?0 16 ?is written to address 6f 16 by executing the ldm instruction. main routine int 0 interrupt control register ?1 16 (address 7d 16 ) oscillation circuit control register (address 6f 16 ) ?0 16 count start flag (address 40 16 ) ?0 16 timer b2 interrupt routine count-up processing for clock rti counted up every minute int 0 interrupt routine int 0 level/edge selection bit = ? (bit 4 at address 7d 16 ) timer b1 count start flag ? (bit 6 at address 40 16 ) by setting interrupt priority level, interrupts other than int 0 are disabled. system clock stop bit at wait state (bit 5 at address 6c 16 ) ? timer b1 count start flag ? (bit 6 at address 40 16 ) timer b1 register ffff 16 (addresses 53 16 and 52 16 ) timer b1 count start flag ? (bit 6 at address 40 16 ) timer b1 register fffe 16 (addresses 53 16 and 52 16 ) timer b1 count start flag ? (bit 6 at address 40 16 ) make int 0 interrupt priority level higher. wit instruction make int 0 interrupt priority level to the former level. rti int 0 interrupt control register (address 7d 16 ) ?1 16 timer b1 interrupt request bit = ? (bit 3 at address 7b 16 ) count value of timers b1 and b2 clock counter display urging user to set time again int 0 interrupt polarity is selected. (falling edge: ?? ?? int 0 interrupt polarity is selected. (rising edge: ?? ?? counting for timer b1 stops. counting for timer b1 starts. counting for timer b1 stops. 0: no request 0: no request 1: requested 1: rising edge (?? ?? 0: falling edge (?? ?? count start flag counting for timers b1 and b2 start 1: requested h by software initial settings, interrupt priority level is set as follows: l timer b2 < int 0 counting for timer b1 starts. timer b2 interrupt request bit = ? (bit 3 at address 7c 16 ) 17.5 timer b
applications 7733 group users manual 17C58 memo 17.5 timer b
chapter 18 chapter 18 low voltage version 18.1 performance overview 18.2 pin configuration 18.3 functional description 18.4 electrical characteristics 18.5 standard characteristics 18.6 applications
low voltage version 7733 group users manual 18C2 the low voltage version has the following characteristics: ? low power source voltage (2.7 to 5.5 v) ? wide operating temperature range (C40 to 85 c) the low voltage version is suitable to control equipment which is required to process a large amount of data with a little power dissipation, for example portable equipment which is driven by a battery and oa equip- ment. differences between the m37733mhlxxxhp, which is the low voltage version of the 7733 group, and the m37733mhbxxxfp are mainly described below. for the eprom mode of the built-in prom version, refer to chapter 19. built-in prom version.
low voltage version 7733 group users manual 18C3 items number of basic instructions the minimum instruction execution time main-clock frequency f(x in ) sub-clock frequency f(x cin ) memory size programmable input/output ports multi-function timers serial i/o a-d converter watchdog timer interrupts clock generating circuits power source voltage power consumption (in single-chip mode) port input/output characteristics memory expansion operating temperature range device structure package 18.1 performance overview table 18.1.1 shows the performance overview of the m37733mhlxxxhp. table 18.1.1 m37733mhlxxxhp performance overview rom ram ports p0Cp2, p4Cp8 port p3 timers a0Ca4 timers b0Cb2 uart0Cuart2 main-clock oscillation circuit sub-clock oscillation circuit input/output withstand voltage output current performance 103 333 ns (when f(x in ) = 12 mhz and main clock is system clock) 12 mhz (max.) (note) 32.768 khz (typ.) 124 kbytes 3968 bytes 8 bits 5 8 4 bits 5 1 16 bits 5 5 16 bits 5 3 (uart or clock synchronous serial i/o) 5 3 (10-bit successive approximation method) 5 1(8 channels) 12 bits 5 1 3 external, 16 internal (by software, one of interrupt priority levels 0 to 7 can be set for each interrupt.) built-in (externally connected to a ceramic reso- nator or a quartz-crystal oscillator) built-in (externally connected to a quartz-crystal oscillator) 2.7 v C 5.5 v 9 mw (when f(x in ) = 12 mhz, vcc = 3 v, and the main clock is the system clock, typ.) 22.5 mw (when f(x in ) = 12 mhz, vcc = 5 v, the main clock is the system clock, typ.) 90 m w (when f(x cin ) = 32 khz, vcc = 3 v, the sub clock is the system clock, and the main clock is stopped, typ.) 5 v 5 ma possible (maximum of 16 mbytes) C40 c to +85 c high-performance cmos silicon gate process 80-pin plastic molded fine-pitch qfp note: when the main clock division selection bit = 1, the maximum value of f(x in ) = 6 mhz. 18.1 performance overview
low volt age version 7733 group users manual 18C4 18.2 pin configuration 18.2 pin configuration figure 18.2.1 shows the m37733mhlxxxhp pin configuration. fig. 18.2.1 m37733mhlxxxhp pin configuration (top view) p3 2 / al e p3 1 / bh e p3 3 / hl da x ou t e cnv ss r eset p4 0 / ho l d 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 57 56 55 54 53 52 49 48 47 46 43 42 41 p8 6 / r x d 1 p8 7 / t x d 1 p0 0 / a 0 p0 1 / a 1 p0 2 / a 2 p0 3 / a 3 p0 4 / a 4 p0 5 / a 5 p0 6 / a 6 p0 7 / a 7 p1 0 / a 8 / d 8 p1 1 / a 9 / d 9 p1 2 / a 10 / d 10 p1 3 / a 11 / d 11 p1 4 / a 12 / d 12 p1 5 / a 13 / d 13 p1 6 / a 14 / d 14 p1 7 / a 15 / d 15 p2 0 / a 16 / d 0 p2 1 / a 17 / d 1 60 59 58 70 30 31 32 33 34 35 36 37 38 39 40 26 27 28 29 21 23 22 p4 1 / rdy p4 2 / 1 byt e x i n v ss p3 0 / r/ w p2 7 / a 23 / d 7 p2 6 / a 22 / d 6 p2 5 / a 21 / d 5 p2 4 / a 20 / d 4 p2 3 / a 19 / d 3 p2 2 / a 18 / d 2 p6 6 / tb 1 i n p6 5 / tb 0 i n p6 4 / i nt 2 p6 3 / i nt 1 p6 2 / i nt 0 p6 1 / ta 4 i n p6 0 / ta 4 ou t p5 7 / ta 3 i n / ki 3 p5 6 / ta 3 ou t / ki 2 p5 5 / ta 2 i n / ki 1 p5 4 / ta 2 ou t / ki 0 p5 3 / ta 1 i n p5 2 / ta 1 ou t p5 1 / ta 0 i n p5 0 / ta 0 ou t p4 7 p8 5 / cl k 1 p8 4 / ct s 1 / rt s 1 p8 3 / t x d 0 p8 2 / r x d 0 / cl k s 0 p8 1 / cl k 0 p8 0 / ct s 0 / rt s 0 / cl k s 1 v cc av cc v re f av ss v ss p7 7 / an 7 / x ci n p7 6 / an 6 / x co ut p7 5 / an 5 / ad tr g / tx d 2 p7 4 / an 4 / rx d 2 p7 3 / an 3 / cl k 2 p7 2 / an 2 / ct s 2 p7 1 / an 1 p7 0 / an 0 p6 7 / tb 2 i n / sub m 37733m h l xxxh p p4 3 p4 4 p4 5 p4 6 1 2 3 4 5 outline 80p6d-a 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 64 63 62 61 51 50 45 44 24 25
low voltage version 7733 group users manual 18C5 18.3 functional description 18.3 functional description the m37733mhlxxxhp has the same functions as the m37733mhbxxxfp except for the power-on reset conditions. power-on reset conditions are described below. for the other functions, refer to chapters 2. central processing unit to 14. clock generat- ing circuit.
low voltage version 7733 group users manual 18C6 18.3.1 power-on reset conditions figure 18.3.1 shows the power-on reset conditions and figure 18.3.2 shows an example of power-on reset circuit. for details of reset, refer to chapter 13. reset. fig. 18.3.1 power-on reset conditions fig. 18.3.2 example of power-on reset circuit 0v 0v vcc reset powered on here 2.7v 0.55v vcc gnd reset vcc c d m62003l m37733mhlxxxhp h delay time t d is about 10 ms when c d = 0.07 f. t d ? 0.152 5 c d [ s ], c d : [ f ] reset int i (i = 0 to 2) int (interrupt signal) (reset signal) h c d 5v 18.3 functional description
low voltage version 7733 group users manual 18C7 18.4 electrical characteristics 18.4 electrical characteristics the m37733mhlxxxhps electrical characteristics are described below. for the latest data, inquire of addresses described last ( contact addresses for further information) . 18.4.1 absolute maximum ratings absolute maximum ratings parameter power source voltage analog power source voltage input voltage input voltage output voltage power dissipation operating temperature storage temperature conditions ta = 25 c unit v v v v v mw c c ratings C0.3 to 7 C0.3 to 7 C0.3 to 12 C0.3 to vcc+0.3 C0.3 to vcc+0.3 200 C40 to 85 C65 to 150 ______ reset , cnvss, byte p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , v ref , x in p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , __ p8 0 Cp8 7 , x out , e symbol vcc avcc v i v i v o p d t opr t stg
low voltage version 7733 group users manual 18C8 18.4 electrical characteristics 18.4.2 recommended operating conditions recommended operating conditions (vcc = 2.7 to 5.5 v, ta = C40 to 85 c, unless otherwise noted) v v v v v v v v v v ma ma ma ma ma ma mhz khz power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage high-level input voltage high-level input voltage low-level input voltage low-level input voltage low-level input voltage high-level peak output current high-level average output current low-level peak output current low-level peak output current low-level average output current low-level average output current main-clock oscillation frequency (note 4) sub-clock oscillation frequency f(x in ) :operating f(x in ) :stopped, f(x cin ) = 32.768 khz p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnvss, byte, x cin (note 3) p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnvss, byte, x cin (note 3) p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 3 , p5 4 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p4 4 Cp4 7 , p5 0 Cp5 3 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 3 , p5 4 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p4 4 Cp4 7 , p5 0 Cp5 3 vcc avcc vss avss v ih v ih v ih v il v il v il i oh (peak) i oh (avg) i ol (peak) i ol (peak) i ol (avg) i ol (avg) f(x in ) f(x cin ) parameter symbol limits min. max. 5.5 5.5 2.7 2.7 vcc 0 0 32.768 typ. unit 0.8 vcc 0.8 vcc vcc vcc vcc 0.2 vcc 0.2 vcc 0.16 vcc C10 C5 10 16 5 12 12 50 0.5 vcc 0 0 0 notes 1: average output current is the average value of an interval of 100 ms. 2: the sum of i ol (peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i oh (peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i ol (peak) for ports p4, p5, p6, and p7 must be 100 ma or less, and the sum of i oh (peak) for ports p4, p5, p6, and p7 must be 80 ma or less. 3: limits v ih and v il for x cin are applied when the sub clock external input selection bit = 1. 4: the maximum value of f(x in ) = 6 mhz when the main clock division selection bit = 1.
low voltage version 7733 group users manual 18C9 18.4 electrical characteristics 18.4.3 electrical characteristics electrical characteristics (vcc = 5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz, unless otherwise noted) high-level output voltage high-level output voltage high-level output voltage high-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage hysteresis hysteresis reset hysteresis x in hysteresis x cin (when external clock is input) high-level input current low-level input current low-level input current ram hold voltage symbol parameter test conditions min. max. v v v v v v v v v v v v v m a m a m a ma v limits unit typ. vcc = 5 v, i oh = C10 ma vcc = 3 v, i oh = C1 ma vcc = 5 v, i oh = C400 m a vcc = 5 v, i oh = C10 ma vcc = 5 v, i oh = C400 m a vcc = 3 v, i oh = C1 ma vcc = 5 v, i oh = C10 ma vcc = 5 v, i oh = C400 m a vcc = 3 v, i oh = C1 ma vcc = 5 v, i ol = 10 ma vcc = 3 v, i ol = 1 ma vcc = 5 v, i ol = 16 ma vcc = 3 v, i ol = 10 ma vcc = 5 v, i ol = 2 ma vcc = 5 v, i ol = 10 ma vcc = 5 v, i ol = 2 ma vcc = 3 v, i ol = 1 ma vcc = 5 v, i ol = 10 ma vcc = 5 v, i ol = 2 ma vcc = 3 v, i ol = 1 ma vcc = 5 v vcc = 3 v vcc = 5 v vcc = 3 v vcc = 5 v vcc = 3 v vcc = 5 v vcc = 3 v vcc = 5 v, v i = 5 v vcc = 3 v, v i = 3 v vcc = 5 v, v i = 0 v vcc = 3 v, v i = 0 v v i = 0 v, without a pull-up transistor v i = 0 v, with a pull-up transistor when clock is stopped 2 0.5 1.8 1.5 0.45 1.9 0.43 0.4 1.6 0.4 0.4 1 0.7 0.5 0.4 0.4 0.26 0.4 0.26 5 4 C5 C4 C5 C4 C1.0 C0.35 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 p3 0 Cp3 2 _ e p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 , p4 0 Cp4 3 , p5 4 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 5 , p8 0 Cp8 7 p4 4 Cp4 7 , p5 0 Cp5 3 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 p3 0 Cp3 2 e p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnvss, byte p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 3 , p6 0 , p6 1 , p6 5 C p6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnvss, byte p5 4 Cp5 7 , p6 2 Cp6 4 hold , rdy , ta0 in Cta4 in , tb0 in Ctb2 in , int 0 C int 2 , ad trg , cts 0 , cts 1 , cts 2 , clk 0 , clk 1 , clk 2 , ki 0 C ki 3 v oh v oh v oh v oh v ol v ol v ol v ol v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i il i il v ram vcc = 5 v vcc = 3 v vcc = 5 v vcc = 3 v C0.5 C0.18 3 2.5 4.7 3.1 4.8 2.6 3.4 4.8 2.6 0.4 0.1 0.2 0.1 0.1 0.06 0.1 0.06 C0.25 C0.08 2
low voltage version 7733 group users manual 18C10 18.4 electrical characteristics limits vcc = 5 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 6 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 3 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 6 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 3 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 0.75 mhz), f(x cin ) : stopped, in operating (note 1) vcc = 3v, f(x in ) = 12 mhz (square waveform), f(x cin ) = 32.768 khz, when the wit instruction is executed (note 2) vcc = 3 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) vcc = 3 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when the wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped electrical characteristics (vcc= 5 v, vss = 0 v, ta = C40 to 85 c, unless otherwise noted) unit measuring conditions symbol parameter i cc power source current min. typ. 4.5 3 0.4 6 30 3 ma ma ma m a m a m a m a m a max. 9 6 0.8 12 60 6 1 20 notes 1: this is applied when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output disable selection bit = 1. 2: this is applied when the main clock external input selection bit = 1 and the system clock stop bit at wait state = 1. 3: this is applied when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4: this is applied when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1. 18.4.4 a-d converter characteristics a-d converter characteristics (vcc = avcc = 5 v, vss = avss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note) , unless otherwise noted) in single-chip mode, output pins are open, and the other pins are con- nected to vss. limits min. typ. max. resolution v ref = vcc 10 bits absolute accuracy v ref = vcc 3 lsb r ladder ladder resistance v ref = vcc 10 25 k w t conv conversion time 19.6 m s v ref reference voltage 2.7 vcc v v ia analog input voltage 0 v ref v symbol parameter measuring conditions unit note: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz.
low vol t age version 7733 group users manual 18C11 18.4 electrical characteristics limits ns ns ns ns ns ns 666 333 333 limits limits 18.4.5 internal peripheral devices timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. t c(ta) t w(tah) t w(tal) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width min. 250 125 125 max. ns ns ns unit symbol parameter t c(ta) t w(tah) t w(tal) tai in input cycle time (note 3) tai in input high-level pulse width (note 3) tai in input low-level pulse width (note 3) min. max. unit symbol parameter timer a input (gating input in timer mode) parameter limits timer a input (external trigger input in one-shot pulse mode) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width max. unit symbol min. 666 166 166 t c(ta) t w(tah) t w(tal) limits tai in input high-level pulse width tai in input low-level pulse width ns ns min. 166 166 max. t w(tah) t w(tal) unit parameter symbol t c(up) t w(uph) t w(upl) t su(upCt in ) t h(t in Cup) tai out input cycle time tai out input high-level pulse width tai out input low-level pulse width tai out input setup time tai out input hold time ns ns ns ns ns min. max. unit symbol parameter timer a input (up-down input in event counter mode) timer a input (external trigger input in pulse width modulation mode) 3333 1666 1666 666 666 timer a input (count input in event counter mode) data formula (min.) data formula (min.) 8 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) (note 2) (note 2) (note 2) 8 5 10 9 2 5 f(f 2 ) (note 2) notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 3: the tai in input cycle time must be 4 cycles of a count source or more . the tai in input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively.
low voltage version 7733 group users manual 18C12 18.4 electrical characteristics limits max. m s ns ns unit symbol parameter timer a input (two-phase pulse input in event counter mode) min. 2 500 500 measuring conditions taj in input cycle time taj in input setup time taj out input setup time t c(ta) t su(taj in -taj out ) t su(taj out -taj in ) note: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz.
low vol t age version 7733 group users manual 18C13 18.4 electrical characteristics internal peripheral devices tai in input t c(ta) t w(tah) t w(tal) tai out input (up-down input) t c(up) t w(uph) t w(upl) tai in input (when fall count is selected) tai in input (when rise count is selected) tai out input (up-down input) t h(t in Cup) t su(upCt in ) l count input in event counter mode l gating input in timer mode l external trigger input in one-shot pulse mode l external trigger input in pulse width modulation mode l up-down input and count input in event counter mode measuring conditions ?v cc = 2.7 to 5.5 v ?input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc t su(taj in Ctaj out ) taj in input taj out input t su(taj out Ctaj in ) t su(taj in Ctaj out ) t su(taj out Ctaj in ) l two-phase pulse input in event counter mode t c(ta)
low volt age version 7733 group users manual 18C14 18.4 electrical characteristics ns ns ns ns ns ns ns ns ns ns min. 666 333 333 max. min. 666 333 333 timer b input (count input in event counter mode) t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) min. max. ns ns ns ns ns ns limits unit symbol tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width t c(tb) t w(tbh) t w(tbl) ns ns ns limits unit symbol parameter timer b input (pulse period measurement mode) parameter tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edges count) tbi in input high-level pulse width (both edges count) tbi in input low-level pulse width (both edges count) 250 125 125 500 250 250 timer b input (pulse width measurement mode) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width limits unit symbol parameter max. ad trg input cycle time (minimum allowable trigger) ad trg input low-level pulse width min. max. ns ns limits unit parameter symbol t c(ad) t w(adl) a-d trigger input 1333 166 serial i/o clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width txd i output delay time txd i hold time rxd i input setup time rxd i input hold time t c(ck) t w(ckh) t w(ckl) t d(cCq) t h(cCq) t su(dCc) t h(cCd) min. max. 100 limits unit symbol parameter 333 166 166 0 65 75 data formula (min.) data formula (min.) 8 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) (note 2) (note 2) (note 2) notes 1: the tbi in input cycle time must be 4 cycles of a count source or more . the tbi in input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 8 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 )
low voltage version 7733 group users manual 18C15 18.4 electrical characteristics ns ns ns min. 250 250 250 external interrupt int i input, key input interrupt ki i input int i input high-level pulse width int i input low-level pulse width ki i input low-level pulse width t w(inh) t w(inl) t w(kil) max. limits unit symbol parameter measuring conditions ? cc = 2.7 to 5.5 v ?nput timing voltage ?utput timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc : v ol = 0.8 v, v oh = 2.0 v tbi in input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) ad trg input t w(inl) t w(inh) int i input t c(ck) t w(ckh) t w(ckl) t h(c?) t su(d?) clk i input txd i output rxd i input t d(c?) t h(c?) t w(kil) ki i input internal peripheral devices
low voltage version 7733 group users manual 18C16 18.4 electrical characteristics 18.4.6 ready and hold timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. limits t su(rdyC f 1 ) t su(holdC f 1 ) t h( f 1 Crdy) t h( f 1 Chold) max. ns ns ns ns min. parameter symbol unit 80 80 0 0 note: this is applied to the case where the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz, unless otherwise noted) ns min. max. 120 limits unit conditions parameter fig. 18.4.1 symbol _____ hlda output delay time t d( f 1 Chlda) ____ rdy input setup time _____ hold input setup time ____ rdy input hold time _____ hold input hold time
low vol t age version 7733 group users manual 18C17 18.4 electrical characteristics 1 with no wait 1 with wait rdy input ready e output e output rdy input t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) measuring conditions ?v cc = 2.7 to 5.5 v ?input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 hold input hlda output t h( 1 Chold) t d( 1 Chlda) t su(holdC 1 ) hold t d( 1 Chlda)
low voltage version 7733 group users manual 18C18 18.4.7 single-chip mode timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. t d(eCp0q) t d(eCp1q) t d(eCp2q) t d(eCp3q) t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) port p0 data output delay time port p1 data output delay time port p2 data output delay time port p3 data output delay time port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time ns ns ns ns ns ns ns ns ns unit symbol max. 300 300 300 300 300 300 300 300 300 min. limits parameter switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 2) , unless otherwise noted) conditions fig. 18.4.1 note: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. t c t w(h) t w(l) t r t f t su(p0dCe) t su(p1dCe) t su(p2dCe) t su(p3dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp0d) t h(eCp1d) t h(eCp2d) t h(eCp3d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits unit parameter 83 33 33 200 200 200 200 200 200 200 200 200 0 0 0 0 0 0 0 0 0 external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time port p0 input setup time port p1 input setup time port p2 input setup time port p3 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p0 input hold time port p1 input hold time port p2 input hold time port p3 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time symbol max. 15 15 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: when the main clock division selection bit = 1, the minimum value of t c = 166 ns. 3: when the main clock division selection bit = 1, values of t w (h) /t c and t w (l) /t c must be set to values from 0.45 through 0.55. 18.4 electrical characteristics
low vol t age version 7733 group users manual 18C19 t d(eCp0q) t su(p0dCe) t h(eCp0d) t d(eCp1q) t su(p1dCe) t h(eCp1d) t d(eCp2q) t su(p2dCe) t h(eCp2d) t d(eCp3q) t su(p3dCe) t h(eCp3d) t w(h) t c t r t f e port p0 output port p0 input port p1 output port p1 input port p2 output port p2 input port p3 output port p3 input x in t d(eCp4q) t su(p4dCe) t h(eCp4d) t d(eCp5q) t su(p5dCe) t h(eCp5d) t d(eCp6q) t su(p6dCe) t h(eCp6d) t d(eCp7q) t su(p7dCe) t h(eCp7d) t d(eCp8q) t su(p8dCe) t h(eCp8d) port p4 output port p4 input port p5 output port p5 input port p6 output port p6 input port p7 output port p7 input port p8 output port p8 input t w(l) single-chip mode measuring conditions ?v cc = 2.7 to 5.5 v ?input timing voltage ?output timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc : v ol = 0.8 v, v oh = 2.0 v 18.4 electrical characteristics
low volt age version 7733 group users manual 18C20 parameter address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time e pulse width floating start delay time floating release delay time bhe output delay time r/ w output delay time bhe hold time r/ w hold time f 1 output delay time 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 18.4.8 memory expansion mode and microprocessor mode : with no wait timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits typ. data formula (min.) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) C 63 C 63 C 43 C 43 C 73 symbol t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1 ) C 43 C 35 C 30 C 63 C 63 C 50 C 50 conditions fig. 18.4.1 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 1 5 10 9 2 5 f(f 2 ) 2 5 10 9 2 5 f(f 2 ) 90 10 30 t c t w(h) t w(l) t r t f t su(dCe) t h(eCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 83 33 33 80 0 parameter max. 15 15 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: when the main clock division selection bit = 1, the minimu m value of t c = 166 ns. 3: when the main clock division selection bit = 1, values of t w (h) /t c and t w (l) /t c must be set to values from 0.45 through 0.55. min. 20 20 40 40 10 9 4 40 131 53 20 20 33 33 0 18.4 electrical characteristics
low vol t age version 7733 group users manual 18C21 t h(aleCa) t h(eCdq) t d(eCdq) address/data output a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 (byte = l) data address t d(aCe) t pxz(eCdz) t pzx(eCdz) t d(eC f 1 ) t w(el) t h(eCan) t d(eC f 1 ) t w(ale) t d(bheCe) t h(eCbhe) t d(r/wCe) t h(eCr/w) x in 1 e address output a 0 Ca 7 a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l), d 0 Cd 7 (byte = h) ale output bhe output r/w output address measuring conditions ?v cc = 2.7 to 5.5 v ?output timing voltage ?data input : v ol = 0.8 v, v oh = 2.0 v : v il = 0.16 v cc , v ih = 0.5 v cc with no wait (wait bit = 1) t d(eC f 1 ) t d(anCe) t su(dCe) t h(eCd) t d(aleCe) t d(bheCe) t d(r/wCe) address memory expansion mode and microprocessor mode : t w(h) t w(l) t c t f t r port pi output (i = 4C8) port pi input (i = 4C8) t d(eCpiq) t su(pidCe) t h(eCpid) t w(ale) t w(el) t d(anCe) t d(aleCe) t h(eCan) t h(eCbhe) t h(eCr/w) t f t r t c t w(h) t w(l) (write) (read) t d(eC f 1 ) t su(aCale) address 18.4 electrical characteristics
low volt age version 7733 group users manual 18C22 parameter address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time e pulse width floating start delay time floating release delay time bhe output delay time r/ w output delay time bhe hold time r/ w hold time f 1 output delay time 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 18.4.9 memory expansion mode and microprocessor mode : with wait 1 timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits typ. data formula (min.) min. 20 20 40 40 10 9 4 40 298 53 20 20 33 33 0 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) C 63 C 63 C 43 C 43 C 73 symbol t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1 ) 1 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) C 43 C 35 C 30 C 63 C 63 C 50 C 50 90 10 30 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . t c t w(h) t w(l) t r t f t su(dCe) t h(eCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 83 33 33 80 0 parameter max. 15 15 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: when the main clock division selection bit = 1, the minimu m value of t c = 166 ns. 3: when the main clock division selection bit = 1, values of t w (h) /t c and t w (l) /t c must be set to values from 0.45 through 0.55. conditions fig. 18.4.1 18.4 electrical characteristics
low vol t age version 7733 group users manual 18C23 when external memory area is accessed with wait 1 (wait bit = 0 and wait selection bit = 1) t c t h(eC r/w) t d(r/wCe) t d(bheCe) t h(eC bhe) t w(ale) t h(eCan) t w(el) t d(eC f 1 ) t d(eC f 1 ) address x in 1 e address output a 0C a 7 , a 8C a 15 (byte = h) data input d 8C d 15 (byte = l) d 0C d 7 (byte = h) ale output bhe output r/w output t h(eC bhe) t d(aleCe) t su(dCe) t h(eCd) t d(anCe) t d(eC f 1 ) address memory expansion mode and microprocessor mode : port pi output (i = 4C8) port pi input (i = 4C8) t d(eCpiq) t su(pidCe) t h(eCpid) t w(h) t w(l) t d(eCdq) t h(aleCa) t h(eCdq) address/data output a 16 /d 0C a 23 /d 7 , a 8 /d 8C a 15 /d 15 (byte = l) data t pxz(eCdz) t pzx(eCdz) t d(eC f 1 ) t w(el) t h(eCan) t d(anCe) t d(aleCe) t w(ale) t r t f t w(l) t w(h) t r t f t c t d(r/wCe) t d(bheCe) t h(eC r/w) measuring conditions ? v cc = 2.7 to 5.5 v ? output timing voltage ? data input : v ol = 0.8 v, v oh = 2.0 v : v il = 0.16 v cc , v ih = 0.5 v cc t su(aCale) t d(aCe) address address 18.4 electrical characteristics
low volt age version 7733 group users manual 18C24 1 5 10 9 2 5 f(f 2 ) 3 5 10 9 2 5 f(f 2 ) 3 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 18.4.10 memory expansion mode and microprocessor mode : with wait 0 timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits typ. data formula (min.) min. 182 162 40 123 93 40 40 40 298 53 182 182 33 33 0 3 5 10 9 2 5 f(f 2 ) 3 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 2 5 10 9 2 5 f(f 2 ) 2 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) C 68 C 88 C 43 C 43 C 73 C 43 C 43 symbol t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1 ) C 43 C 35 C 30 C 68 C 68 C 50 C 50 90 10 30 parameter address output delay time address output delay time address hold time ale puls e width address output set up time address hold time ale output delay time data output delay time data hold time e pulse width floating start delay time floating release delay time bhe output delay time r/ w output delay time bhe hold time r/ w hold time f 1 output delay time conditions fig. 18.4.1 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 1 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) t c t w(h) t w(l) t r t f t su(dCe) t h(eCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 83 33 33 80 0 parameter max. 15 15 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: when the main clock division selection bit = 1, the minimu m value of t c = 166 ns. 3: when the main clock division selection bit = 1, values of t w (h) /t c and t w (l) /t c must be set to values from 0.45 through 0.55. 18.4 electrical characteristics
low vol t age version 7733 group users manual 18C25 x in 1 address output a 0 Ca 7 , a 8 Ca 15 (byte = h) ale output e bhe output r/w output t c data input d 8 Cd 15 (byte = l) d 0 Cd 7 (byte = h) t d(eC f 1 ) t d(eC f 1 ) t w(el) t h(eCan) t w(ale) t d(bheCe) t h(eCbhe) t d(r/wCe) t h(eCr/w) address measuring conditions ?v cc = 2.7 to 5.5 v ?output timing voltage ?data input : v ol = 0.8 v, v oh = 2.0 v : v il = 0.16 v cc , v ih = 0.5 v cc t d( e C 1 ) t d( an C e) t su ( d C e) t h( e C d) t d( al e C e) t h( e C bh e) t h( e C r/ w) address/data output a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 (byte = l) t h(eCdq) t h(aleCa) t d(eCdq) t su(aCale) data t p xz( e C dz ) t p zx( e C dz ) address address port pi output (i = 4C8) port pi input (i = 4C8) t d(eCpiq) t su(pidCe) t h(eCpid) t w(l) t w(h) t r t f t w( el ) t f t r t w( l) t w( h) t c t d( e C 1 ) t d(anCe) t d(aleCe) t h( e C an ) t w( al e) t d( bh e C e) t d( r/ w C e) t d(aCe) when external memory area is accessed with wait 0 (wait bit = 0 and wait selection bit = 0) memory expansion mode and microprocessor mode : address 18.4 electrical characteristics
low volt age version 7733 group user? manual 18?6 __ 18.4.11 measuring circuit for ports p0 to p8 and pins f 1 and e _ fig. 18.4.1 measuring circuit for ports p0 to p8 and pins f 1 and e p0 p1 p2 p3 p4 p5 p6 p7 p8 50 pf e 18.4 electrical characteristics f 1
7733 group users manual low voltage version 18C27 (2) n-channel i ol Cv ol characteristics 18.5 standard characteristics standard characteristics described below are just examples of the m37733mhlxxxhps characteristics and are not guaranteed. for rated values, refer to section 18.4 electrical characteristics. 18.5.1 programmable i/o port (cmos output) standard characteristics: ports p0 to p3, p4 0 Cp4 3 ,p5 4 Cp5 7 , p6, p7, and p8 (1) p-channel i oh Cv oh characteristics v oh [v] p-channel power source voltage v cc = 3 v 20.0 16.0 12.0 4.0 8.0 0 0.6 1.2 1.8 2.4 3.0 i oh [ma] ta = 25 ? ta = 85 ? n-channel power source voltage v cc = 3 v 20.0 16.0 12.0 8.0 4.0 0 0.6 1.2 1.8 2.4 3.0 v ol [v] i ol [ma] ta = 25 ? ta = 85 ? 18.5 standard characteristics
7733 group users manual 18C28 low voltage version 18.5.2 programmable i/o port (cmos output) standard characteristics: ports p4 4 to p4 7 and p5 0 to p5 3 (1) p-channel i oh Cv oh characteristics (2) n-channel i ol Cv ol characteristics v oh [v] p-channel power source voltage v cc = 3 v 20.0 16.0 12.0 4.0 8.0 0 0.6 1.2 1.8 2.4 3.0 i oh [ma] ta = 25 ? ta = 85 ? n-channel power source voltage v cc = 3 v 20.0 16.0 12.0 8.0 4.0 0 0.6 1.2 1.8 2.4 3.0 v ol [v] i ol [ma] ta = 25 ? ta = 85 ? 18.5 standard characteristics
7733 group users manual low vol t age version 18C29 18.5.3 iccCf(x in ) standard characteristics (1) iccCf(x in ) characteristics on operating and at reset (2) iccCf(x in ) characteristics during wait mode 0 1 2 3 4 0 2 4 6 8 10 12 14 ?measuring conditions (vcc = 3 v, ta = 25 c, f(x in ):square waveform input, single-chip mode) ?register setting conditions oscillation circuit control register 1 = 02 16 (main clock is input from the external.) on operating (cpu + peripheral devices) f(x in ) [mhz] icc [ma] on operating (cpu) 0 0.2 0.4 0.6 0.8 1 02 46 8 1 0 1 2 1 4 ?measuring conditions (vcc = 3 v, ta = 25 c, f(x in ):square waveform input, single-chip mode) ?register setting conditions oscillation circuit control register 0 = 20 16 (in wait mode, clocks f 2 to f 512 are stopped.) oscillation circuit control register 1 = 02 16 (main clock is input from the external.) or 00 16 (main-clock oscillation circuit is operating by itself.) f(x in ) [mhz] icc [ma] cc 1 = 0 cc 1 = 1 cc 1 : main clock external input selection bit (bit 1 of oscillat ion circuit control register 1) 18.5 standard characteristics
7733 group users manual 18C30 low voltage version 18.5.4 a-d converter standard characteristics the lower line of the graph indicate the absolute precision errors. these are expressed as the deviation from the ideal value when the output code changes. for example, the change in output code from 0e 16 to 0f 16 should occur at 36.25 mv, but the measured value is 0.3 mv. accordingly, the measured point of change is 36.25 + 0.3 = 36.55 mv. the upper line of the graph indicate the input voltage width for which the output code is constant. for example, the measured input voltage width for which the output code is 0f 16 is 2.2 mv. accordingly, the differential non-linear error is 2.2 C 2.5 = C0.3 mv (C0.12 lsb). [measuring conditions] ?vcc = avcc = 3 v, ?v ref = 2.56 v, ?f(x in ) = 12 mhz, ?temp. = 25 c 18.5 standard characteristics
7733 group users manual low voltage version 18C31 18.5 standard characteristics
7733 group users manual 18C32 low volt age version 18.6 applications some application examples of connecting external memorys for the low voltage version are described bellow. applications shown here are just examples. modify the desire d application to suit the users need and make sufficient evaluation before actually using it. 18.6.1 memory expansion the following items of the low voltage version are the same as section 17.1 memory expansion, but a part of the calculation way and constants for parameters i s different: ?memory expansion model ?calculation way for address access time of external memory ?bus timing ?memory expansion way address access time of external memory t a(ad) t a(ad) = t d(a-e) + t w(el) C t su(d-e) C (address decode time ] 1 + address latch delay time ] 2 ) address decode time ] 1 : time necessary for validating a chip select signal after an address is decoded address latch delay time ] 2 : delay time necessary for latching an address (this is not necessary on the minimum model.) data setup time of external memory for writing data t su(d) t su(d) = t w(el) C t d(eCdq) table 18.6.1 lists the calculation formulas and constants fo r each parameter of the low voltage version. figure 18.6.1 shows the relationship between t a(ad) and 2 5 f(f 2 ). figure 18.6.2 shows the relationship between t su(d) and 2 5 f(f 2 ). table 18.6.1 calculation formulas and constants for each par ameter (unit : ns) wait 1 0 1 wait 0 0 0 80 90 10 C 30 C 88 C 35 C 63 C 35 no wait 1 0 or 1 3 5 10 9 2 5 f(f 2 ) 4 5 10 9 2 5 f(f 2 ) 2 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) 1 5 10 9 2 5 f(f 2 ) wait bit : bit 2 at address 5e 16 wait selection bit : bit 0 at address 5f 16 note: this is applied to the case where the system clock selectio n bit (bit 3 at address 6c 16 ) = 0. software wait wait bit wait selection bit t d(a-e) t w(el) t su(d-e) t su(e-dq) t pxz(e-dz) t pzx(e-dz) 18.6 applications
7733 group users manual low vol t age version 18C33 fig. 18.6.1 relationship between t a(ad) and 2 5 f( f 2 ) fig. 18.6.2 relationship between t su(d) and 2 5 f( f 2 ) 2 3 4 5 6 7 8 9 10 11 12 0 200 400 600 800 1000 1200 1400 1600 1800 2000 1875 1208 875 675 541 446 375 319 275 238 208 875 541 375 275 208 160 125 75 56 41 no wait wait 1 or wait 0 is valid. 97 external clock input frequency 2 5 f(f 2 ) [mhz] data setup time tsu (d) [ns] 2 3 4 5 6 7 8 9 10 11 12 0 500 1000 1500 2000 2500 3000 3500 3297 2130 1547 1197 963 797 672 574 497 433 380 2322 1488 1072 822 655 536 447 377 322 276 238 822 572 422 322 250 197 155 122 94 72 no wait wait 1 is valid. wait 0 is valid. 1322 memory access time ta (ad) [ns] external clock input frequency 2 5 f(f 2 ) [mhz] ] address decode time and address latch delay time are not con sidered. 18.6 applications
7733 group users manual 18C34 low volt age version fig. 18.6.3 memory expansion example on minimum model 18.6.2 memory expansion example on minimum model figure 18.6.3 shows a memory expansion example on the minimu m model (with external ram) and figure 18.6.4 shows the corresponding timing diagram. in example, a n atmel companys eprom (at27lv256r) is used as the external rom. in figure 18.6.3, the circuit condition is no wait. 0000 16 0080 16 external rom area (at27lv256r) sfr area internal ram area external ram area (m5m5256cfp) memory map a 15 a 0 to a 14 d 0 to d 7 ac04 ac32 8 mhz x in x out m37733s4lhp byte r/w e bhe open a 0 to a 14 d 0 to d 7 oe m5m5256cfp-10vll oe rd wr ce s at27lv256r-15di ac04 ac32 circuit conditions : no wait, a 0 to a 14 vcc = 3.3 0.3 v ] 1 ] 2 ] 3 ] 1 8000 16 ffff 16 0880 16 ] 1 make sure that the propagation delay time is 35 ns or less . ] 2 make sure that the propagation delay time is 47 ns or less . ] 3 make sure that the propagation delay time is 62 ns or less . w 1 = , , , or 2 f(x in ) 8 f(x in ) 16 f(x in ) 2 f(x cin ) dq 1 to dq 8 18.6 applications
7733 group users manual low voltage version 18C35 fig. 18.6.4 timing diagram on minimum model d 0 to d 7 external memory data output a a d s, oe l at reading 215 (min.) 62 (min.) 10 (max.) 95 (min.) t su (p2d-e) 3 80 rom : 25 (max.) ram : 30 (max.) e ac32 (t plh ) ac32 (t phl ) t a (s) , t a (oe) e a 1 to a 14 aa l at writing d 0 to d 7 aa s, w d 215 (min.) t su (d) 3 40 (unit : ns) ac32 (t phl ) ac32 (t plh ) 90 (max.) 82 (min.) a 1 to a 14 a t a (ad) t a (ce) ac04 (t phl ) ce 62 (min.) a 18.6 applications
7733 group users manual 18C36 low volt age version 18.6.3 memory expansion example on medium model a figure 18.6.5 shows a memory expansion example on the medium model a. figure 18.6.6 shows the corresponding timing diagram. fig. 18.6.5 memory expansion example on medium model a internal rom area circuit conditions : no wait a 16 /d 0 to a 23 /d 7 10 mhz x in x out m37733mhlxxxhp byte r/w e open bhe a 0 to a 16 oe s1 m5m51008afp-10vll a 0 to a 15 cnv ss w external rom area (m5m51008afp) memory map 000000 16 000080 16 ] dq 1 to dq 8 ] make sure that the propagation delay time is 22 ns or less. 03ffff 16 000fff 16 01ffff 16 020000 16 internal ram area sfr area dq le s2 ale a 16 a 17 ac573 d 0 Cd 7 v cc = 3.3 0.3 v 1 = , , , or 2 f(x in ) 8 f(x in ) 16 f(x in ) 2 f(x cin ) 18.6 applications
7733 group users manual low voltage version 18C37 fig. 18.6.6 timing diagram on medium model a a 0 to a 15 aa l at writing e, oe, s1 a 16 / d 0 to a 23 / d 7 a 16 , a 17 , s2 aa d 165 (min.) 90 (max.) 37 (min.) t su (d) 3 40 (unit : ns) r/w, we ac573 (t phl ) a 16 / d 0 to a 23 / d 7 external memory data output aa d l at reading e, oe, s1 165 (min.) 37 (min.) 10 (max.) 70 (min.) t a (oe), t a (s1) t su (p1d/p2d-e) 3 80 t a (s2) ac573 (t plh ) a 0 to a 15 aa a 16 , a 17 , s2 ac573 (t phl ) 35 (max.) 57 (min.) t a (a) + ac573 18.6 applications
7733 group users manual 18C38 low volt age version 18.6.4 memory expansion example on maximum model figure 18.6.7 shows a memory expansion example on the maximu m model. figure 18.6.8 shows the corresponding timing diagram. in this example, atmel company s eproms (at27lv256r) are used as the external roms. in figure 18.6.7, the circuit condition is no wait. fig. 18.6.7 memory expansion example on maximum model r/w e bhe ac04 8 mhz x in x out m37733s4lhp byte a 17 a 8 to a 16 even data bus odd data bus ac573 ac32 rd d 0 to d 7 d 8 to d 15 address bus wo a 1 to a 15 d 0 to d 7 oe a 0 to a 14 ce a 1 to a 15 a 0 to a 14 d 0 to d 7 oe ce we at27lv256r-15di ac32 dq le dq le a 16 /d 0 to a 17 /d 1 a 1 to a 16 d 0 to d 7 m5m51008afp-10vll a 0 to a 15 dq 1 to dq 8 oe w a 1 to a 16 d 8 to d 15 a 0 to a 15 dq 1 to dq 8 oe w ac32 circuit conditions : no wait 03ffff 16 external rom area (at27lv256r 5 2) sfr area internal ram area memory map 000000 16 000080 16 000880 16 external ram area (m5m51008afp 5 2) 00ffff 16 020000 16 not used ac04 s 1 s 1 a 1 to a 7 a 8 /d 8 to a 15 /d 15 ale d 2 to d 7 a 16 ] 1 make sure that the propagation delay time is 47 ns or less . ] 2 make sure that the propagation delay time is 50 ns or less . ] 3 make sure that the propagation delay time is 62 ns or less . a 16 a 16 vcc = 3.3 0.3 v s 2 s 2 ] 1 ] 3 ] 2 ] 2 a 0 1 = , , , or 2 f(x in ) 8 f(x in ) 16 f(x in ) 2 f(x cin ) 18.6 applications
7733 group users manual low vol t age version 18C39 fig. 18.6.8 timing diagram on maximum model a 1 to a 7 l at writing e a 8 / d 8 to a 15 / d 15 a 16 / d 0 , d 1 to d 7 a d 215 (min.) 90 (max.) 62 (min.) ac32 (t phl ) t su (d) 3 40 ( un i t : ns ) w ac32 (t plh ) a 8 / d 8 to a 15 / d 15 a 16 / d 0 external memory data output a d l at reading e 215 (min.) 62 (min.) 10 (max.) 95 (min.) t a (ad) , t a (ce) t su (p1d/p2d-e) 3 80 oe ac32 (t plh ) a 1 to a 7 a ce, s1 t a (oe) ac573 (t phl ) ce ac32 (t phl ) rom : 25 (max.) ram : 35 (max.) 82 (min.) t a (s1) ac04 (t phl ) s1 s1 ac573 (t phl ) + ac04 (t phl ) 18.6 applications a a a a a
7733 group users manual 18C40 low volt age version 18.6.5 ready generating circuit example when validating wait only for a certain area (for example, rom area) in figures 18.6.3 to 18.6.8, use the ready function. figure 18.6.9 shows a ready generating circuit example. fig. 18.6.9 ready generating circuit example m37733mhlxxxhp cs 1 a 8 to a 23 (d 0 to d 15 ) a 0 to a 7 ac74 d t q 1 rdy e ac32 ac32 ac04 address bus data bus address latch circuit address decode circuit cs 2 wait generated by the ready function is inserted only to an area where accessed by signal cs 2 . circuit conditions : f(x in ) 10.8 mhz, no wait, 1 e 1 cs 2 q rdy t c t d(e- 1 ) t su(rdy- 1 ) propagation delay time of ac32 (max. : 11.9 ns) ] ] condition to satisfy the relationship of t su(rdy- 1 ) 3 80 ns in the left timing chart is t accordingly, when f(x in ) 10.8 mhz, this example satisfies the relationship of t su(rdy- 1 ) 3 80 ns. : wait generated by the ready function 1 = , , , or 2 f(x in ) 8 f(x in ) 16 f(x in ) 2 f(x cin ) v cc = 3.0 to 5.5 v c 3 91.9 ns. 18.6 applications
chapter 19 chapter 19 built-in prom version 19.1 eprom mode 19.2 usage precaution
built-in prom version 7733 group users manual 19-2 in the prom version, programming to the built-in prom is possible by using a general-purpose prom programmer and a programming adapter which is suitable for the microcomputer. the built-in prom version has the following two types : l one time prom version programming to the prom is possible once. this version is suitable for a small quantity of and various production. l eprom version programming to the prom is possible repeatedly because a program can be erased by exposing the erase window on the top of the package to an ultraviolet light source. this version can be used only for program development (evaluation only). the built-in prom version differs from the mask rom version in the following: ? the built-in prom version has a built-in prom. ? bit 3 of the oscillation circuit control register 1 (address 6f 16 ) of the built-in prom version is 1 at reset. ? bit 3 of the oscillation circuit control register 1 (address 6f 16 ) of the built-in prom version must be fixed to 1.
built-in prom version 7733 group users manual 19-3 19.1 eprom mode 19.1 eprom mode the built-in prom version has the following two modes : l normal operating mode the microcomputer has the same function as the mask rom version. l eprom mode programming to the built-in prom can be performed. the built-in prom version enters this mode ______ when l level is input to pin reset . 19.1.1 pin description table 19.1.1 lists the pin description in the eprom mode. in the normal operating mode, each pin has the same function as the mask rom version. functions apply 5 v 10% to pin vcc, and 0 v to pin vss. apply v pp level when programming or verifying. connect to pin vss. connect pins x in and x out via a ceramic resonator or a quartz-crystal oscillator. when an external clock is used, the clock should be input to pin x in , and pin x out should be left open. open. connect pin avcc to pin vcc and pin avss to pin vss. connect to pin vss. input pins for low-order 8 bits (a 0 Ca 7 ) of address input pins for middle-order 8 bits (a 8 Ca 15 ) of address i/o pins for 8-bit data (d 0 Cd 7 ) input pin for the most significant bit (a 16 ) address connect to pin vss. connect to pin vss. _____ p5 0 , p5 1 and p5 2 respectively function as pgm , ___ ___ oe and ce input pins. connect p5 3 Cp5 6 to pin vcc, and p5 7 to pin vss. connect to pin vss. connect to pin vss. connect to pin vss. pin vcc, vss cnvss byte ______ reset x in x out e avcc, avss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 p3 1 Cp3 3 p4 0 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7 input/output CC input input input output output CC input input input i/o input input input input input input input name power source input v pp input reset input clock input clock output enable output analog power source input reference voltage input address input (a 0 Ca 7 ) address input (a 8 Ca 15 ) data input/output (d 0 Cd 7 ) address input (a 16 ) input port p3 input port p4 control input input port p6 input port p7 input port p8 table 19.1.1 pin description in eprom mode
built-in prom version 7733 group users manual 19-4 b0 0 1 0 0 1 0 01000 16 C1ffff 16 02000 16 C1ffff 16 01000 16 C0ffff 16 08000 16 C0ffff 16 0c000 16 C0ffff 16 08000 16 C1ffff 16 19.1 eprom mode m5m27c101k vcc v pp vss a 0 Ca 16 d 0 Cd 7 ce oe pgm vcc v pp vss address input data i/o ce oe pgm table 19.1.2 pin correspondence in eprom mode vcc cnvss, byte vss p0, p1, p3 0 p2 p5 2 p5 1 p5 0 table 19.1.3 programmable area memory allocation selection bits programmable area b2 0 0 0 1 1 1 b1 0 0 1 0 0 1 m37733ehbfp (m37733ehbxxxfp) m37733ehbfs m37733ehlhp (m37733ehlxxxhp) 19.1.2 reading/programming from and to built-in prom in the eprom mode, ports p0, p1, p2, p3 0 , p5 0 , p5 1 , p5 2 and pins cnvss and byte are eprom pins (m5m27c101k equivalent), and reading/programming from and to the built-in prom can be performed in the same manner as for m5m27c101k. however, there is no device identification code. accordingly, programming conditions must be set carefully. furthermore, specify addresses from 01000 16 to 1ffff 16 as the programmable area. table 19.1.2 lists the pin correspondence in the eprom mode and table 19.1.3 lists the programmable area. figures 19.1.1 and 19.1.2 show the pin connections in the eprom mode. note: when changing the allocation of the internal memory by the memory allocation selection bits (refer to figure 2.4.1. ), specify addresses listed in table 19.1.3 as the programmable area.
built-in prom version 7733 group users manual 19-5 19.1 eprom mode fig. 19.1.1 pin connections in eprom mode (m37733ehbfp) 66 p8 2 /rxd 0 /clks 0 67 p8 1 /clk 0 1 p6 6 /tb1 in 2 p6 5 /tb0 in 3 p6 4 /int 2 4 p6 3 /int 1 5 p6 2 /int 0 6 p6 1 /ta4 in 7 p6 0 /ta4 out 8 p4 1 /rdy 64 p8 4 /cts 1 /rts 1 63 p8 5 /clk 1 62 p8 6 /rxd 1 61 p8 7 /txd 1 60 p0 0 /a 0 59 p0 1 /a 1 58 p0 2 /a 2 57 p0 3 /a 3 9 10 p5 7 /ta3 in /ki 3 11 p5 6 /ta3 out /ki 2 12 p5 5 /ta2 in /ki 1 13 p5 4 /ta2 out /ki 0 14 p5 3 /ta1 in 15 p5 2 /ta1 out 16 p5 1 /ta0 in 17 p5 0 /ta0 out 18 p4 7 19 p4 6 20 p4 5 21 p4 4 22 p4 3 23 p4 2 / 1 24 56 p0 4 /a 4 55 p0 5 /a 5 54 p0 6 /a 6 53 p0 7 /a 7 52 p1 0 /a 8 /d 8 51 p1 1 /a 9 /d 9 50 p1 2 /a 10 /d 10 49 p1 3 /a 11 /d 11 48 p1 4 /a 12 /d 12 47 p1 5 /a 13 /d 13 46 p1 6 /a 14 /d 14 45 p1 7 /a 15 /d 15 44 p2 0 /a 16 /d 0 43 p2 1 /a 17 /d 1 42 p2 2 /a 18 /d 2 41 p2 3 /a 19 /d 3 80 p7 1 /an 1 79 p7 2 /an 2 /cts 2 78 p7 3 /an 3 /clk 2 77 p7 4 /an 4 /rxd 2 76 p7 5 /an 5 /ad trg /txd 2 75 p7 6 /an 6 /x cout 74 p7 7 /an 7 /x cin 73 v ss 72 av ss 71 v ref 70 av cc 69 v cc 68 p8 0 /cts 0 /rts 0 /clks 1 65 p8 3 /txd 0 39 p2 5 /a 21 /d 5 38 p2 6 /a 22 /d 6 25 p4 0 /hold 26 byte 27 cnv ss 28 reset 29 x in 30 x out 31 e 32 v ss 33 p3 3 /hlda 34 p3 2 /ale 35 p3 1 /bhe 36 p3 0 /r/w 37 p2 7 /a 23 /d 7 40 p2 4 /a 20 /d 4 m37733ehbfp outline 80p6n-a * : connect these pins to a resonator or an oscillator. a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 9 a 10 a 11 a 12 a 13 a 14 d 0 d 1 d 2 d 3 oe ce v pp d 4 d 5 d 6 d 7 v ss * : eprom pin. a 15 pgm v cc p7 0 /an 0 p6 7 /tb2 in / sub a 16
built-in prom version 7733 group users manual 19-6 19.1 eprom mode fig. 19.1.2 pin connections in eprom mode (m37733ehlhp) x out p3 2 /ale p3 0 /r/w p3 1 /bhe d 2 a 14 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 outline 80p6d-a 1 4 3 2 5 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 /a 0 p0 1 /a 1 p0 2 /a 2 p0 3 /a 3 p0 4 /a 4 p0 5 /a 5 p0 6 /a 6 p0 7 /a 7 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 p1 7 /a 15 /d 15 p2 0 /a 16 /d 0 p2 1 /a 17 /d 1 60 59 58 75 74 73 72 71 69 68 67 66 65 70 80 79 78 77 76 64 63 62 61 30 26 27 28 29 31 32 33 34 35 36 21 23 22 24 25 37 38 39 40 p4 2 / 1 p4 1 /rdy p4 0 /hold byte cnv ss reset x in e v ss p3 3 /hlda p2 7 /a 23 /d 7 p2 6 /a 22 /d 6 p2 5 /a 21 /d 5 p2 4 /a 20 /d 4 p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out p4 7 p8 5 /clk 1 p8 4 /cts 1 /rts 1 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 p7 0 /an 0 p6 7 /tb2 in / sub m37733ehlhp p4 3 p4 4 p4 5 p4 6 p2 3 /a 19 /d 3 p2 2 /a 18 /d 2 v cc a 15 a 13 a 12 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 d 0 d 1 d 7 d 6 d 5 d 4 d 3 v pp v ss * * : connect these pins to a resonator or an oscillator. : eprom pin. ce pgm oe a 16
built-in prom version 7733 group users manual 19-7 (1) read ___ ___ when pins ce and oe are set to l level and an address is input to address input pins, the contents ___ ___ of the built-in prom can be read from data i/o pins; when pins ce and oe are set to h level, data i/o pins enter the floating state. (2) program ___ ___ when pin ce is set to l level, pin oe is set to h level, and v pp level is applied to pin v pp , programming to the prom can be performed. input an address to address input pins and supply data to be programmed to data i/o pins in 8-bit ____ parallel. on this condition, when pin pgm is set to l level, the data is programmed into the built-in prom. (3) erase (available only in eprom version) the contents of the built-in prom is erased by exposing the glass window on top of the package to an ultraviolet light which has a wave length of 2537 angstrom. the light must be 15 w?s/cm 2 or more. table 19.1.4 i/o signals in eprom mode pin name data i/o output floating floating input output floating v il v il v ih v il v il v ih v il v ih x v ih v il v ih x x x v il v ih v ih 5 v 5 v 5 v 12.5 v 12.5 v 12.5 v vcc v pp pgm ce 5 v 5 v 5 v 6 v 6 v 6 v oe 19.1 eprom mode x : it may be v il or v ih . mode read-out output disable program program verify program disable
built-in prom version 7733 group users manual 19-8 19.1.3 programming algorithm to built-in prom set vcc = 6 v, v pp = 12.5 v, and address to 01000 16 . (refer to table 19.1.3. ) after applying a programming pulse of 0.2 ms, check whether data can be read or not. a if the data cannot be read, apply a programming pulse of 0. 2 ms again. ? repeat the procedure, which consists of applying a programm ing pulse of 0.2 ms and read check, until the data can be read. additionally, record the number of pul ses applied ( x ) before the data was read. ? apply x pulses (0.2 5 x ms) (described in ? ) as additional programming pulses. ? when this procedure ( to ? ) is complete, increment the address and repeat the above pr ocedure until the last address is reached. ? after programming to the last address, read data when vcc = v pp = 5 v (or vcc = v pp = 5.5 v). figure 19.1.3 shows the programming algorithm flow chart. 19.1 eprom mode fig. 19.1.3 programming algorithm flow chart verify all byte start addr = first location x = 0 v cc = v pp = * 5.0 v device failed device passed v cc = 6.0 v v pp = 12.5 v x = x + 1 x = 25? verify byte increment addr verify byte device failed last addr? fail yes no pass pass yes fail pass no fail program one pulse of 0.2 ms program pulse of 0.2 x ms duration * : 4.5 v v cc = v pp 5.5 v
built-in prom version 7733 group users manual 19-9 19.1 eprom mode ac electrical characteristics (ta = 25 5 c, vcc = 6 v 0.25 v, v pp = 12.5 0.3 v, unless otherwise noted) 19.1.4 electrical characteristics of programming algorithm max. 130 0.21 5.25 150 typ. 0.2 min. limits unit parameter s s s s s ns s s ms ms s ns address setup time oe setup time data setup time address hold time data hold time ___ output floating delay time after oe vcc setup time v pp setup time ____ pgm pulse width ____ additional pgm pulse width ___ ce setup time ___ data delay time after oe t as t oes t ds t ah t dh t dfp t vcs t vps t pw t opw t ces t oe symbol 2 2 2 0 2 0 2 2 0.19 0.19 2 switching characteristics measuring conditions l input voltage : v il = 0.45 v, v ih = 2.4 v l input signal rise/fall time (10%?0%) : 20 ns l reference voltage in timing measurement : input/output ??= 0.8 v, ??= 2 v t vcs t vps t ds t dh t dfp t as t ah verify program data set data output valid v ih v il v ih /v oh v il /v ol v pp v cc v cc + 1 v cc address data v pp v cc t oes t oe t opw t pw v ih v il v ih v il pgm oe v ih v il t ces ce programming timing diagram
built-in prom version 7733 group users manual 19-10 19.2 usage precaution [precautions on all built-in prom versions] when programming to the built-in prom, high voltage is required. accordingly, be careful not to apply excessive voltage to the microcomputer. furthermore, be especially careful during power-on. [precautions on one time prom version] one time prom versions shipped in blank (m37733ehbfp, m37733ehlhp), of which built-in proms are programmed by users, are also provided. for these microcomputers, a programming test and screening are not performed in the assembly process and the following processes. to improve their reliability after programming, we recommend to program and test as the flow shown in figure 19.2.1 before use. 19.2 usage precaution fig. 19.2.1 programming and test flow for one time prom version [precautions on eprom version] l cover the transparent glass window with a shield or others during the read mode because exposing to sun light or fluorescent lamp can cause erasing the programmed data. a shield to cover the transparent window is available from mitsubishi electric corporation. be careful that the shield does not touch the eprom lead pins. l clean the transparent glass before erasing. there is a possibility that fingers flat and paste disturb the passage of ultraviolet rays and affect badly the erasure capability. l the eprom version is a tool only for program development (evaluation only), and do not use it for the mass product run. programming with prom programmer screening ( note ) (leave at 150 c for 40 hours) verify test with prom programmer function check in target device note: never expose to 150 c exceeding 100 hours.
chapter 20 external rom version 20.1 performance overview 20.2 pin configuration 20.3 pin description 20.4 block description 20.5 memory allocation 20.6 processor modes 20.7 timer a 20.8 reset 20.9 electrical characteristics 20.10 low voltage version
external rom version 7733 group users manual 20C2 the external rom version can operate only in the microprocessor mode. functions of the external rom version differ from those of the mask rom version in the following. therefore, only the differences are described in this chapter: ? memory allocation ? operation is available only in the microprocessor mode ? the rom area change function is not available. ? timer a has the pulse output port mode. ? power source current and current consumption for the other functions, refer to chapters 2. central processing unit (cpu) to 18. low voltage version. h for product expansion information of the 7733 group, contact the appropriate office, as listed in contact addresses for further information.
external rom version 7733 group users manual 20C3 20.1 performance overview performance overview of the external rom version differs from that of the mask rom version in the following: memory size and current consumption. for the other items, refer to section 1.1 overview. table 20.1.1 lists the m37733s4bfps performance overview. table 20.1.1 m37733s4bfps performance overview performance 2048 bytes 57 mw (when f(x in ) = 25-mhz external square wave input, vcc = 5 v, and the main clock is the system clock, typ.) 300 m w (when f(x cin ) = 32 khz, vcc = 5 v, the sub clock is the system clock, and the main clock is stopped, typ.) items memory size current consumption ram 20.1 performance overview
external rom version 7733 group users manual 20C4 20.2 pin configuration 20.2 pin configuration figure 20.2.1 shows the m37733s4bfp pin configuration. note: for the low voltage version, refer to section 20.10 low voltage version. fig. 20.2.1 m37733s4bfp pin configuration (top view) 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 /rtp1 3 p5 6 /ta3 out /ki 3 /rtp1 2 p5 5 /ta2 in /ki 1 /rtp1 1 p5 4 /ta2 out /ki 0 /rtp1 0 p5 3 /ta1 in /rtp0 3 p5 2 /ta1 out /rtp0 2 p5 1 /ta0 in /rtp0 1 p5 0 /ta0 out /rtp0 0 hold byte cnv ss reset x in x out e v ss (p3 3 )hlda (p3 2 )ale (p3 1 )bhe (p3 0 )r/w (p2 7 )a 23 /d 7 (p2 6 )a 22 /d 6 (p2 5 )a 21 /d 5 (p2 4 )a 20 /d 4 p7 4 /an 4 /r x d 2 p7 5 /an 5 /ad trg /t x d 2 p7 6 /an 6 /x cout p7 7 /an 7 /x cin v ss av ss v ref av cc v cc p8 0 /cts 0 /rts 0 /clks 1 p8 1 /clk 0 p8 2 /r x d 0 /clks 0 p8 3 /t x d 0 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 a 0 (p0 0 ) a 1 (p0 1 ) a 2 (p0 2 ) a 3 (p0 3 ) a 4 (p0 4 ) a 5 (p0 5 ) a 6 (p0 6 ) a 7 (p0 7 ) a 8 /d 8 (p1 0 ) a 9 /d 9 (p1 1 ) a 10 /d 10 (p1 2 ) 1 4 3 2 5 6 7 8 9 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 outline 80p6n-a a 11 /d 11 (p1 3 ) a 12 /d 12 (p1 4 ) a 13 /d 13 (p1 5 ) a 14 /d 14 (p1 6 ) a 15 /d 15 (p1 7 ) a 16 /d 0 (p2 0 ) a 17 /d 1 (p2 1 ) a 18 /d 2 (p2 2 ) a 19 /d 3 (p2 3 ) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 m37733s4bfp 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 rdy p4 7 p4 6 p4 5 p4 4 p4 3 (p4 2 )/ 1 p7 1 /an 1 p7 2 /an 2 /cts 2 p7 3 /an 3 /clk 2 by setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pins level can be fixed in the stop or wait mode.
external rom version 7733 group users manual 20C5 20.3 pin description 20.3 pin description tables 20.3.1 and 20.3.2 list the pin description. table 20.3.1 pin description (1) pin vcc, vss cnvss ______ reset x in x out _ e byte avcc avss v ref a 0 (p0 0 )C a 7 (p0 7 ) a 8 /d 8 (p1 0 )Ca 15 / d 15 (p1 7 ) a 16 /d 0 ( p2 0 )Ca 23 / d 7 (p2 7 ) input/output input input input output output input input output i/o i/o functions to pin vcc, apply 5 v10% (when the main clock is the system clock) or 2.7 v to 5.5 v (when the sub- clock is the system clock). to pin vss, apply 0 v. connect to pin vcc. the microcomputer is reset when l level is input to this pin. pins x in and x out are the i/o pins of the clock generating circuit, respectively. connect these pins via a ceramic resonator or a quartz-crystal oscillator. when an external clock is used, the clock should be input to pin x in , and pin x out should be left open. __ this pin outputs signal e . when e s level is l, the microcomputer reads data and instruction codes or writes _ data. also, output of signal e can be stopped by software. input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. a 16-bit width is selected when the level is l, and an 8-bit width is selected when the level is h. power source input for the a-d converter. connect to pin vcc. power source input for the a-d converter. connect to pin vss. this is the reference voltage input pin for the a-d converter. addresss low-order 8 bits (a 0 Ca 7 ) are output. l when the external data bus width = 8 bits (pin byte is at h level) addresss middle-order 8 bits (a 8 Ca 15 ) are output. l when the external bus width = 16 bits (pin byte is at l level) input/output of data (d 8 Cd 15 ) and output of addresss middle-order 8 bits (a 8 Ca 15 ) are performed with the time sharing method. input/output of data (d 0 Cd 7 ) and output of addresss high-order 8 bits (a 16 Ca 23 ) are performed with the time sharing method. name power source input cnvss reset input clock input clock output enable output external data bus width selection input analog power source input reference voltage input address (low order) output address (middle order) output/data (high order) i/o address (high order) output/ data (low-order) i/o
external rom version 7733 group users manual 20C6 20.3 pin description table 20.3.2 pin description (2) input/output output input input output i/o i/o i/o i/o i/o functions __ ____ these pins respectively output signals r/ w , bhe , ale, _____ and hlda . __ l signal r/ w this signal indicates the data bus state. when this signal level is h, a data bus is in the read state. when this signal level is l, a data bus is in the write state. ____ l signal bhe this signals level is l when the microcomputer accesses an odd address. l signal ale this signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. _____ l signal hlda this signal informs the external whether the microcomputer enters the hold state or not. _____ in hold state, pin hlda outputs l level. _____ the microcomputer is in hold state while pin hold s ____ input level is l and is in ready state while pin rdy s input level is l. clock f 1 is output from pin f 1 . p4 3 Cp4 7 function as i/ o ports with the same functions as port p5. p5 is a cmos 8-bit i/o port and has an i/o direction register. each pin can be programmed as an input port or an output port. and it can be programmed as i/o pins for timers a0Ca3 and input pins ( ki 0 C ki 3 ) for the key input interrupt. p6 is an 8-bit i/o port with the same function as port p5 and can be programmed as i/o pins for timer a4, external interrupt input pins, and input pins for timers b0Cb2. p6 7 also functions as an output pin for the sub clock ( f sub ). p7 is an 8-bit i/o port with the same function as port p5 and can be programmed as analog input pins for the a-d converter. p7 6 and p7 7 can be programmed as i/o pins (x cout , x cin ) for the sub-clock (32 khz) oscillation circuit. when using p7 6 and p7 7 as pins x cout and x cin , connect a quartz-crystal oscillator between them. p7 2 Cp7 5 also function as uart2s i/o pins. p8 is an 8-bit i/o port with the same function as port p5 and can be programmed as serial i/os i/o pins. name read write output, byte high enable output, address latch enable output, hold acknowledge output hold request, ready, clock output, i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 pin __ r/ w (p3 0 ), ____ bhe (p3 1 ), ale (p3 2 ), _____ hlda (p3 3 ) _____ hold , ____ rdy , f 1 (p4 2 ), p4 3 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7
external rom version 7733 group users manual 20C7 20.4 block description 20.4 block description figure 20.4.1 shows the m37733s4bfp block diagram. fig.20.4.1 m37733s4bfp block diagram low-order address (8) x in x out e reset v ref p8 (8) p7 (8) p5 (8) p6 (8) p4 (5) cnvss byte uart1 (9) uart0 (9) av ss (0v) av cc (0v) v ss v cc uart2 (9) x cin x cout 1 rdy hold hlda ale bhe r/w x cout x cin clock input clock output internal enable output reset input reference voltage input clock generating circuit data buffer db h (8) data buffer db l (8) instruction queue buffer q 0 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) data bank register dt(8) program counter pc(16) incrementer/decrementer(24) program bank register pg(8) input buffer register ib(16) direct page register dpr(16) stack pointer s(16) index register y(16) index register x(16) anthmetic logic unit(16) accumulator b(16) accumulator a(16) instruction register(8) data bus(even) data bus(odd) input/output port p8 input/output port p7 input/output port p6 input/output port p5 input/output port p4 address bus watchdog timer external data bus width selection input timer tb1(16) timer tb2(16) address bus/ data bus timer tb0(16) timer ta1(16) timer ta2(16) timer ta3(16) timer ta4(16) timer ta0(16) ram 2048 bytes central processing unit (cpu) incrementer(24) program address register pa(24) data address register da(24) address bus bus interface unit (biu) processor status register ps(11) a-d converter(10) high-order ? middle-order address /data (16)
external rom version 7733 group users manual 20C8 20.5 memory allocation the internal areas memory allocation is described below. for details, refer to section 2.4 memory allocation. for the external area, refer to section 20.6 processor modes. figure 20.5.1 shows the m37733s4bfps memory map and figure 20.5.2 shows the sfr areas memory map. 20.5 memory allocation
external rom version 7733 group users manual 20C9 fig. 20.5.1 m37733s4bfps memory map 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 000880 16 00ffff 16 010000 16 000000 16 00007f 16 timer a4 00ffd6 16 00fffe 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 a-d/uart2 trans./rece. uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide reset interrupt vector table peripheral device control registers (sfr) uart1 transmission uart0 transmission refer to figure 20.5.2. : external memory area for the 7733 group? microcomputers other than the m37733s4bfp, refer to section ?ppendix 1. 7733 group memory allocation . h 20.5 memory allocation
external rom version 7733 group users manual 20C10 fig. 20.5.2 sfr areas memory map uart 0 transmission interrupt control register uart 1 transmission interrupt control register int 2 /key input interrupt control register port p1 direction register ( note 3 ) uart 0 transmit/receive mode register uart 0 baud rate register (brg0) uart 0 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 0 transmission buffer register uart 1 transmit/receive control register 0 uart 1 transmit/receive mode register uart 1 baud rate register (brg1) uart 1 transmit/receive control register 1 uart 0 receive buffer register uart 1 transmission buffer register uart 1 receive buffer register port p0 register ( note 3 ) a-d register 0 a-d register 2 port p1 register ( note 3 ) port p0 direction register ( note 3 ) port p2 register ( note 3 ) port p3 register ( note 3 ) port p4 register ( note 3 ) port p5 register port p6 register port p7 register port p8 register a-d control register 0 a-d control register 1 a-d register 1 a-d register 3 a-d register 4 a-d register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002a 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 00000b 00000c 00000d 00000e 00000f 00000a 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f 00004b 00004c 00004d 00004e 00004f 00004a 000044 address (hexadecimal notation) address (hexadecimal notation) timer a1 register timer a4 register timer a2 register timer a3 register timer b0 register timer b1 register timer b2 register count start flag one-shot start flag up-down flag timer a0 register timer a0 mode register timer a1 mode register timer a2 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 watchdog timer register watchdog timer frequency selection flag a-d/uart2 trans./rece. interrupt control register uart 0 receive interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register processor mode register 1 oscillation circuit control register 1 serial transmit control register port function control register oscillation circuit control register 0 timer a3 mode register port p2 direction register ( note 3 ) port p3 direction register ( note 3 ) port p4 direction register ( note 3 ) port p5 direction register port p6 direction register port p7 direction register port p8 direction register pulse output data register 1 ( note 1 ) a-d register 6 a-d register 7 uart2 transmit/receive mode register uart2 baud rate register (brg2) uart2 transmission buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register waveform output mode register ( note 1 ) notes 1: memory map of the m37733s4bfp differs from that of the m37733mhbxxxfp in addresses 1c 16 , 1d 16 , 62 16 , and 63 16 . 2: writing to the reserved area is disabled. 3: these registers are used when outputting an arbitrary data in the stop or wait mode. pulse output data register 0 ( note 1 ) reserved area (notes 1, 2) a-d control register 1 20.5 memory allocation
external rom version 7733 group users manual 20C11 fig. 20.6.1 structure of processor mode register 0 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits ( note ) wait bit software reset bit interrupt priority detection time selection bits must be fixed to ?. this bit is ignored. 0 0 0 0 0 0 0 0: do not select. 0 1: do not select. 1 0: microprocessor mode 1 1: do not select. microcomputer is reset by setting this bit to ?. this bit is ??at reading. 0 0: 7 cycles of 0 1: 4 cycles of 1 0: 2 cycles of 1 1: do not select. 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) represents that bits 2 to 7 are not used for setting the processor mode. 5 : it may be ??or ?. note : fix the processor mode bits to ?0 2 . b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw wo rw rw rw rw 5 ? ? ? 0: software wait is inserted when accessing external area. 1: no software wait is inserted when accessing external area. 20.6 processor modes the m37733s4bfp can operate only in the microprocessor mode. for the processor mode, refer to the description of the microprocessor mode in section 2.5 processor modes. also, be sure to set as follows: ? connect pin cnvss to vcc. ? fix the processor mode bits to 10 2 . figure 20.6.1 shows the structure of the processor mode register 0. 20.6 processor modes
external rom version 7733 group users manual 20C12 20.7 timer a 20.7 timer a timer a is used mainly for output to the external. it consists of five counters (timers a0 to a4) each equipped with a 16-bit reload function. timers a0 to a4 operate independently of each other. 20.7.1 overview in the external rom version, timer a has five operating modes listed below. in operating modes to ? , the external rom version operates the same as the mask rom and prom versions. operating mode ? is described in this chapter. timer mode event counter mode a one shot pulse mode ? pulse width modulation (pwm) mode ? pulse output mode refer to chapter 6. timer a.
external rom version 7733 group users manual 20C13 20.7 timer a 20.7.2 pulse output port mode (1) overview in the pulse output mode, there are two types of pulse outpu t port: rtp0 controlled by timer a0 and rtp1 controlled by timer a2. when an underflow occurs in timer a0 or a2, the contents of the pulse output data register 0 or 1 is output from the corresponding pulse output pins. also, the pulse width can be modulated by timer a as follows : use timer a1 for rtp0 and use timer a3 for rtp1. in addition, rtp0 can reverse the polarity of t he contents of the pulse output data register 0 by software and outputs it. table 20.7.1 lists the specifications of the pulse output mo de. table 20.7.1 specifications of pulse output port mode pulse output port control timer pulse output pins register where pulse data is set pulse width modulation output level reverse function rtp0 timer a0 rtp0 0 Crtp0 3 (ports p5 0 Cp5 3 ) pulse output data register 0 possible (timer a1 is used) available rtp1 timer a2 rtp1 0 Crtp1 3 (ports p5 4 Cp5 7 ) pulse output data register 1 possible (timer a3 is used) not available
external rom version 7733 group users manual 20C14 20.7 timer a (2) block description figure 20.7.1 shows the block diagram for the pulse output m ode. figures 20.7.3 to 20.7.6 show the structures of registers related to the pulse output port mod e. also, figure 20.7.2 shows the structure of the port p5 outpu t control circuit. fig. 20.7.1 block diagram for pulse output port mode b3 b2 b1 b0 d q d q d q d q t d q d q d q t timer a0 d q 45 pulse width modulation selection bits (bits 4, 5 at address 62 16 ) pulse width modulation output by timer a3 pulse width modulation output by timer a1 timer a2 pulse output data register 1 (address 1c 16 ) rtp1 3 (p5 7 /ta3 in ) polarity selection bit (bit 3 at address 62 16 ) pulse output data register 0 (address 1d 16 ) data bus (even) data bus (odd) b3 b2 b1 b0 rtp1 2 (p5 6 /ta3 out ) rtp1 1 (p5 5 /ta2 in ) rtp1 0 (p5 4 /ta2 out ) rtp0 3 (p5 3 /ta1 in ) rtp0 1 (p5 1 /ta0 in ) rtp0 2 (p5 2 /ta1 out ) rtp0 0 (p5 0 /ta0 out )
external rom version 7733 group users manual 20C15 20.7 timer a fig. 20.7.2 port p5 output control circuit l p5 0 /ta0 out /rtp0 0 , p5 2 /ta1 out /rtp0 2 , p5 4 /ta2 out /rtp1 0 , p5 6 /ta3 out /rtp1 2 direction register port latch pulse output timer a output bit 2 of the timer ai mode register (addresses 56 16 to 59 16 ) ( note 2 ) (whether to output a pulse or not is selected.) bits 0 and 1 of the waveform output mode register (address 62 16 ) ( note 1 ) (rtp1, rtp0 selected) input l p5 1 /ta0 in /rtp0 1 , p5 3 /ta1 in /rtp0 3 , p5 5 /ta2 in /rtp1 1 , p5 7 /ta3 in /rtp1 3 bits 0 and 1 of the waveform output mode register ( note 1 ) (rtp1, rtp0 selected) input direction register port latch pulse output notes 1: ports p5 0 to p5 3 correspond to bit 1. ports p5 4 to p5 7 correspond to bit 0. 2: bit 2 of the timer ai mode register which corresponds to each port ? ? ? ? ? ? ? ? ? ? ? ?
external rom version 7733 group users manual 20C16 20.7 timer a fig. 20.7.3 structures of timer a0, a2 mode registers and ti mer a0, a2 registers in pulse output port mode x: it may be either 0 or 1. 3 gate function selection bits 2 pulse output function selection bit 1 0 operating mode selection bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer a0 mode register (address 56 16 ) 0 0: timer mode 1: pulse is output. must be fixed to 1. 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 6 count source selection bits b1 b0 b4 b3 5 must be fixed to 0 in the timer mode. 00 0 0 0: 0 1: bit 4 at reset 0 0 0 0 0 0 0 0 rw b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. undefined rw rw rw rw rw rw rw rw rw timer a2 mode register (address 58 16 ) no gate function bit 4 must be fixed to 0. 1 0 5
external rom version 7733 group users manual 20C17 20.7 timer a fig. 20.7.4 structures of timer a1, a3 mode registers and ti mer a1, a3 registers in pulse output port mode (when pulse width modulation function is used) b7 b6 b5 b4 b3 b2 b1 b0 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 6 count source selection bits b7 b6 11 1 note: fix bit 2 to 1 and bit 4 to 0 even when not using the p ulse width modulation function. x: it may be 0 or 1. at reset 0 0 0 0 0 0 0 0 rw 3 trigger selection bits 2 must be fixed to 1 in the pwm mode. ( note ) 1 0 operating mode selection bits bit name functions 1 1: pwm mode b1 b0 b4 b3 5 16/8-bit pwm mode selection bit writing 1 to the count start flag (pin tai in functions as a programmable i/o port.) bit 0: the counter operates as a 16-bit pulse width modulator. 1: the counter operates as an 8-bit pulse width modulator. 4 n when operating as an 8-bit pulse width modulator (b15) b7 b0 b7 b0 (b8) timer a1 register (addresses 49 16 , 48 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) functions bit at reset rw 7 to 0 values 00 16 to ff 16 can be set. assuming that the set value = m, period of the pwm pulse which is output from pin ta1 out or ta3 out is (m + 1)(2 8 C 1)/fi. fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) 15 to 8 values 00 16 to fe 16 can be set. assuming that the set value = n, h level width of the pwm pulse which is output from pin ta1 out or ta3 out is n(m +1)/fi. undefined undefined b7 b0 b7 b0 timer a1 register (addresses 49 16 , 48 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) functions bit at reset rw 15 to 0 values 0000 16 to fffe 16 can be set. assuming that the set value = n, h level width of the pwm pulse which is output from pin ta1 out or ta3 out is n/fi. undefined fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) n when operating as a 16-bit pulse width modulator (b15) (b8) rw rw rw rw rw rw rw rw wo wo wo timer a1 mode register (address 57 16 ) timer a3 mode register (address 59 16 ) 0 5 ( note ) 0 0: 0 1:
external rom version 7733 group users manual 20C18 20.7 timer a b7 b6 b5 b4 b3 b2 b1 b0 7 must be fixed to 0. 6 not implemented. this bit is 0 at reading. at reset 0 0 0 undefined 0 0 undefined 0 rw 3 polarity selection bit 2 not implemented. this bit is 0 at reading. 1 0 waveform output selection bits bit name functions 0 0: port p5 is a programmable i/o port. 0 1: rtp1 is selected. 1 0: rtp0 is selected. 1 1: rtp1 and rtp0 are selected. b1 b0 5 pulse width modulation selection bit by timer a3 0: positive polarity 1: negative polarity bit 0: not modulated 1: modulated 4 pulse width modulation selection bit by timer a1 rw rw C rw rw rw C rw waveform output mode register (address 62 16 ) 0 (valid only for rtp0) 0: not modulated 1: modulated fig. 20.7.5 structures of waveform output mode register
external rom version 7733 group users manual 20C19 20.7 timer a fig. 20.7.6 structures of pulse output data registers 0, 1 b7 b6 b5 b4 b3 b2 b1 b0 4 to 7 not implemented. at reset undefined undefined undefined undefined undefined rw 1 rtp1 1 output data bit 0 rtp1 0 output data bit bit name functions 3 rtp1 3 output data bit bit 2 rtp1 2 output data bit wo wo wo wo C pulse output data register 1 (address 1c 16 ) 0: l level is output. 1: h level is output. note: use the ldm and sta instructions to set bits 0 to 3. b7 b6 b5 b4 b3 b2 b1 b0 4 to 7 not implemented. at reset undefined undefined undefined undefined undefined rw 1 rtp0 1 output data bit 0 rtp0 0 output data bit bit name functions 3 rtp0 3 output data bit bit 2 rtp0 2 output data bit wo wo wo wo C pulse output data register 1 (address 1d 16 ) when the positive polarity is selected, 0: l level is output. 1: h level is output. when the negative polarity is selected, 0: h level is output. 1: l level is output. note: use the ldm and sta instructions to set bits 0 to 3.
external rom version 7733 group users manual 20C20 20.7 timer a (3) initial setting example for registers related to pulse o utput port mode figures 20.7.7 to 20.7.9 show an initial setting example for registers related to the pulse output port mode. fig. 20.7.7 initial setting example for registers related to pulse output port mode (1) b7 b0 setting of the pulse output data register 0 and pulse output data register 1 pulse output data register 0 (address 1d 16 ) continued to initial setting example for registers related to pulse outp ut port mode (2) on the next page rtp0 0 rtp0 1 rtp0 2 rtp0 3 setting of the division ratio for timer a0 or timer a2 b7 b0 values 0000 16 to ffff 16 (n) can be set. (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) h counter divides the count source by (n + 1). b7 b0 count source selection bits 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 00 setting of the timer a0 mode register or timer a2 mode regis ter timer a0 mode register (address 56 16 ) timer a2 mode register (address 5a 16 ) b7 b6 1 x: it may be 0 or 1. output data is set to the corresponding bit. b7 b0 pulse output data register 1 (address 1c 16 ) rtp1 0 rtp1 1 rtp1 2 rtp1 3 output data is set to the corresponding bit. 0 5 0
external rom version 7733 group users manual 20C21 20.7 timer a fig. 20.7.8 initial setting example for registers related to pulse output port mode (2) continued from "initial setting example for registers related to pulse output port mode (1)" on the preceding page b7 b0 timer a1 mode register (address 57 16 ) timer a3 mode register (address 59 16 ) setting of the timer a1 mode register or timer a3 mode regis ter setting of the pwm pulses period and h level width b7 b0 values 0000 16 to fffe 16 (n) can be set. (b15) (b8) b7 b0 timer a1 register (addresses 49 16 , 48 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) n when operating as a 16-bit pulse width modulator b7 b0 values 00 16 to ff 16 (m) can be set. (b15) (b8) b7 b0 when operating as an 8-bit pulse width modulator values 00 16 to fe 16 (n) can be set. h when operating as an 8-bit pulse width modulator period = (m+1) (2 8 C 1)/fi h level width = n(m + 1)/fi fi: frequency of the count source however, if n = 00 16 , the counter does not operate and pin tai out outputs l level. at this time, no timer ai request is generated. timer a1 register (addresses 49 16 , 48 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) b7 b0 11 0 setting of timers a1 and a3 timer a1 mode register (address 57 16 ) timer a3 mode register (address 59 16 ) 1 b4 b3 trigger selection bits 0 x: count start flag b7 b6 count source selection bits 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 x: it may be 0 or 1. 5 16/8-bit pwm mode selection bit 0: the counter operates as a 16-bit pulse width modulato r. 1: the counter operates as an 8-bit pulse width modulato r. 1 continued to initial setting example for registers related to pulse outp ut port mode (3) on the next page when not modulating the pulse width when modulating the pulse width h when operating as a 16-bit pulse width modulator period = (2 16 C 1)/fi h level width = n/fi fi: frequency of the count source however, if n = 0000 16 , the counter does not operate and pin tai out outputs l level. at this time, no timer ai request is generated. n
external rom version 7733 group users manual 20C22 20.7 timer a fig. 20.7.9 initial setting example for registers related to pulse output port mode (3) counting is started. setting of the count start flag to 1 b7 b0 count start flag (address 40 16 ) timer a0 count start flag timer a1 count start flag ( note ) timer a2 count start flag timer a3 count start flag ( note ) setting of the waveform output mode register b7 b0 waveform output mode register (address 62 16 ) continued from "initial setting example for registers related to pulse output port mode (2)" on the preceding page 0 setting of the interrupt priority level b7 b0 timer a0 interrupt control register (address 75 16 ) timer a1 interrupt control register (address 76 16 ) ( note ) timer a2 interrupt control register (address 77 16 ) timer a3 interrupt control register (address 78 16 ) ( note ) interrupt priority level selection bits when using interrupts, one of levels 1-7 must be set. when disabling interrupts, level 0 must be set. note: this is used when the pulse width is modulated. 0 waveform output selection bits 0 0: port p5 is a programmable i/o port. 0 1: rtp1 is selected . 1 0: rtp0 is selected . 1 1: rtp0 and rtp1 are selected. b1 b0 polarity selection bit (affective only for rtp0) 0: positive polarity 1: negative polarity pulse width modulation selection bit by timer a1 0: not modulated 1: modulated pulse width modulation selection bit by timer a3 0: not modulated 1: modulated note: this is used when the pulse width is modulated.
external rom version 7733 group users manual 20C23 20.7 timer a (4) operation in pulse output port mode the rtp0 operation when the pulse width is not modulated and the output level reverse function is not used is described below. note: description in ( ) is applied to the rtp1 operation. when the count start flag of timer a0 (a2) is set to 1, t he counter starts counting of the count source. when an underflow occurs, data is output from each bit of r tp0 (rtp1) according to the setting of each bit of the pulse output data register 0 (1). this da ta is retained until the next underflow occurs. timer a0 (a2) reloads the contents of the reload reg ister and continues counting. a when the underflow occurs in , the timer a0 (a2) interrupt request bit is set to 1. the n, the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 20.7.10 shows an operation example of the pulse outpu t port mode. fig. 20.7.10 operation example of pulse output port mode n pulse output is started. 0000 16 ffff 16 timer a0 interrupt request bit count start flag undefined 3 c n, m : reloaded value counting is started. m contents of pulse output data register 0 3 (0011 2 ) 6 (0110 2 ) c (1100 2 ) 9 (1001 2 ) contents of rtp0 output cleared to 0 when an interrupt request is accepted; otherwise, cleared by software. cleared to 0 when an interrupt request is accepted; otherwise, cleared by software. counter contents (hex.) note: the output level of the pulse output port is undefined from when the pulse output port mode is set until the first timer underflow occurs. also, this output level is at a floating state after reset because the e pulse output port becomes the input port at that time. in the above example, in order to shorten this undefined p eriod, the following procedure is performed: p ? a small value (n) is set to the timer counter as the ini tial value. ? after the first underflow occurs, the normal value (m) i s set to the timer counter. t rtp0 3 output rtp0 2 output rtp0 1 output rtp0 0 output 6
external rom version 7733 group users manual 20C24 20.7 timer a (5) selectable functions the pulse width modulation function and the rtp0 output leve l reverse function are described below. l pulse width modulation function the rtp0 operation when the positive polarity is selected is described below. note: description in ( ) is applied to the rtp1 operation. when the pulse width modulation selection bit by timer a1(a 3) [bit 4(5)) at address 62 16 ] is set to 1, modulated (refer to figure 20.7.5. ) is selected. the pulse width modulation is performed while pins rtp0 0 to rtp0 3 (rtp1 0 to rtp1 3 ) output h level. (refer to section 6.6 pulse width modulation (pwm) mode and figure 20.7.4 .) figure 20.7.11 shows an operation example when modulated is selected. fig. 20.7.11 operation example when modulated is selected n 0000 16 3 (0011 2 ) 6 (0110 2 ) c (1100 2 ) 9 (1001 2 ) ffff 16 timer a0 interrupt request bit n, m : reloaded value m rtp0 3 output rtp0 2 output rtp0 1 output rtp0 0 output timer a1 interrupt request bit count start flag counting is started. contents of pulse output data register 0 cleared to 0 when an interrupt request is accepted; otherwise, cleared by software. cleared to 0 when an interrupt request is accepted; otherwise, cleared by software. counter contents (hex.) pulse output is started. note: the output level of the pulse output port is undefined from when the pulse output port mode is set until the first timer underflow occurs. also, this output level is at a floating state after reset because the pulse output port becomes the input port at that time. in the above example, in order to shorten this undefined per iod, the following procedure is performed: ? a small value (n) is set to the timer counter as the initi al value. ? after the first underflow occurs, the normal value (m) is set to the timer counter.
external rom version 7733 group users manual 20C25 20.7 timer a l output level reverse function (only for rtp0) when the polarity selection bit (bit 3 at address 62 16 ) is set to 1, the output level can be reversed. in this case, when the rtp0 0 to rtp0 3 output data bits (bits 0 to 3 at address 1d 16 ) are set to 0, pins rtp0 0 to rtp0 3 output h level; when these bits are set to 1, these pin s output l level. when the output level reverse function and modulated are s elected, the pulse width modulation is performed while pins rtp0 0 to rtp0 3 output l level. figure 20.7.12 shows an operation example when the output level is reversed with modulated s elected. fig. 20.7.12 operation example when rtp0 output level revers e function and modulated are selected [precautions for pulse output port mode (pulse output functi on)] 1. in order to make ports p5 0 (rtp0 0 ), p5 2 (rtp0 2 ), p5 4 (rtp1 0 ), and p5 6 (rtp1 2 ) function as the pulse output pins, fix bit 2 of the timer a0 to a3 mode registers to 1. l when using rtp0: fix bit 2 of the timer a0 and a1 mode regi sters to 1. l when using rtp1: fix bit 2 of the timer a2 and a3 mode regi sters to 1. 2. when the pulse width modulation function is not used, tim ers a1 and a3 can be used as timers which do not have i/o pins. in this case, fix bit 2 of the timer a 1 and a3 mode registers to 1. in addition, fix bits 0, 1, 4, and 5 of these registers to 0. n 0000 16 3 (0011 2 ) 6(0110 2 ) c (1100 2 ) 9 (1001 2 ) ffff 16 n, m : reloaded value m pulse output is started. rtp0 3 output rtp0 2 output rtp0 1 output rtp0 0 output timer a1 interrupt request bit count start flag counting is started. contents of pulse output data register 0 timer a0 interrupt request bit cleared to 0 when an interrupt request is accepted; otherwise, cleared by software. cleared to 0 when an interrupt request is accepted; otherwise, cleared by software. counter contents (hex.) note: the output level of the pulse output port is undefined from when the pulse output port mode is set until the first timer underflow occurs. also, this output level is at a floating state after reset because the t pulse output port becomes the input port at that time. in the above example, in order to shorten this undefined p eriod, the following procedure is performed: g ? a small value (n) is set to the timer counter as the ini tial value. ? after the first underflow occurs, the normal value (m) i s set to the timer counter. n
external rom version 7733 group users manual 20C26 20.8 reset 20.8 reset the reset description of the external rom version differs from that of the mask rom version in the state immediately after reset. the state immediately after reset of the external rom version differs from that of the mask rom version in the following addresses: addresses 1c 16 , 1d 16 , 62 16 and 63 16 . only the differences are described below. figures 20.8.1 and 20.8.2 show the state of sfr area and internal ram area immediately after reset (1) and (4). figure 20.8.1 corresponds to figure 13.1.3. figure 20.8.2 corresponds to figure 13.1.6. for the other descriptions, refer to chapter 13. reset.
external rom version 7733 group users manual 20C27 20.8 reset fig. 20.8.1 state of sfr area and internal ram area immediately after reset (1) : ??immediately after reset. : ??immediately after reset. : undefined immediately after reset. 0 1 ? : always ??at reading 0 0 : always undefined at reading : ??immediately after reset. must be fixed to ?. 10 16 11 16 12 16 13 16 port p8 direction register 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 address port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register a-d control register 0 a-d control register 1 port p0 register port p1 register port p2 register port p3 register port p0 direction register port p1 direction register port p2 direction register port p3 direction register register name access characteristics state immediately after reset rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 00 16 00 16 ? ? 00 16 00 16 00 16 0000 00000000 00 16 0 0 000 ? 00 11 b7 b0 b7 b0 : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : not implemented. it is impossible to read the bit state. the written value becomes invalid. rw ro wo n sfr area (addresses 0 16 to 7f 16 ) rw ? ? ? ? ? 00 16 ? ? ? h the contents of addresses 1c 16 and 1d 16 of the m37733s4bfp differ from those of the m37733mhbxxxfp. abbreviations which represent access characteristics rw rw ?? 0 ? ??? ? 00 16 ? ? ? ? ? pulse output data register 1 pulse output data register 0 ? ? ? ? ? ? wo wo h h
external rom version 7733 group users manual 20C28 20.8 reset fig. 20.8.2 state of sfr area and internal ram area immediately after reset (4) 7a 16 7b 16 7c 16 7d 16 7e 16 0 ro uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address oscillation circuit control register 0 serial transmit control register a-d / uart 2 trans./rece. interrupt control register uart0 transmission interrupt control register uart1 transmission interrupt control register int 2 /key input interrupt control register watchdog timer frequency selection flag register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw( h 2) rw rw rw rw b7 b0 wo rw rw rw rw rw rw rw rw rw rw state immediately after reset ? ? ? ? ? 0 000 ? 0 ? ( h 1) b7 b0 ? 0 0 0 0 0 00 0 0000 00 0 000 port function control register uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register rw rw wo rw rw rw 000 0 0 1 000 0 00 0 0 000 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 000 0 0 0 0 0 000 0 00 0 0 00 0 ? ? ? 00 0 000 00 0 000 a value of ?ff 16 ?is set to the watchdog timer. (refer to chapter ?0. watchdog timer. ) for access characteristics at address 6c 16 , also refer to figure 14.3.2. the contents of addresses 62 16 and 63 16 of the m37733s4bfp differ from those of the m37733mhbxxxfp. do not wirte to address 63 16 . n internal ram area (m37733s4bfp: addresses 80 16 to fff 16 ) l at hardware reset (not including the case where the stop or wait mode is terminated)...undefined. l at software reset...retains the state immediately before reset . l when the stop or wait mode is terminated (when hardware reset is used)...retains the state immediately before the stp or wit instruction is executed. ? rw h 3 000 h 1 h 2 h 3 h 4 waveform output mode register h 3 (reserved area) h 4 uart 2 transmit/receive mode register uart 2 baud rate register (brg2) uart 2 transmission buffer register uart 2 transmit/receive control register 0 uart 2 transmit/receive control register 1 uart 2 receive buffer register oscillation circuit control register 1 00 rw ? 00 0 000 0 wo wo wo rw ro 1 000 rw rw ro ro 000 0 00 1 0 ro 000 00 0 ? rw ? ? 0 000 0 000 ? 0 rw rw rw 0 ? 0 00 ?
external rom version 7733 group users manual 20C29 20.9 electrical characteristics 20.9 electrical characteristics except for icc, the electrical characteristics of the m37733s4bfp are the same as those of the m37733mhbxxxfp in the microprocessor mode. for the others, refer to chapter 15. electrical characteristics.) electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, unless otherwise noted) max. 22.8 3.2 20 120 10 1 20 limits vcc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 12.5 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 5v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 1.5625 mhz), f(x cin ) : stopped, in operating (note 1) vcc = 5v, f(x in ) = 25 mhz (square waveform), f(x cin ) = 32.768 khz, when the wit instruction is executed (note 2) vcc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) vcc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when the wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped unit measuring conditions symbol parameter i cc power source current min. typ. 11.4 1.6 10 60 5 ma ma a a a a a external bus is operating, output pins are open, and the other pins are connected to vss. notes 1: this is applied when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output disable selection bit = 1. 2: this is applied when the main clock external input selection bit = 1 and the system clock stop selection bit at wait state = 1. 3: this is applied when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4: this is applied when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1.
external rom version 7733 group users manual 20C30 20.10 low voltage version 20.10 low voltage version differences from the m37733s4bfp are mainly described below. 20.10.1 performance overview the performance overview of the low voltage version differs from that of the mask rom version in the following: memory size and current consumption. for the other items, refer to section 18.1 performance overview. table 20.10.1 shows the performance overview of the m37733s4lhp. items memory size current consumption performance 2048 bytes 10.8 mw (when f(x in ) = 12-mhz external square wave input, vcc = 3 v, and the main clock is the system clock, typ.) 120 w (when f(x cin ) = 32 khz, vcc = 3 v, the sub clock is the system clock, and the main clock is stopped, typ.) table 20.10.1 m37733s4lhps performance overview ram
external rom version 7733 group users manual 20C31 20.10 low voltage version 20.10.2 pin configuration figure 20.10.1 shows the m37733s4lhp pin configuration. fig. 20.10.1 m37733s4lhp pin configuration (top view) (p3 2 )ale (p3 1 )bhe (p3 3 )hlda x out e cnv ss reset hold 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p8 6 /r x d 1 p8 7 /t x d 1 a 0 (p0 0 ) a 1 (p0 1 ) a 2 (p0 2 ) a 3 (p0 3 ) a 4 (p0 4 ) a 5 (p0 5 ) a 6 (p0 6 ) a 7 (p0 7 ) a 8 /d 8 (p1 0 ) a 9 /d 9 (p1 1 ) a 10 /d 10 (p1 2 ) a 11 /d 11 (p1 3 ) a 12 /d 12 (p1 4 ) a 13 /d 13 (p1 5 ) a 14 /d 14 (p1 6 ) a 15 /d 15 (p1 7 ) a 16 /d 0 (p2 0 ) a 17 /d 1 (p2 1 ) 60 59 58 75 74 73 72 71 69 68 67 66 65 70 80 79 78 77 76 64 63 62 61 30 26 27 28 29 31 32 33 34 35 36 21 23 22 24 25 37 38 39 40 rdy (p4 2 )/ 1 byte x in v ss (p3 0 )r/w (p2 7 )a 23 /d 7 (p2 6) /a 22 /d 6 (p2 5 )a 21 /d 5 (p2 4 )a 20 /d 4 (p2 3 )a 19 /d 3 (p2 2 )a 18 /d 2 p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 /rtp1 3 p5 6 /ta3 out /ki 2 /rtp1 2 p5 5 /ta2 in /ki 1 /rtp1 1 p5 4 /ta2 out /ki 0 /rtp1 0 p5 3 /ta1 in /rtp0 3 p5 2 /ta1 out /rtp0 2 p5 1 /ta0 in /rtp0 1 p5 0 /ta0 out /rtp0 0 p4 7 p8 5 /clk 1 p8 4 /cts 1 /rts 1 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 p7 0 /an 0 p6 7 /tb2 in / sub m37733s4lhp p4 3 p4 4 p4 5 p4 6 1 2 3 4 5 outline 80p6d-a by setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pins level can be fixed in the stop or wait mode.
external rom version 7733 group users manual 20C32 20.10 low voltage version limits vcc = 5 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 6 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 3 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 6 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 3 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 0.75 mhz), f(x cin ) : stopped, in operating (note 1) vcc = 3 v, f(x in ) = 12 mhz (square waveform), f(x cin ) = 32.768 khz, when the wit instruction is executed (note 2) vcc = 3 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) vcc = 3 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when the wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped electrical characteristics (vcc= 5 v, vss = 0 v, ta = C40 to 85 c, unless otherwise noted) unit measuring conditions symbol parameter icc power source current min. typ. 5.4 3.6 0.5 6 40 3 ma ma ma a a a a a max. 10.8 7.2 1.0 12 80 6 1 20 notes 1: this is applied when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output disable selection bit = 1. 2: this is applied when the main clock external input selection bit = 1 and the system clock stop bit at wait state = 1. 3: this is applied when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4: this is applied when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1. external bus is operating, output pins are open, and the other pins are connected to vss. 20.10.3 functional description except for the power-on reset conditions, the m37733s4lhp has the same functions as the m37733s4bfp. for the other functions, refer to chapters 2. central processing unit (cpu) to 14. clock generating circuit. the power-on reset conditions of the m37733s4lhp are the same as those of the m37733mhlxxxhp. for details, refer to section 18.3 functional description . 20.10.4 electrical characteristics except for icc, the electrical characteristics of the m37733s4lhp are the same as those of the m37733mhlxxxhp in the microprocessor mode. for the others, refer to section 18.4 electrical characteristics.
appendix appendix appendix 1. memory allocation of 7733 group appendix 2. memory allocation in sfr area appendix 3. control registers appendix 4. package outlines appendix 5. hexadecimal instruction code table appendix 6. machine instructions appendix 7. examples of handling unused pins appendix 8. countermeasure examples against noise appendix 9. q & a
appendix 7733 group users manual 21-2 appendix 1. memory allocation of 7733 group 1. m37733mhbxxxfp, m37733ehbxxxfp, m37733ehbfs, m37733mhlxxxhp, m37733ehlxxxhp fig. 1 memory allocation of m37733mhbxxxfp, m37733ehbxxxfp, m37733ehbfs, m37733mhlxxxhp, m37733ehlxxxhp (1) 01ffff 16 ff0000 16 sfr area internal ram area 3968 bytes 000000 16 00007f 16 000080 16 000fff 16 ffffff 16 bank 0 16 bank 1 16 bank ff 16 internal rom area 60 kbytes internal rom area 64 kbytes 001000 16 00ffff 16 010000 16 bank 2 16 002000 16 000000 16 00007f 16 000080 16 000fff 16 (4 kbytes) 00ffff 16 010000 16 01ffff 16 ffffff 16 000000 16 00007f 16 a-d/uart2 trans./rece. uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide reset 00ffd6 16 00fffe 16 interrupt vector table sfr area internal ram area 3968 bytes internal rom area 56 kbytes internal rom area 64k bytes peripheral device control registers (sfr) ?memory allocation selection bits (b2, b1, b0)=(0, 0, 0) ?rom size: 124 kbytes ?ram size: 3.9 kbytes ?memory allocation selection bits (b2, b1, b0)=(0, 0, 1) ?rom size: 120 kbytes ?ram size: 3.9 kbytes uart1 transmission uart0 transmission : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: memory allocation of the 7735 group differs from that of the 7733 group. (for the memory allocation of the 7735 group, refer to section ?ppendix 1 in part 2. ) refer to appendix 2. 02ffff 16 020000 16 appendix 1. memory allocation of 7733 group
appendix 7733 group users manual 21-3 appendix 1. memory allocation of 7733 group fig. 2 memory allocation of m37733mhbxxxfp, m37733ehbxxxfp, m37733ehbfs, m37733mhlxxxhp, m37733ehlxxxhp (2) 00ffff 16 010000 16 uart1 transmission 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 001000 16 000000 16 00007f 16 000080 16 00087f 16 00ffff 16 010000 16 ffffff 16 000000 16 reset 00007f 16 00ffd6 16 00fffe 16 a-d/uart2 trans./rece. 020000 16 008000 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 60 kbytes bank 2 16 (29.9 kbytes) uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide interrupt vector table sfr area internal ram area 2048 bytes peripheral device control registers (sfr) : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode ?memory allocation selection bits (b2, b1, b0)=(0, 1, 0) ?rom size: 60 kbytes ?ram size: 2048 bytes ?memory allocation selection bits (b2, b1, b0)=(1, 0, 0) ?rom size: 32 kbytes ?ram size: 2048 bytes (1.9 kbytes) uart0 transmission refer to appendix 2. 02ffff 16 notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: banks 10 16 to ff 16 cannot be accessed in the 7735 group and in external bus mode b of the 7736 group. internal rom area 32 kbytes
appendix 7733 group users manual 21-4 appendix 1. memory allocation of 7733 group fig. 3 memory allocation of m37733mhbxxxfp, m37733ehbxxxfp, m37733ehbfs, m37733mhlxxxhp, m37733ehlxxxhp (3) 00ffff 16 010000 16 020000 16 uart1 transmission 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 00c000 16 000000 16 00007f 16 000080 16 000fff 16 00ffff 16 010000 16 ffffff 16 000000 16 reset 00007f 16 00ffd6 16 00fffe 16 a-d/uart2 trans./rece. 008000 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 16 kbytes bank 2 16 (28 kbytes) uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide interrupt vector table sfr area internal ram area 3968 bytes peripheral device control registers (sfr) : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode ?memory allocation selection bits (b2, b1, b0)=(1, 0, 1) ?rom size: 16 kbytes ?ram size: 2048 bytes ?memory allocation selection bits (b2, b1, b0)=(1, 1, 0) ?rom size: 96 kbytes ?ram size: 3968 bytes (45.9 kbytes) uart0 transmission refer to appendix 2. 02ffff 16 notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: banks 10 16 to ff 16 cannot be accessed in the 7735 group and in external bus mode b of the 7736 group. internal rom area 32 kbytes 001000 16 internal rom area 64 kbytes 01ffff 16
appendix 7733 group user s manual 21-5 2. m37733s4bfp, m37733s4lhp 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 000880 16 00ffff 16 010000 16 000000 16 00007f 16 timer a4 00ffd6 16 00fffe 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 a-d/uart2 trans./rece. uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide reset interrupt vector table peripheral device control registers (sfr) uart1 transmission uart0 transmission refer to appendix. 2 : external memory area the area at addresses 00ffd6 16 to 00ffff 16 is the interrupt vector table area. be sure to set rom to this area. h memory allocation of the 7735 group differs from that of the 7733 group. (for the memory allocation of the 7735 group, refer to secti on appendix 1 in part 2. ) h fig. 4 memory allocation of m37733s4bfp, m37733s4lhp appendix 1. memory allocation of 7733 group
appendix 7733 group user s manual 21-6 fig. 5 memory allocation in sfr area (1) appendix 2. memory allocation in sfr area figures 5 to 8 show the memory allocation in sfr area. the signals used in figures 5 to 8 are shown below. : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. 0 1 ? : always 0 at reading 0 0 : always undefined at reading : 0 immediately after reset. must be fixed to 0. : it is possible to read the bit state at reading. the writ ten value becomes valid. : it is possible to read the bit state at reading. the writ ten value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : not implemented. it is impossible to read the bit state. the written value becomes invalid. rw ro wo ? abbreviations which represent access characteristics 10 16 11 16 12 16 13 16 port p8 direction register 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 address port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register a-d control register 0 a-d control register 1 port p0 register port p1 register port p2 register port p3 register port p0 direction register port p1 direction register port p2 direction register port p3 direction register register name access characteristics state immediately after reset rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 00 16 00 16 ? ? 00 16 00 16 00 16 00 0 0 00 0 0 00 0 0 00 16 0 0 00 0 ? 0 0 11 b7 b0 b7 b0 n sfr area (addresses 0 16 to 7f 16 ) rw ? ? ? ? ? 00 16 ? ? h do not write to the reserved area. (for the m37733s4bfp, m3 7733s4lhp, m37735s4bfp, m37735s4lhp, refer to figure 20.8.1.) rw rw ?? 0 ? ?? ? ? 00 16 ? ? ? ? ? (reserved area) h (reserved area) h ? ? ? ? ? ? appendix 2. memory allocation in sfr area
appendix 7733 group user s manual 21-7 fig. 6 memory allocation in sfr area (2) uart0 transmit/receive control register 0 uart0 transmit/receive mode register uart0 baud rate register uart0 transmission buffer register uart1 receive buffer register register name uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register uart1 transmission buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 30 16 31 16 32 16 33 16 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 28 16 29 16 2b 16 2c 16 2d 16 2e 16 2f 16 2a 16 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 3f 16 address access characteristics rw wo wo ro ro b7 b0 wo rw ro ro ro rw rw ro ro rw wo wo wo rw ro ro ro rw rw state immediately after reset 00 1 00 0 00 16 0 00 0 00 0 ? b7 b0 00 16 00 0 0 0 0 1 0 00 0 0 00 0 00 1 00 0 00 0 0 0 0 1 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a-d register 5 a-d register 1 a-d register 3 a-d register 2 a-d register 4 a-d register 0 a-d register 6 a-d register 7 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro rw rw 00 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix 2. memory allocation in sfr area
appendix 7733 group user s manual 21-8 fig. 7 memory allocation in sfr area (3) timer b2 register 40 16 41 16 42 16 43 16 44 16 45 16 46 16 47 16 48 16 49 16 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5c 16 5d 16 5e 16 5f 16 4b 16 4c 16 4d 16 4e 16 4f 16 4a 16 address timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register processor mode register 0 one-shot start flag timer a0 register up-down flag timer a1 register register name count start flag timer a1 mode register timer a2 mode register timer a3 mode register timer b0 mode register timer b1 mode register timer b2 mode register access characteristics wo rw b7 b0 rw rw rw rw rw rw rw wo rw state immediately after reset 00 16 00 16 00 16 00 16 ? 00 16 b7 b0 00 16 00 0 00 0 0 0 0 0 0 0 wo rw rw rw timer a0 mode register timer a4 mode register rw rw rw 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 0 rw rw ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 processor mode register 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 2 h 2 h 2 h 3 h 3 h 1 access characteristics at addresses 46 16 to 55 16 vary according to the timer s operating mode. (refer to chapter 6. timer a, and chapter 7. timer b. ) h 2 access characteristics for bit 5 at addresses 5b 16 to 5d 16 vary according to the timer b s operating mode. (refer to chapter 7. timer b. ) h 3 access characteristics for bit 1 at address 5e 16 and its state immediately after reset vary according to the voltage level applied to pin cnv ss . (refer to section 2.5 processor modes. ) appendix 2. memory allocation in sfr area
appendix 7733 group user s manual 21-9 fig. 8 memory allocation in sfr area (4) 0 ro o uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address oscillation circuit control register 0 serial transmit control register a-d / uart 2 trans./rece. interrupt control register uart0 transmission interrupt control register uart1 transmission interrupt control register int 2 /key input interrupt control register watchdog timer frequency selection flag register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw( h 2) rw rw rw rw b7 b0 wo rw rw rw rw rw rw rw rw rw rw state immediately after reset ? ? ? ? ? 0 00 0 ? 0 ? ( h 1) b7 b0 ? 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 port function control register uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register rw rw wo rw rw rw 00 0 0 0 1 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 ? ? ? 00 0 0 0 0 00 0 0 0 0 a value of fff 16 is set to the watchdog timer. (refer to chapter 10. watchdog timer. ) for access characteristics at address 6c 16 , also refer to figure 14.3.2. fix this bit to 1 in the one time prom version and eprom v ersion. (however, fix this bit to 0 in the 7735 group.) do not write to the reserved area. (refer to figure 20.8.1 for the m37733s4bfp, m37733s4lhp, m3 7735s4bfp, 37735s4lhp.) n internal ram area (m37733mhbxxxfp: addresses 80 16 to fff 16 ) at hardware reset (not including the case where the stop or wait mode is te rminated)...undefined. at software reset...retains the state immediately before res et . when the stop or wait mode is terminated (when the hardware reset is used)...retains the state imm ediately before the stp or wit instr uction is executed. ? rw h 3 00 0 h 1 h 2 h 3 h 4 (reserved area) h 4 memory allocation control register uart 2 transmit/receive mode register uart 2 baud rate register (brg2) uart 2 transmission buffer register uart 2 transmit/receive control register 0 uart 2 transmit/receive control register 1 uart 2 receive buffer register oscillation circuit control register 1 rw 0 ? 0 00 0 rw ? 00 0 0 0 0 0 wo wo wo rw ro 1 00 0 rw ro ro 00 0 0 00 1 0 ro 00 0 00 0 ? rw ? ? 0 00 0 0 00 0 ? 0 appendix 2. memory allocation in sfr area rw
appendix 7733 group users manual 21-10 appendix 3. control registers appendix 3. control registers the control registers allocated in the sfr area are shown on the following pages. below is the structure diagram for all registers. 0 1 0 xxx register (address xx 16 ) b1 b0 b2 b3 b4 b5 b6 b7 0 ] 1 ] 2 ] 3 2 3 ... select bit 0 : ... 1 : ... ... select bit 0 : ... 1 : ... the value is ??at reading. 0 : ... 1 : ... fix this bit to ?. 4 7 t o 5 not implemented. 5 rw wo ro rw rw | 0 0 0 bit bit name this bit is ignored in ... mode. functions at reset rw ... flag undefined undefined ] 1 blank : set to ??or ??according to the usage. 0 : set to ??at writing. 1 : set to ??at writing. 5 : ignored depending on the mode or state. it may be ??or ?.? : not implemented. ] 2 0 : ??immediately after reset. 1 : ??immediately after reset. undefined : undefined immediately after reset. ] 3 rw : it is possible to read the bit state at reading. the written value becomes valid. ro : it is possible to read the bit state at reading. the written value becomes invalid. accordingly, the written value may be ??or ?.? wo : the written value becomes valid. it is impossible to read the bit state. the value is undefined at reading. however, when [??at reading] is indicated in the ?unction?or ?ote?column, the bit is always ??at reading.(see to ] 4 above.) : it is impossible to read the bit state. the value is undefined at reading. however, when [??at reading] is indicated in the ?unction?or ?ote?column, the bit is always ??at reading.(see to ] 4 above.) the written value becomes invalid. accordingly, the written value may be ?? or ?. ] 4
appendix 7733 group user s manual 21-11 appendix 3. control registers port pi register port pi direction register data is input from or output to a pin by reading from or writing t o the corresponding bit. port pi register (i = 0 to 8) (addresses 2 16 ,3 16 ,6 16 ,7 16 ,a 16 ,b 16 ,e 16 ,f 16 ,12 16 ) b1 b0 b2 b3 b4 b5 b6 b7 note: writing to bits 4 to 7 of the port p3 register is invalid an d these bits are fixed to 0 when they are read. 0: l level 1: h level 7 port pi 7 s pin undefined rw bit bit name functions at reset rw 0 port pi 0 s pin rw undefined 1 port pi 1 s pin rw undefined 2 port pi 2 s pin rw undefined 3 port pi 3 s pin rw undefined 4 port pi 4 s pin rw undefined 5 port pi 5 s pin rw undefined 6 port pi 6 s pin rw undefined bit bit name functions 0: input mode (the port functions as an input port.) 1: output mode (the port functions as an output port.) port pi direction register (i = 0 to 8) (addresses 4 16 ,5 16 ,8 16 ,9 16 ,c 16 ,d 16 ,10 16 ,11 16 ,14 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw note: writing to bits 4 to 7 of the port p3 direction register is invalid and these bits are fixed to 0 when they are read. 0 port pi 0 direction selection bit 0 rw 1 port pi 1 direction selection bit 0 rw 2 port pi 2 direction selection bit 0 rw 3 port pi 3 direction selection bit 0 rw 4 port pi 4 direction selection bit 0 rw 5 port pi 5 direction selection bit 0 rw 6 port pi 6 direction selection bit 0 rw 7 port pi 7 direction selection bit 0 rw pi 7 b1 b2 b3 b4 b5 b6 b7 bit corresponding pin pi 6 pi 5 pi 4 pi 3 pi 2 pi 1 pi 0 b0
appendix 7733 group user s manual 21-12 appendix 3. control registers a-d control register 0 a-d control register 1 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (address 1f 16 ) bit 1 0 bit name at reset 1 rw functions 0 0: pins an 0 and an 1 (2 pins) 0 1: pins an 0 to an 3 (4 pins) 1 0: pins an 0 to an 5 (6 pins) (note 2) 1 1: pins an 0 to an 7 (8 pins) b1 b0 not implemented. undefined 1 these bits are ignored in the one-shot and repeat modes. (t hey may be 0 or 1. ) when an external trigger is selected, pin an 5 cannot be used as an analog input pin. writing to each bit of the a-d control register 1 must be pe rformed while the a-d converter stops operating. when the v ref connection selection bit is cleared from 1 to 0, wait f or an interval of 1 s or more passed, and then start a-d conversion. 2 3 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution a-d sweep pin selection bits (valid in the single sweep and repeat sweep modes.) (note 1) 0 4 must be fixed to 0. 5 v ref connection selection bit (note 4) 0: pin v ref is connected. 1: pin v ref is disconnected. (high impedance) 7 6 not implemented. 0 0 undefined rw rw rw rw rw C 0 notes 1: 2: 3: 4: b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 0 (address 1e 16 ) bit a-d conversion frequency ( f ad ) selection flag a-d conversion start flag trigger selection bit 4 a-d operation mode selection bits 2 1 0 bit name at reset 0 0 0 0 0 undefined undefined undefined rw functions 0 0 0: an 0 is selected. 0 0 1: an 1 is selected. 0 1 0: an 2 is selected. 0 1 1: an 3 is selected. 1 0 0: an 4 is selected. 1 0 1: an 5 is selected. (note 2) 1 1 0: an 6 is selected. 1 1 1: an 7 is selected. f 2 ] : refer to chapter 14. clock generating circuit. b2 b1 b0 0: internal trigger 1: external trigger 0: f 2 /4 ] 1: f 2 /2 00: one-shot mode 01: repeat mode 10: single sweep mode 11: repeat sweep mode 0: a-d conversion is stopped. 1: a-d conversion is started. b4b3 these bits are ignored in the single sweep and repeat sweep modes. (they may be 0 or 1. ) when an external trigger is selected, pin an 5 cannot be used as an analog input pin. writing to each bit (except bit 6) of the a-d control regist er 0 must be performed while the a-d converter stops operating. analog input selection bits (valid in the one-shot and repeat modes.) (note 1) notes 1: 2: 3: 3 7 6 5 rw rw rw rw rw rw rw rw C
appendix 7733 group user s manual 21-13 appendix 3. control registers a-d register i b7 b0 a-d register 0 (addresses 21 16 and 20 16 ) a-d register 1 (addresses 23 16 and 22 16 ) a-d register 2 (addresses 25 16 and 24 16 ) a-d register 3 (addresses 27 16 and 26 16 ) a-d register 4 (addresses 29 16 and 28 16 ) a-d register 5 (addresses 2b 16 and 2a 16 ) a-d register 6 (addresses 2d 16 and 2c 16 ) a-d register 7 (addresses 2f 16 and 2e 16 ) bit 0 at reading. the a-d conversion result is read out. functions at reset 0 undefined ro ro rw b7 b0 (b15) (b8) l when resolution = 10 bits 15 to 10 9 to 0 b7 b0 a-d register 0 (addresses 21 16 and 20 16 ) a-d register 1 (addresses 23 16 and 22 16 ) a-d register 2 (addresses 25 16 and 24 16 ) a-d register 3 (addresses 27 16 and 26 16 ) a-d register 4 (addresses 29 16 and 28 16 ) a-d register 5 (addresses 2b 16 and 2a 16 ) a-d register 6 (addresses 2d 16 and 2c 16 ) a-d register 7 (addresses 2f 16 and 2e 16 ) bit 0 at reading. the a-d conversion result is read out. functions at reset 0 undefined ro rw b7 b0 (b15) (b8) l when resolution = 8 bits 7 to 0 15 to 8 ro
appendix 7733 group user s manual 21-14 appendix 3. control registers uart0, uart1 transmit/receive mode register bit 7 sleep selection bit (valid in the uart mode.) (note) 6 parity enable bit (valid in the uart mode.) (note) 5 odd/even parity selection bit (valid in the uart mode when the parity enable bit = 1. ) (note) 4 stop bit length selection bit (valid in the uart mode.) (note) 3 internal/external clock selection bit 2 1 0 serial i/o mode selection bits bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0 0: serial i/o is disabled. (p8 functions as a programmable i/o port.) 0 0 1: clock synchronous serial i/o mode 0 1 0: do not select. 0 1 1: do not select. 1 0 0: uart mode (transfer data length = 7 bits) 1 0 1: uart mode (transfer data length = 8 bits) 1 1 0: uart mode (transfer data length = 9 bits) 1 1 1: do not select. uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) note: bits 4 to 6 are ignored in the clock synchronous serial i/o mode. (they may be 0 or 1. ) fix bit 7 to 0. b2 b1 b0 0: odd parity 1: even parity 0: parity is disabled. 1: parity is enabled. 0: the sleep mode is terminated. (ignored.) 1: the sleep mode is selected. 0: internal clock 1: external clock 0: one stop bit 1: two stop bits rw rw rw rw rw rw rw rw uarti baud rate register (brgi) b7 b0 uart0 baud rate register (address 31 16 ) uart1 baud rate register (address 39 16 ) uart2 baud rate register (address 65 16 ) functions bit at reset rw 7 to 0 values 00 16 to ff 16 can be set. assuming that the set value = n, brgi divides the count source frequency by (n + 1). un- defined wo
appendix 7733 group user s manual 21-15 appendix 3. control registers uarti transmission buffer register b7 b0 (b15) (b8) b7 b0 uart0 transmission buffer register (addresses 33 16 , 32 16 ) uart1 transmission buffer register (addresses 3b 16 , 3a 16 ) uart2 transmission buffer register (addresses 67 16 , 66 16 ) bit not implemented. the transmit data is set. at reset un- defined rw functions 8 to 0 15 to 9 un- defined wo uart0, uart1 transmit/receive control register 0 0: at the falling edge of the transfer clock, transmit data is output; at the rising edge of the transfer clock, receive data is input. when not in transferring, pin clk i s level is h. 1: at the rising edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. when not in transferring, pin clk i s level is l. 0: the cts / rts function is enabled. 1: the cts / rts function is disabled. (p8 0 and p8 4 function as programmable i/o ports.) (valid when the cts / rts enable bit is 0. ) 2 cts / rts function selection bit bit 1 0 brg count source selection bits bit name at reset 0: data is present in the transmission register. (transmission is in progress.) 1: no data is present in the transmission register. (transmission is completed.) rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 uart0 transmit/receive control register 0 ( a d dress 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b1 b0 0: the cts function is selected. 1: the rts function is selected. 4 cts / rts enable bit 3 transmission register empty flag 0 1 0 0 0 clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. note: fix bits 6 and 7 to 0 in the uart mode. 5 data output selection bit 0: pin txd i is set for cmos output. 1: pin txd i is set for n-channel open- drain output. 0 6 0 7 0: lsb (least significant bit) first 1: msb (most significant bit) first 0 clk polarity selection bit (this bit is used in the clock synchronous serial i/o mode.) (note) transfer format selection bit (this bit is used in the clock synchronous serial i/o mode.) (note) rw rw rw ro rw rw rw rw
appendix 7733 group user s manual 21-16 appendix 3. control registers uarti transmit/receive control register 1 at reset bit bit name 5 framing error flag (notes 1 and 2) (valid in the uart mode.) 0 0: no framing error is detected. 1: framing error is detected. rw functions b7 b6 b5 b4 b3 b2 b1 b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart2 transmit/receive control register 1 (address 69 16 ) notes 1: bits 4 to 7 are cleared to 0 when the serial i/o mode sel ection bits (bits 2 to 0 at addresses 30 16 , 38 16 ) are cleared to 000 2 or when the receive enable bit is cleared to 0. (bit 7 is cleared to 0 when all of bits 4 to 6 are 0. ) note also that bits 5 and 6 are cleared to 0 when the low-order byte of the uarti receive buffer register (addresses 36 16 , 3e 16 , 6a 16 ) is read out. 2: bits 5 to 7 are ignored in the clock synchronous serial i/o mode. 0 transmit enable bit 0 0: transmission is disabled. 1: transmission is enabled. 1 transmission buffer empty flag 1 0: data is present in the transmission buffer register. 1: no data is present in the transmission buffer register. 2 receive enable bit 0 0: reception is disabled. 1: reception is enabled. 3 receive completion flag 0 0: no data is present in the receive buffer register. 1: data is present in the receive buffer register. 4 overrun error flag (note 1) 0 0: no overrun error is detected. 1: overrun error is detected. 6 parity error flag (notes 1 and 2) (valid in the uart mode.) 0 0: no parity error is detected. 1: parity error is detected. 7 error sum flag (notes 1 and 2) (valid in the uart mode.) 0 0: no error is detected. 1: error is detected. rw ro rw ro ro ro ro ro uarti receive buffer register b7 b0 (b15) (b8) b7 b0 uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) uart2 receive buffer register (addresses 6b 16 , 6a 16 ) bit not implemented. a value of 0 is read out from here. the receive data is read out from here. at reset 0 un- defined rw functions 8 to 0 15 to 9 ro
appendix 7733 group user s manual 21-17 appendix 3. control registers count start flag bit 7 timer b2 count start flag 6 timer b1 count start flag 5 timer b0 count start flag 4 timer a4 count start flag 3 timer a3 count start flag 2 timer a2 count start flag 1 timer a1 count start flag 0 timer a0 count start flag bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 count start flag (address 40 16 ) 0: counting is stopped. 1: counting is started. rw rw rw rw rw rw rw rw one-shot start flag bit 7 to 5 not implemented. 4 timer a4 one-shot start flag 3 timer a3 one-shot start flag 2 timer a2 one-shot start flag 1 timer a1 one-shot start flag 0 timer a0 one-shot start flag bit name at reset 0 0 undefined 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 one-shot start flag (address 42 16 ) 1: one-shot pulse output is started. (valid when the internal trigger is selected.) 0 at reading. wo wo wo wo wo C up-down flag bit bit name at reset 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 up-down flag (address 44 16 ) 0 0 0 4 timer a4 up-down flag 3 timer a3 up-down flag 2 timer a2 up-down flag 1 timer a1 up-down flag 0 timer a0 up-down flag 5 timer a2 two-phase pulse signal processing selection bit 6 timer a3 two-phase pulse signal processing selection bit 7 timer a4 two-phase pulse signal processing selection bit 0: countdown 1: countup this bits is valid when the contents of the up-down flag is selected as the up-down switching factor. 0: two-phase pulse signal processing function is disabled. 1: two-phase pulse signal processing function is enabled. when not using the two-phase pulse signal processing function, be sure to set this bit to 0. this bit is 0 at reading. rw rw rw rw rw wo wo wo note: when writing to bits 5 to 7, use the ldm or sta instruction.
appendix 7733 group user s manual 21-18 appendix 3. control registers timer ai mode register bit 7 5 4 3 1 bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0: timer mode 0 1: event counter mode 1 0: one-shot pulse mode 1 1: pulse width modulation (pwm) mode b1 b0 2 these bits have different functions according to the operat ing mode. 0 operating mode selection bits 6 rw rw rw rw rw rw rw rw timer ai register b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. undefined rw
appendix 7733 group user s manual 21-19 appendix 3. control registers n timer mode clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. 3 gate function selection bits 2 pulse output function selection bit 1 0 operating mode selection bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0: timer mode 0: no pulse is output. (pin tai out functions as a programmable i/o port.) 1: pulse is output. (pin tai out functions as a pulse output pin.) 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 6 count source selection bits b1 b0 b4 b3 5 must be fixed to 0 in the timer mode. 00 0 0 x: no gate function (pin tai in functions as a programmable i/o port.) 1 0: counter counts only while pin tai in s input signal level is l. 1 1: counter counts only while pin tai in s input signal level is h. bit 4 at reset 0 0 0 0 0 0 0 0 rw b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. undefined rw rw rw rw rw rw rw rw rw
appendix 7733 group user s manual 21-20 appendix 3. control registers n event counter mode timer a0 mode register (address 56 16 ) timer a1 mode register (address 57 16 ) b7 b6 b5 b4 b3 b2 b1 b0 5 00 1 bit 4 up-down switching factor selection bit 3 count polarity selection bit bit name 6 these bits are ignored in the event counter mode. 5 must be fixed to 0 in the event counter mode. 7 functions 0: counts at falling edge of external signal 1: counts at rising edge of external signal 0: contents of the up-down flag 1: a signal which is input to pin ta0 out or ta1 out at reset 0 0 0 0 0 rw 2 pulse output function selection bit 0 operating mode selection bits 1 0: no pulse is output. (pin ta0 out or ta1 out functions as a programmable i/o port.) 1: pulse is output. (pin ta0 out or ta1 out functions as a pulse output pin.) 0 1: event counter mode b1 b0 0 0 0 b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (ffff 16 C n + 1) in up- counting. at reading this register, the counter value is read out. undefined bit functions at reset rw rw rw rw rw rw rw rw rw 5
appendix 7733 group user s manual 21-21 appendix 3. control registers b7 b6 b5 b4 b3 b2 b1 b0 timer a2 mode register (address 58 16 ) timer a3 mode register (address 59 16 ) timer a4 mode register (address 5a 16 ) 00 1 bit 4 up-down switching factor selection bit 0 operating mode selection bits bit name 6 count type selection bit 5 must be fixed to 0 in the event counter mode. note: this bit is valid only for the timer a3 mode register. for the timer a2 and a4 mode registers, this bit i s ignored. (it may be 0 or 1. ) 1 7 two-phase pulse signal processing type selection bit (note) functions 0 1: event counter mode b1 b0 0: contents of the up-down flag 1: a signal which is input to pin ta2 out , ta3 out , or ta4 out at reset 0 0 0 0 0 0 rw 2 pulse output function selection bit 0: no pulse is output. (pin ta2 out , ta3 out , or ta4 out functions as a programmable i/o port.) 1: pulse is output. (pin ta2 out , ta3 out , or ta4 out functions as a pulse output pin.) 0 3 count polarity selection bit 0: counting is performed at the falling edge of the external signal. 1: counting is performed at the rising edge of the external signal. 0 0: reload count type 1: free-run count type 0: normal processing 1: quadruple processing b7 b0 b7 b0 (b15) (b8) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (ffff 16 C n + 1) in up-counting. at reading this register, the counter value is read out. undefined timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw rw rw rw rw rw rw rw rw
appendix 7733 group user s manual 21-22 appendix 3. control registers n one-shot pulse mode b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, h level width of the one-shot pulse output from pin tai out is n/fi. undefined fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) 3 trigger selection bits 2 must be fixed to 1 in the one-shot pulse mode. 1 0 operating mode selection bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 1 0: one-shot pulse mode 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 6 count source selection bits b1 b0 b4 b3 5 must be fixed to 0 in the one-shot pulse mode. 10 1 clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. 0 x: writing 1 to the one-shot start flag (pin tai in functions as a programmable i/o ? @ ? @ port.) 1 0: falling edge of the pin tai in s input signal 1 1: rising edge of the pin tai in s input signal bit at reset 0 0 0 0 0 0 0 0 rw 0 4 rw rw rw rw rw rw rw rw wo
appendix 7733 group user s manual 21-23 appendix 3. control registers n pulse width modulation (pmw) mode b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 6 count source selection bits 11 1 clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. at reset 0 0 0 0 0 0 0 0 rw 3 trigger selection bits 2 must be fixed to 1 in the pwm mode. 1 0 operating mode selection bits bit name functions 1 1: pwm mode b1 b0 b4 b3 5 16/8-bit pwm mode selection bit 0 x: writing 1 to the count start flag (pin tai in functions as a programmable i/o port.) 1 0: falling edge of the pin tai in s input signal 1 1: rising edge of the pin tai in s input signal bit 0: the counter operates as a 16-bit pulse width modulator. 1: the counter operates as an 8-bit pulse width modulator. 4 n when operating as an 8-bit pulse width modulator (b15) b7 b0 b7 b0 (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 7 to 0 values 00 16 to ff 16 can be set. assuming that the set value = m, period of the pwm pulse which is output from pin tai out is (m + 1)(2 8 C 1)/fi. fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) 15 to 8 values 00 16 to fe 16 can be set. assuming that the set value = n, h level width of the pwm pulse which is output from pin tai out is n(m +1)/fi. un- defined un- defined b7 b0 b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 values 0000 16 to fffe 16 can be set. assuming that the set value = n, h level width of the pwm pulse which is output from pin tai out is n/fi. un- defined fi: frequency of the count source (f 2 , f 16 , f 64 , or f 512 ) n when operating as a 16-bit pulse width modulator (b15) (b8) rw rw rw rw rw rw rw rw wo wo wo
appendix 7733 group user s manual 21-24 appendix 3. control registers timer bi mode register timer bi register b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. un- defined rw rw rw rw rw rw rw rw bit 7 4 must be fixed to 0 (i = 0). 3 1 bit name at reset 0 0 0 0 un- defined 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 0 0: timer mode 0 1: event counter mode 1 0: pulse period/pulse width measurement mode 1 1: do not select. b1 b0 2 these bits have different functions according to th e operating mode. 0 operating mode selection bits 6 note: in the timer and event counter modes, bit 5 is ignored and undefined at reading. 5 these bits have different functions according to th e operating mode. not implemented (i = 1, 2). 0 un- defined ro (note)
appendix 7733 group user s manual 21-25 appendix 3. control registers n timer mode at reset 0 0 un- defined un- defined 0 0 rw bit 3 bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) b1 b0 b4 b3 0 0 x x x 0 0 0 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 6 count source selection bits 5 this bit is ignored in the timer mode and is undefi ned at reading. clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. un- defined 2 these bits are ignored in the timer mode. 1 0 operating mode selection bits 0 0: timer mode 4 ? timer b0 mode register must be fixed to 0. ? timer b1 and b2 mode registers not implemented. rw rw rw rw rw ro rw rw rw
appendix 7733 group user s manual 21-26 appendix 3. control registers n event counter mode 0 0: counting is performed at the falling edge of the external signal. 0 1: counting is performed at the rising edge of the external signal. 1 0: counting is performed at both falling and rising edges of the external signal. 1 1: do not select. b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) bit 5 this bit is ignored in the event counter mode and is undefined at reading. 4 ? timer b0 mode register must be fixed to 0. 3 2 count polarity selection bits 1 0 operating mode selection bits bit name functions 0 1: event counter mode b1 b0 b3 b2 x 01 6 these bits are ignored in the event counter mode. 7 at reset 0 0 0 un- defined un- defined 0 0 rw 0 ? timer b1 and b2 mode registers not implemented. 0 b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. un- defined xx rw rw rw rw rw ro rw rw rw
appendix 7733 group user s manual 21-27 appendix 3. control registers n pulse period/pulse width measurement mode b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 the result of the pulse period or pulse width measurement is read out. un- defined 0 0: pu l se per i od m eas ur em ent i nt er va l bet w een f al l i ng edges of t he m eas ur em ent pul se ) 0 1: pu l se per i od m eas ur em ent i nt er va l bet w een r i si ng edges of t he m eas ur ement pul se ) 1 0: pu l se wi dt h m eas ur em ent i nt er va l f r om a f al l i ng edge t o a r i si ng edge, and f r om a r i si ng edge t o a f al l i ng edge of t he meas ur ement pul se ) 1 1: do not se l ec t . b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) bit 6 count source selection bits 5 timer bi overflow flag (note) ? timer b0 mode register must be fixed to 0. 3 2 measurement mode selection bits 1 0 operating mode selection bits bit name functions 1 0: pu l se per i od/ pul se wi dt h m eas ur em ent m o d e b1 b0 0: no overflow 1: overflow b3 b2 10 7 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 b7 b6 at reset 0 0 0 un- defined 1 0 0 rw 0 ? timer b1 and b2 mode registers not implemented. 0 clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter 14. clock generating circuit. note: timer bi overflow flag is cleared to 0 when writing to the timer bi mode register is performed with the count start flag = 1. this flag cannot be set to 1 by software. rw rw rw rw rw ro rw rw ro 4
appendix 7733 group user s manual 21-28 appendix 3. control registers n clock timer at reset functions 0 0 un- defined un- defined 0 0 rw bit 3 must be fixed to 0 for the clock timer. b7 b6 b5 b4 b3 b2 b1 b0 timer b2 mode register (address 5d 16 ) 1 0 1 0 0 0 6 these bits are ignored for the clock timer. 5 this bit is ignored for the clock timer. b7 b0 b7 b0 (b15) (b8) timer b2 register (addresses 55 16 and 54 16 ) functions bit at reset rw 15 to 0 values 0000 16 to ffff 16 can be set. assuming that the set value = n, counter divides the count source frequency by (n + 1). at reading this register, the counter value is read out. un- defined 2 must be fixed to 1 for the clock timer. 1 must be fixed to 0 for the clock timer. 0 must be fixed to 1 for the clock timer. 4 not implemented. x 7 xx rw rw rw rw ro rw rw rw
appendix 7733 group user s manual 21-29 appendix 3. control registers processor mode register 0 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits wait bit software reset bit must be fixed to 0. clock f 1 output selection bit (note 2) 0 0 0 0 0 0 0 0: single-chip mode 0 1: memory expansion mode 1 0: microprocessor mode 1 1: do not select. 0: software wait is inserted when accessing external area. 1: no software wait is inserted when accessing external area. microcomputer is reset by setting this bit to 1. this bit is 0 at reading. 0 0: 7 cycles of f 0 1: 4 cycles of f 1 0: 2 cycles of f 1 1: do not select. 0: clock f 1 output is disabled. (p4 2 functions as a programmable i/o port.) 1: clock f 1 output is enabled. 2 functions as a clock f 1 output pin.) 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) (note 1) notes 1: when the vcc-level voltage is applied to pin cnvss, this bit is set to 1 after reset. (at reading, this bit is always 1. ) 2: this bit is ignored in the microprocessor mode. (it may be 0 or 1. ) b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw wo rw rw rw rw interrupt priority detection time selection bits processor mode register 1 b2 b3 b4 b5 b6 b7 b1 processor mode register 1 (address 5f 16 ) b0 bit bit name function at reset 0 7 to1 wait selection bit 0 : wait 0 1 : wait 1 0 not implemented. un- defined rw rw _ (port p4
appendix 7733 group user s manual 21-30 appendix 3. control registers watchdog timer register b7 b0 watchdog timer register (address 60 16 ) bit 7 to 0 watchdog timer is initialized. by writing dummy data to this register, watchdog timer s val ue is initialized to fff 16 (dummy data: 00 16 to ff 16 ). at reset un- defined wo rw functions watchdog timer frequency selection flag 0 : clock f 512 1 : clock f 32 at reset un- defined 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 watchdog timer frequency selection flag (address 61 16 ) bit 7 to 1 not implemented. 0 watchdog timer frequency selection flag bit name clocks f 32 , f 512 : refer to chapter 14. clock generating circuit. rw
appendix 7733 group users manual 21-31 appendix 3. control registers memory allocation control register rom size rom size 3 4 7 to 5 0 0 not implemented. notes 1: the case where value ?5 16 ?is written in of the procedure listed below is not included. 2: when changing these bits, this change must be performed in an area which is internal rom area before and after this change, for example addresses 00c000 16 to 00ffff 16 . also, when changing these bits, be sure to follow the procedure listed below. 3: this figure is applied only to the m37733mhbxxxfp. for the other microcoputers, please refer to the latest datasheets on the english document cd-rom or our web site. bit bit name functions at reset rw 0 1 2 memory allocation selection bits (notes 1 and 2) 0 0 0 0: 124 kbytes, 3968 bytes 0 0 1: 120 kbytes, 3968 bytes 0 1 0: 60 kbytes, 2048 bytes 0 1 1: do not select. 1 0 0: 32 kbytes, 2048 bytes 1 0 1: 16 kbytes, 2048 bytes 1 1 0: 96 kbytes, 3968 bytes 1 1 1: do not select. 0 0 b2b1b0 memory allocation control register (address 63 16 ) (note 3) b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw rw 0 rw un- defined | note: when changing bits 2 to 0, be sure to follow this procedure. procedure by using the ldm instruction, write value ?5 16 ?to address 63 16 . (by this, writing to the memory allocation selection bits is enabled.) by using the ldm instruction, write value ?0000xxx 2 ?to address 63 16 . (values of b2, b1, and b0 shown in the above figure) writing is performed by the next instruction. must be fixed to ?.? (note 1)
appendix 7733 group users manual 21-32 appendix 3. control registers uart2 transmit/receive mode register bit 7 not implemented. 6 parity enable bit (valid in the uart mode.) (note 2) 5 odd/even parity selection bit (valid in the uart mode when the parity enable bit = ??) (note 2) 4 stop bit length selection bit (valid in the uart mode.) (note 2) 3 internal/external clock selection bit 2 @ 1 @ 0 serial i/o mode selection bits (note 1) bit name at reset un- defined 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0 0: serial i/o is ignored. (p7 functions as a programmable i/o port) 0 0 1: clock synchronous serial i/o mode 0 1 0: 0 1 1: 1 0 0: uart mode (transfer data length = 7 bits) 1 0 1: uart mode (transfer data length = 8 bits) 1 1 0: uart mode (transfer data length = 9 bits) 1 1 1: do not select. uart2 transmit/receive mode register (address 64 16 ) notes 1: by specifying these bits, an a-d conversion interrupt or a uart2 transmit/receive interrupt is selected. when bits 2 to 0 = ?00 2 ,?an a-d conversion interrupt is selected. when bits 2 to 0 = ?01 2 ? or ?00 2 to 111 2 ,?a uart2 transmit/receive interrupt is selected. 2: in the clock synchronous serial i/o mode, bits 4 to 6 are ignored. (they may be ??or ?.? b2 b1 b0 0: odd parity 1: even parity 0: parity is disabled. 1: parity is enabled. 0: internal clock 1: external clock 0: one stop bit 1: two stop bits rw rw rw rw rw rw rw do not select. uart2 transmit/receive control register 0 2 cts enable bit bit 1 @ 0 brg count source selection bits bit name at r eset [ functions b7 b6 b5 b4 b3 b2 b1 b0 0 0: clock f 2 0 1: clock f 16 1 0: clock f 64 1 1: clock f 512 uart2 transmit/receive control register 0 (address 68 16 ) b1 b0 0: the cts function is enabled. 1: the cts function is disabled. (p8 0 and p8 4 function as programmable i/o ports.) 3 transmission register empty flag not implemented. 1 0 0 0 7 to 4 rw rw rw rw ro 0: data is present in the transmission register. (transmission is in progress.) 1: no data is present in the transmission @ @ register. (transmission is completed.) un- defined clocks f 2 , f 16 , f 64 , and f 512 : refer to chapter ?4. clock generating circuit.
appendix 7733 group users manual 21-33 appendix 3. control registers oscillation circuit control register 0 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 x cout drivability selection bit main clock stop bit system clock selection bit p o r t - x c selection bit not implemented. 0 0 0 0 un- defined 0 0: drivability low 1: drivability high when the port-xc selection bit = 0, 0: main clock 1: main clock divided by 8 when the port-xc selection bit = 1, 0: main clock 1: sub clock 1 un- defined oscillation circuit control register 0 (address 6c 16 ) b1 b0 b2 b3 b4 b5 b6 b7 notes 0: main clock oscillation or external clock input is available. 1: main clock oscillation or external clock input is stopped. rw rw C not implemented. C rw ( note 1 ) 0: operate as i/o ports (p7 7 , p7 6 ). 1: operate as pins x cin and x cout . rw ( notes 2 and 3 ) rw ( note 2 ) system clock stop bit at wait state (note 4) 0: output is enabled. 1: output is disabled. (refer to tables 12.1.2 and 12.1.5 ) 0: operates in the wait mode. 1: stopped in the wait mode. signal output disable selection bit rw ( note 1 ) 1: nothing can be written to this bit after reset. writing to this bit is enabled when the port-xc selection bit = 1. 2: when selecting the sub clock as the system clock, set bit 3 to 1 after setting bit 4 to 1. if the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to 1 . 3: although this bit can be set to 1, it cannot be cleared t o 0 after this bit is once set to 1. 4: when setting the system clock stop bit at wait state to 1, perform it immediately before the wit instruction is executed. furthermore, clear this bit to 0 immediately after the wait mode is terminated.
appendix 7733 group user? manual 21-34 appendix 3. control registers port function control register bit functions b7 b6 b5 b4 b3 b2 b1 b0 port function control register (address 6d 16 ) bit name 0: pins p0 to p3 are used for the external bus output. 1: pins p0 to p3 are used for the port output. 0 standby state selection bit 1 sub-clock output selection bit/ timer b2 clock source selection bit 0: no internal connection 1: internal connection with timer b2 2 timer b1 internal connect selection bit 3 port p6 pull-up selection bit 0 0: no pull-up for pins p5 4 /ta2 out /ki 0 to p5 7 /ta3 in /ki 3 1: with pull-up for pins p5 4 /ta2 out /ki 0 to p5 7 /ta3 in /ki 3 6 port p5 pull-up selection bit 7 key input interrupt selection bit 0: int 2 interrupt 1: key input interrupt 5 port p6 pull-up selection bit 1 4 must be fixed to ?. at reset rw rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 0 ?ort-x c selection bit ] = ?? (when the sub clock is not used) timer b2 (event counter mode) clock source selection (note 1) 0: tb2 in input (event counter mode) 1: main clock divided by 32 (clock timer) ?ort-x c selection bit = ?? (when the sub clock is used) sub-clock output selection 0: pin p6 7 /tb2 in / sub functions as a programmable i/o port. 1: sub clock sub is output from pin p6 7 /tb2 in / sub . (note 2) notes 1: when the port-xc selection bit = ??and timer b2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: when timer b1 operates in the event counter mode, bit 2 is valid. ?ey input interrupt selection bit = ? 0: no pull-up for pin p6 4 /int 2 1: with pull-up for pin p6 4 /int 2 ?ey input interrupt selection bit = ? 0: pin p6 4 /int 2 is a port with no pull-up. 1: pin p6 4 /int 2 is an input pin with pull-up and is used for the key input interrupt. 0: no pull-up for pins p6 2 /int 0 and p6 3 /int 1 1: with pull-up for pins p6 2 /int 0 and p6 3 /int 1 port-xc selection bit ] : bit 4 of the oscillation circuit control register 0 (addr ess 6c 16 )
appendix 7733 group user? manual 21-35 appendix 3. control registers serial transmit control register bit bit name at reset rw functions b7 b6 b5 b4 b3 b2 b1 b0 serial transmit control register (address 6e 16 ) h when using multiple transfer clock output pins, satisfy the following conditions: l serial i/o mode selection bits (bits 2 to 0 at address 30 16 ) = ?01 2 l internal/external clock selection bit (bit 3 at address 30 16 ) = ? l cts / rts enable bit (bit 4 at address 34 16 ) = ? l receive enable bit (bit 2 at address 35 16 ) = ??(for cases and in table 8.3.4) l transmission clock output pin selection bits = ?1 2 ? ?0 2 ? or ?1 2 ? (refer to table 8.3.3 .) note: bits 4 and 5 are ignored in the uart mode. (they may be ?? or ?.? not implemented. un- defined 4 transmission clock output pin selection bits (valid only in the clock synchronous serial i/o mode.) (note) 0 0 0: one transfer clock output pin (clk 0 ) 0 1: 1 0: 1 1: 5 0 0 3 to 0 7, 6 not implemented. value ??is read out from here. b5 b4 multiple transfer clock output pins rw rw
appendix 7733 group users manual 21-36 appendix 3. control registers oscillation circuit control register 1 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa a aaaaaaaaaaaaa a a aaaaaaaaaaaaa a a aaaaaaaaaaaaa a a aaaaaaaaaaaaa a aaaaaaaaaaaaaaa bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to ??in the one time prom and eprom versions (notes 1 and 2) . must be fixed to ?? (note 2) . clock prescaler reset bit 0 0 0 0 undefined 0 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input from the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. a a b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown in figure 10.2.3. by writing ??to this bit, clock prescaler is initialized. rw 1 (note 3) 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. ignored in the mask rom and external rom versions. 2: the case where data ?1010101 2 ?is written with the procedure shown in figure 10.2.3 is not included. 3: in the 7735 group, fix this bit to ?. (note 1) (note 1) (note 1) write data ?1010101 2 .?( ldm instruction) ?when writing to bits 0 to 3 write data ?0001xxx 2 .?( ldm instruction) next instruction (b3 in figure 10.2.2) (b2 to b0 in figure 10.2.2) write data ?0 16 .?( ldm instruction) ?when performing clock prescaler reset
appendix 7733 group users manual 21-37 appendix 3. control registers interrupt control register int 0 , int 1 , and int 2 /key input interrupt control registers (addresses 7d 16 to 7f 16 ) b2b1b0 0 0 0: level 0 (interrupt is disabled.) 0 0 1: level 1 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 rw 0 a-d / uart2 trans./rece., uart0 and 1 transmission, uart0 and 1 receive, timers a0 to a4, timers b0 to b2 interrupt control registers (addresses 70 16 to 7c 16 ) b7 b6 b5 b4 b3 b2 b1 b0 bit bit name functions at reset rw 0 2 3 4 5 6 7 1 b2b1b0 0 0 0 : level 0 (interrupt is disabled.) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 0 not implemented. 0 0 interrupt priority level selection bits interrupt request bit 0 un- defined 0: no interrupt request has occurred. 1: interrupt request has occurred. 0: interrupt request bit is set to 1 at h level when level sense is selected; this bit is set to 1 at falling edge when edge sense is selected. 1: interrupt request bit is set to 1 at l level when level sense is selected; this bit is set to 1 at rising edge when level sense is selected. b7 b6 b5 b4 b3 b2 b1 b0 bit bit name functions rw 0 2 3 1 rw 0 rw 0 interrupt priority level selection bits interrupt request bit (note) 0: no interrupt request has occurred. 1: interrupt request has occurred. 0 rw 4 5 polarity selection bit level sense/edge sense selection bit 0: edge sense 1: level sense rw 0 0 at reset 6 7 un- defined not implemented. note: the interrupt request bits of int 0 to int 2 /key input interrupts are ignored when the level sense is se lected. rw rw rw rw rw rw
appendix 7733 group users manual 21C38 appendix 4. package outlines appendix 4. package outlines
appendix 7733 group users manual 21C39 appendix 4. package outlines
appendix 7733 group users manual 21C40 appendix 4. package outlines
appendix 7733 group users manual 21C41 appendix 5. hexadecimal instruction code table appendix 5. hexadecimal instruction code table instruction code table-1 d 3 d 0 d 7 d 4 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0123456789 bcdef brk bpl bmi rti bvc rts bvs bcc bcs bne beq jsr abs bra rel ldy imm cpx imm cpy imm ora a,(dir,x) ora a,(dir),y and a,(dir,x) eor a,(dir,x) eor a,(dir),y adc a,(dir,x) adc a,(dir),y sta a,(dir,x) lda a,(dir,x) and a,(dir),y sta a,(dir),y lda a,(dir),y cmp a,(dir),y cmp a,(dir,x) sbc a,(dir,x) sbc a,(dir),y ora a,(dir) jsr abl and a,(dir) note 1 eor a,(dir) per adc a,(dir) sta a,(dir) lda a,(dir) cmp a,(dir) sbc a,(dir) bra rel ldx imm clp imm sep imm ora a,sr a ora a,dir seb dir,b asl dir ora a,l(dir) ora a,imm ora a,abs php phd asl a seb abs,b asl abs ora a,(sr),y ora a,l(dir),y clb dir,b ora a,dir,x asl dir,x clc tas ora a,abs,y dec a clb abs,b ora a,abs,x asl abs,x and a,sr bbs dir,b,r and a,dir rol dir and a,l(dir) plp pld and a,imm rol a bbs abs,b,r and a,abs rol abs and a,(sr),y bbc dir,b,r and a,dir,x rol dir,x and a,l(dir),y sec and a,abs,y inc a tsa bbc abs,b,r and a,abs,x rol abs,x eor a,sr mvp eor eor eor eor a,dir lsr dir a,l(dir) pha a,imm lsr a phg jmp abs a,abs lsr abs eor a,(sr),y a,(sr),y a,(sr),y a,(sr),y a,(sr),y a,(sr),y mvn eor eor eor eor lsr lsr cli tad phy jmp a,dir,x a,dir,x a,dir,x a,dir,x a,dir,x a,dir,x dir,x dir,x dir,y dir,y dir,x dir,x a,l(dir),y a,l(dir),y a,l(dir),y a,l(dir),y a,l(dir),y a,l(dir),y a,abs,y a,abs,y a,abs,y a,abs,y a,abs,y a,abs,y abl (abs) abs abs abs abs a,abs,x a,abs,x a,abs,x a,abs,x a,abs,x a,abs,x abs,x abs,x abs,x abs,y abs,x abs,x adc adc adc adc adc ror ror ror jmp rtl pla ldm a,sr a,sr a,sr a,sr a,sr dir dir dir dir dir a,dir a,dir a,dir a,dir a,dir dir dir dir dir dir a,l(dir) a,l(dir) a,l(dir) a,l(dir) a,l(dir) a,imm a,imm a,imm a,imm a a,abs abs a,abs abs a,abs abs a,abs abs a,abs abs adc adc adc adc adc jmp ror ror ldm dir,x dir,x dir,x sei tda ply (abs,x) sta sty sta sta sta stx sty stx dey txa pht note 2 sta sta sta sta sta sty stx txs txy tya ldm ldm lda lda ldy lda lda lda ldx ldx ldy plt tax tay lda lda ldy lda ldx lda tyx tsx clv abs,x lda ldx ldy cmp cmp cmp cmp cmp cpy dec cpy dec cmp dec iny dex wit cmp cmp cmp dec clm cmp phx stp jmp l(abs) pei sbc sbc sbc sbc sbc ora a,abl ora a,abl,x and a,abl and a,abl,x eor a,abl eor a,abl,x a,abl,x a,abl,x a,abl,x a,abl,x a,abl,x adc a,abl a,abl a,abl a,abl a,abl adc sta sta lda lda cmp cmp sbc sbc sbc sbc cpx cpx inc inc inx inc sbc pea sbc sbc inc sem plx nop psh pul jsr abs (abs,x) notes 1: 42 16 specifies the contents of the instruction code table-2. about the second word? codes, refer to the instruction code table-2. 2: 89 16 specifies the contents of the instruction code table-3. about the second word? codes, refer to the instruction code table-2.
appendix 7733 group users manual 21C42 appendix 5. hexadecimal instruction code table instruction code table-2 (the first words code of each instruction is 42 16 ) d 3 d 0 d 7 d 4 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0123456789 bcdef ora b,(dir,x) ora b,(dir),y and b,(dir,x) eor b,(dir,x) eor b,(dir),y adc b,(dir,x) adc b,(dir),y sta b,(dir,x) lda b,(dir,x) and b,(dir),y sta b,(dir),y lda b,(dir),y cmp b,(dir),y cmp b,(dir,x) sbc b,(dir,x) sbc b,(dir),y ora b,(dir) and b,(dir) eor b,(dir) adc b,(dir) sta b,(dir) lda b,(dir) cmp b,(dir) sbc b,(dir) ora b,sr a ora b,dir ora b,l(dir) ora b,imm ora b,abs asl b ora b,(sr),y ora b,l(dir),y ora b,dir,x tbs ora b,abs,y dec b ora b,abs,x and b,sr and b,dir and b,l(dir) and b,imm rol b and b,abs and b,(sr),y and b,dir,x and b,l(dir),y and b,abs,y inc b tsb and b,abs,x eor b,sr eor eor eor eor b,dir b,l(dir) phb b,imm lsr b b,abs eor b,(sr),y b,(sr),y b,(sr),y b,(sr),y b,(sr),y b,(sr),y eor eor eor eor tbd b,dir,x b,dir,x b,dir,x b,dir,x b,dir,x b,dir,x b,l(dir),y b,l(dir),y b,l(dir),y b,l(dir),y b,l(dir),y b,l(dir),y b,abs,y b,abs,y b,abs,y b,abs,y b,abs,y b,abs,y b,abs,x b,abs,x b,abs,x b,abs,x b,abs,x b,abs,x adc adc adc adc adc ror plb b,sr b,sr b,sr b,sr b,sr b,dir b,dir b,dir b,dir b,dir b,l(dir) b,l(dir) b,l(dir) b,l(dir) b,l(dir) b,imm b,imm b,imm b,imm b b,abs b,abs b,abs b,abs b,abs adc adc adc adc adc tdb sta sta sta sta txb sta sta sta sta sta tyb lda lda lda lda lda tbx tby lda lda lda lda lda cmp cmp cmp cmp cmp cmp cmp cmp cmp cmp sbc sbc sbc sbc sbc ora b,abl ora b,abl,x and b,abl and b,abl,x eor b,abl eor b,abl,x b,abl,x b,abl,x b,abl,x b,abl,x b,abl,x adc b,abl b,abl b,abl b,abl b,abl adc sta sta lda lda cmp cmp sbc sbc sbc sbc sbc sbc sbc
appendix 7733 group users manual 21C43 appendix 5. hexadecimal instruction code table instruction code table-3 (the first words code of each instruction is 89 16 ) d 3 d 0 d 7 d 4 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0123456789 bcdef mpy (dir,x) mpy (dir),y div (dir,x) div (dir),y mpy (dir) div (dir) mpy sr a mpy dir mpy l(dir) mpy imm mpy abs mpy (sr),y mpy l(dir),y mpy dir,x mpy abs,y mpy abs,x div sr div dir div l(dir) div imm div abs div (sr),y div dir,x div l(dir),y div abs,y div abs,x rla imm imm ldt mpy abl mpy abl,x div abl div abl,x xab
appendix 7733 group users manual 21C44 a cc ,c ? a cc +m+c a cc ? a cc m symbol functions details adds the carry, the accumulator and the memory contents.the result is entered into the accumulator. when the d flag is 0, binary additions is done, and when the d flag is 1, decimal addition is done. obtains the logical product of the contents of the accumu- lator and the contents of the memory . the result is en- tered into the accumulator. shifts the accumulator or the memory contents one bit to the left. 0 is entered into bit 0 of the accumulator or the memory. the contents of bit 15 ( bit 7 when the m flag is 1) of the accumulator or memory before shift is entered into the c flag. tests the specified bit of the memory. branches when all the contents of the specified bit is 0. tests the specified bit of the memory. branches when all the contents of the specified bit is 1. branches when the contents of the c flag is 0. branches when the contents of the c flag is 1. branches when the contents of the z flag is 1. branches when the contents of the n flag is 1. branches when the contents of the z flag is 0. branches when the contents of the n flag is 0. jumps to the address indicated by the program counter plus the offset value. executes software interruption. branches when the contents of the v flag is 0. branches when the contents of the v flag is 1. makes the contents of the specified bit in the memory 0. makes the contents of the c flag 0. makes the contents of the i flag 0. specifies the bit position in the processor status register by the bit pattern of the second byte in the instruction, and sets 0 in that bit. makes the contents of the v flag 0. compares the contents of the accumulator with the con- tents of the memory. mb=0? mb=1? c=0? c=1? z=1? n=1? z=0? n=0? pc ? pc offset pg ? pg+1 ( when carry occurs ) pg ? pgC1 ( when borrow occurs ) pc ? pc+2 m(s) ? pg s ? sC1 m(s) ? pc h s ? sC1 m(s) ? pc l s ? sC1 m(s) ? ps h s ? sC1 m(s) ? ps l s ? sC1 i ? 1 pc l ? ad l pc h ? ad h pg ? 00 16 v=0? v=1? c ? 0 mb ? 0 makes the contents of the m flag 0. i ? 0 m ? 0 psb ? 0 v ? 0 a cc Cm imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y op n n op addressing modes and (notes 1,2) adc (notes 1,2) asl (note 1) bbc (notes 3,5) bbs (notes 3,5) bcc (note 3) bcs (note 3) beq (note 3) bmi (note 3) bne (note 3) bpl (note 3) bra (note 4) brk bvc (note 3) bvs (note 3) clb (note 5) clc cli clm clv cmp (notes 1,2) clp n n op n 58 d8 1 1 1 21 29 c2 222 61 72 71 2 3 42 75 3 42 72 3 42 61 3 42 71 10 3 2 35 32 2 21 31 82 43 3 42 32 3 42 21 3 4 1 2 72 16 72 3 4 2 4 d5 42 31 10 3 c1 d1 42 d1 8 10 2 3 42 c1 2 2 3 2 3 6 2 3 7 5 7 2 5 7 5 8 6 8 6 8 6 m=0 c ? b 15 b 0 ? 0 m=1 c ? b 7 b 0 ? 0 # op n# op n# op n# 69 2 65 2 4 42 69 43 42 65 6 75 72 # op op n# op # op #n# # 8 9 22 25 472 42 29 3 42 25 6 42 35 93 0a 2 06 42 0a 00 15 2 14 8 18 2 2 2 2 b8 c9 42 c9 42 c5 4 c5 42 d5 42 d2 d2 7 93 2 appendix 6. machine instructions appendix 6. machine instructions
appendix 7733 group users manual 21C45 processor status register addressing modes l(dir) l(dir),y abl,x (abs) stk rel sr (sr),y blk abs,b abs,x abs,y dir,b,r abs,b,r ( abs,x ) 30 op op op n n n n n n n n abs ipl n v m c 2 85 64 diz n op op op n n n op op n op 67 42 67 10 2 3 42 77 3 4 42 7d 6 8 3 4 42 79 8 3 4 6 8 4 5 42 7f 7 9 4 5 op 63 5 7 2 3 73 10 3 42 23 5 7 2 3 33 42 33 8 10 2 3 10 2 37 12 3 42 37 0e 3 663 2f 64 3f 74 42 3d 8 3 4 42 39 84 42 2f 5 8 42 3f 95 1e 83 ??nv? x ?? ?zc ? z ? ? ? ? ? n ? ??n?? ?? ?zc 5 3c 8 4 7 90 42 24 74 2c 85 b0 f0 30 4 4 4 2 2 2 2 4 d0 10 42 82 4 4 2 3 50 42 2 4 ic 94 ???????? ? ? ? ? ? ? ? ? ? ? ? ? ???? ???? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ?? ????? ???? ????? ?? ?? ????? ? ? ? ? ? ? ? ? ? ? ? ??? ? ?????? 0 ? ? ? ? ? ? ? ? ? ? ???? ???0?? ? ? c ? ? z ? ? ? ? ? ? ? ? ? 0 ? ? ? 0 ? ? ? ? ? ? ? ? ? ? ? c3 52 8 d3 2 42 d3 3 10 3 7 42 c3 c7 10 2 d7 11 2 cd 3 dd 63 42 c7 3 13 34 d9 63 84 84 cf 64 df 74 85 95 42 df op # op ## # op op # op #n# # # op ## op # n#n# op # 1 7 ## l(abs) abl # nn 77 11 2 6d 4 7d 6 79 6f 7f 2 8 42 73 42 63 42 6f 42 6d 13 36 12 27 11 2 2d 3 3d 39 23 42 27 13 3 42 2d 4 64 7 34 80 ? 70 12 42 d7 42 cd 4 6 42 dd 42 d9 42 cf 9 10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? specified flag be- comes 0. n appendix 6. machine instructions
appendix 7733 group users manual 21C46 symbol functions details imp imm dir dir,b dir,x dir,y (dir) (dir,x) (dir),y n op op op n nn op n op addressing modes compares the contents of the index register x with the contents of the memory. compares the contents of the index register y with the contents of the memory. decrements the contents of the accumlator or memory by 1. decrements the contents of the index register x by 1. decrements the contents of the index register y by 1. the numeral that places the contents of accumlator b to the higher order and the contents of accumulator a to the lower order is divided by the contents of the memory. the quotient is entered into accumula- tor a and the remainder into accumulator b. logical exclusive sum is obtained of the contents of the accumulator and the contents of the memory. the result is placed into the accumulator. increments the contents of the accumulator or memory by 1. increments the contents of the index register x by 1. increments the contents of the index register y by 1. places a new address into the program counter and jumps to that new address. xCm yCm a cc ? a cc C1 or m ? mC1 x ? xC1 y ? yC1 a(quotient) ? b,a/m b(remainder) a cc ? a cc m a cc ? a cc +1 or m ? m+1 x ? x+1 y ? y+1 abs pc l ? ad l pc h ? ad h abl pc l ? ad l pc h ? ad h pg ? ad g (abs) pc l ? (ad h , ad l ) pc h ? (ad h ,ad l +1) l(abs) pc l ? (ad h , ad l ) pc h ? (ad h , ad l +1) pg ? (ad h , ad l +2) (abs, x) pc l ? (ad h , ad l +x) pc h ? (ad h , ad l +x +1) abs m(s) ? pc h s ? sC1 m(s) ? pc l s ? sC1 pc l ? ad l pc h ? ad h abl m(s) ? pg s ? sC1 m(s) ? pc h s ? sC1 m(s) ? pc l s ? sC1 pc l ? ad l pc h ? ad h pg ? ad g (abs, x) m(s) ? pc h s ? sC1 m(s) ? pc l s ? sC1 pc l ? (ad h , ad l +x) pc h ? (ad h , ad l +x +1) cpx (note 2) cpy (note 2) dec (note 1) dex dey div (notes 2,10) eor (notes 1,2) inc (note 1) inx jmp iny jsr saves the contents of the program counter (also the con- tents of the program bank register for abl) into the stack, and jumps to the new address. n op nn op op n op op n e0 2 e4 42 c4 4 2 1a 21 42 c6 72 d6 21 2 89 29 89 25 29 3 89 35 30 3 89 32 31 3 89 21 32 3 89 31 33 3 49 2 45 42 55 52 62 72 51 82 42 49 42 45 63 42 55 73 42 52 83 42 41 93 10 3 3a 21 42 3a 42 e6 77 e8 c8 21 2 ### # ### ### a 2 c0 2 2 2 7 42 1a 88 ca 1 3 27 41 52 42 51 f6 43 2 1 2 2 appendix 6. machine instructions
appendix 7733 group users manual 21C47 1 processor status register addressing modes l(dir),y abl abl,x (abs) l(abs) stk rel (sr),y blk abs,y dir,b,r abs,b,r ( abs,x ) 30 op # op op op n n n n op n n n abs op ipl n v m c 2 85 64 10 9 diz n nn op op n op n op n op op n n op 3 op ??n? ? x ?? ?z 4 op 47 42 47 35 10 12 3 2 3 89 37 57 42 57 3 36 11 13 2 3 4 42 4d ee 20 83 31 89 2f 31 5 89 3f 32 5 89 3d 31 4 5d 63 42 5d 84 fe 3 8 59 42 59 6 84 3 42 4f 85 4f 64 42 5f 5f 95 74 5c 44 22 84 dc 33 86 7c 3 3 fc 8 89 23 30 3 89 33 73 43 42 43 52 42 53 53 10 3 33 8 3 2 ??n?? ???zc ? ?? n? ? ?z ?? ? z ? ? ? ? n ? ? ?? ? ? n? ? ??z? ? vc z ? ? ? ? ? ?n ? ?? n? ? ?z ?? ? ?? n? ? ?z ?? ?? ??? ?????? ?????????? ??n? ?? ?? ? ?? ? ???? ? nz z l(dir) abs,b abs,x ### # op ## n# # ## n op op ##n# sr #### 7 ? ? ? c ? ? ? ? ? ? ? cc ec 43 ce 73 de 89 27 89 2d 29 89 39 4 3 4 4d 64 3 7 3 2 4c 3 6 4 6c appendix 6. machine instructions
appendix 7733 group users manual 21C48 symbol functions details imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y # n op n op n op n op addressing modes a cc ? m m ? imm dt ? imm x ? m y ? m m=0 0 ? b 15 b 0 ? c m=1 0 ? b 7 b 0 ? c enters the contents of the memory into the accummulator. enters the immediate vaiue into the memory. enters the immediate value into the data bank regiater. enters the contents of the memory into index register x. enters the contents of the memory into index register y. shifts the contents of the accumulator or the contents of the memory one bit to the right. the bit 0 of the accumu- lator or the memory is entered into the c flag. 0 is en- tered into bit 15 (bit 7 when the m flag is 1.) b, a ? a ] m mn+i ? mm+i mnCi ? mmCi pc ? pc+1 a cc ? a cc vm m(s) ? imm 2 s ? sC1 m(s) ? imm 1 s ? sC1 m(s) ? m((dpr)+imm +1) s ? sC1 m(s) ? m((dpr)+imm) s ? sC1 ear ? pc+imm 2 ,imm 1 m(s) ? ear h s ? sC1 m(s) ? ear l s ? sC1 m=0 m(s) ? a h s ? sC1 m(s) ? a l s ? sC1 m=1 m(s) ? a l s ? sC1 m=0 m(s) ? b h s ? sC1 m(s) ? b l s ? sC1 m=1 m(s) ? b l s ? sC1 transmits the data block. the transmission is done from the lower order address of the block. advances the program counter, but pertorms nothing else. logical sum per bit of the contents of the accumulator and the contents of the memory is obtained. the result is en- tered into the accumulator. the 3rd and the 2nd bytes of the instruction are saved into the stack, in this order. specifies 2 sequential bytes in the direct page in the 2nd byte of the instruction, and saves the contents into the stack. regards the 2nd and 3rd bytes of the instruction as 16-bit numerals, adds them to the program counter, and saves the result into the stack. saves the contents of accumulator a into the stack. saves the contents of accumuator b into the stack. lda (notes 1,2) ldm (note 5) ldt ldx (note 2) ldy (note 2) lsr (note 1) mpy (notes 2,11) mvn (note 8) mvp (note 9) nop ora (notes 1,2) pea pei per pha phb n op nn op op op n n op op n 252 b2 62 2 43 74 53 a6 42 2 2 a4 42 5 2 21 46 72 56 72 89 09 16 3 89 05 89 15 19 3 89 12 20 333 21 09 22 05 42 05 4 6 2 3 52 3 7 42 15 12 6 8 2 3 01 42 01 7 9 2 3 11 42 11 10 3 3 463 3 7 42 b2 3 8933 10 2 42 09 multiplies the contents of accumulator a and the contents of the memory. the higher order of the result of operation are entered into accumulator b, and the lower order into accumulator a. transmits the data block. transmission is done form the higher order address of the data block. ### ###### a9 22 42 a9 89 c2 53 64 42 a5 a5 4 b5 42 b5 a1 42 a1 72 b1 42 b1 8 b6 5 b4 a0 a2 2 2 2 4a 42 4a 2 4 89 11 22 89 01 21 18 3 ea 43 15 42 12 8 appendix 6. machine instructions
appendix 7733 group users manual 21C49 1 processor status register addressing modes abl abl,x (abs) stk (sr),y abs,x abs,y abs,b,r ( abs,x ) 30 op n op n n n n n abs ipl n v m c 2 87 5 64 10 9 diz n n op n op n op n op op ?n? x ?? op op n op op op op op n op op op n op a7 2 b7 11 2 ad 43 3 b9 63 af 64 bf 7 n a3 52 b3 42 a7 3 13 3 42 ad 42 bd 4 42 b9 84 42 af 85 42 bf 9 4 5 42 a3 73 42 b3 10 3 9c 54 4 43 be 63 ac 43 3 4e 73 3 89 07 24 33 89 0d 44 89 19 20 4 89 0f 20 5 89 03 19 3 07 10 2 17 11 2 0d 43 89 1f 21 5 1d 63 19 63 0f 64 1f 74 03 52 13 82 42 07 12 3 42 17 13 3 42 0d 64 42 1d 84 42 19 84 42 0f 85 42 1f 95 42 03 73 42 13 10 3 f4 53 d4 62 62 53 48 41 42 48 62 54 73 i + 5 7 2 3 9 + i 5 7 2 ????z ???? ?????? ?? ? ? ?? ?? ? ? ? ? ? n n? ?? ? ? ? ??z? ? z ? ? ? ? ? ? ? ? ? 0 n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? z z ? c 0 ? ? ? ? ? ? ? ? ? z ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ### ## # ###n# ### #### ? ? ? ? ? ? ? ? ? ? ? ? blk sr dir,b,r 44 rel l(abs) abs,b l(dir),y l(dir) # 10 12 n 42 b7 4 6 bd n 6 8 6 9e bc 5e ae 89 17 25 18 89 1d 20 3 2 8 89 13 22 6 8 appendix 6. machine instructions
appendix 7733 group users manual 21C50 symbol functions details imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y op n op n n n n nn n n addressing modes phd m(s) ? dpr h s ? sC1 m(s) ? dpr l s ? sC1 saves the contents of the direct page register into the stack. m(s) ? pg s ? sC1 m(s) ? ps h s ? sC1 m(s) ? ps l s ? sC1 m(s) ? dt s ? sC1 x=0 m(s) ? x h s ? sC1 m(s) ? x l s ? sC1 x=1 m(s) ? x l s ? sC1 x=0 m(s) ? y h s ? sC1 m(s) ? y l s ? sC1 x=1 m(s) ? y l s ? sC1 m=0 s ? s+1 a l ? m(s) s ? s+1 a h ? m(s) m=1 s ? s+1 a l ? m(s) m=0 s ? s+1 b l ? m(s) s ? s+1 b h ? m(s) m=1 s ? s+1 b l ? m(s) s ? s+1 dpr l ? m(s) s ? s+1 dpr h ? m(s) s ? s+1 ps l ? m(s) s ? s+1 ps h ? m(s) s ? s+1 dt ? m(s) x=0 s ? s+1 x l ? m(s) s ? s+1 x h ? m(s) x=1 s ? s+1 x l ? m(s) phg php pht phx phy saves the contents of the program bank register into the stack. saves the contents of the program status register into the stack. saves the contents of the data bank register into the stack. saves the contents of the index register x into the stack. saves the contents of the index register y into the stack. pla restores the contents of the stack on the accumulator a. restores the contents of the stack on the accumulator b. restores the contents of the stack on the direct page reg- ister. restores the contents of the stack on the processor status register. restores the contents of the stack on the data bank reg- ister. restores the contents of the stack on the index register x. plb pld plp plt plx op op op op op op op # # # # # # # # # # op n appendix 6. machine instructions
appendix 7733 group users manual 21C51 processor status register addressing modes l(dir) l(dir),y abl abl,x (abs) l(abs) stk sr (sr),y blk abs,b abs,x abs,y dir,b,r abs,b,r ( abs,x ) 10 98 76 5 2 30 op n op op op op op op op n op n op op op op op n n n n op n n op op n n n n op n n n n n abs 41 31 4 08 1 8b 3 1 41 5a 41 68 51 42 72 2b 1 1 6 28 ab 61 fa 51 68 ipl n v m x d i c z ? ? ? ? ? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z? 5 value saved in stack. ? ? ? ? ?? 0b da 41 ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? 4b #### ## # ########### rel appendix 6. machine instructions
appendix 7733 group users manual 21C52 3 symbol functions details imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y op n op op n op n n op op n op nn op op n op addressing modes ply x=0 s ? s+1 y l ? m(s) s ? s+1 y h ? m(s) x=1 s ? s+1 y l ? m(s) restores the contents of the stack on the index register y. m(s) ? a, b, x saves the registers among accumulator, index register, direct page register, data bank register, program bank register, or processor status register, specified by the bit pattern of the second byte of the instruction into the stack. restores the contents of the stack to the registers among accumulator, index register, direct page register, data bank register, or processor status register, specified by the bit pattern of the second byte of the instruction. m=0 n bit rotate left ? b 15 b 0 ? m=1 n bit rotate left ? b 7 b 0 ? a, b, x ? m(s) psh (note 6) pul (note 7) rla (note 13) rotates the contents of the accumulator a, n bits to the left. m=0 ? b 15 b 0 ? c ? m=1 ? b 7 b 0 ? c ? rol (note 1) links the accumulator or the memory to c flag, and rotates result to the left by 1 bit. m=0 ? c ? b 15 b 0 ? m=1 ? c ? b 7 b 0 ? ror (note 1) links the accumulator or the memory to c flag, and rotates result to the right by 1 bit. s ? s+1 ps l ? m(s) s ? s+1 ps h ? m(s) s ? s+1 pc l ? m(s) s ? s+1 pc h ? m(s) s ? s+1 pg ? m(s) s ? s+1 pc l ? m(s) s ? s+1 pc h ? m(s) s ? s+1 pg ? m(s) s ? s+1 pc l ? m(s) s ? s+1 pc h ? m(s) a cc , c ? a cc CmCc rti rtl rts sbc (notes 1,2) returns from the interruption routine. returns from the subroutine. the contents of the program bank register are also restored. returns from the subroutine. the contents of the program bank register are not restored. subtracts the contents of the memory and the borrow from the contents of the accumulator. 81 6b 60 51 40 11 1 6a 21 66 72 42 4 2 6a 72 1 2 26 72 36 7 2 2a 42 42 89 63 49 2 2 e5 4 2 f5 5 26 f2 2 e1 7 2 f1 2 3 42 9 f1 e1 42 83 f2 42 73 f5 42 63 e5 4 e9 3 2a 76 + i e9 42 8 10 42 # ##n# ###### n appendix 6. machine instructions
appendix 7733 group users manual 21C53 processor status register addressing modes l(dir) l(dir),y abl abl,x (abs) l(abs) stk rel sr (sr),y blk abs,b abs,x abs,y dir,b,r abs,b,r ( abs,x ) 10 98 76 5 2 30 op n op op op op op op op op op op op op op n n n n op n op op n n n op n n n n n abs 1 ipl v m x d i c z 7a 41 ? ? ? n ?? ? ? ? z? ? ? ? ? ?? ? ? ? ?? n if restored the contents of ps, it becomes its value. and the other cases are no change. ? ? ? n ?? ? ? ? z ? ? ? n v? ? ? ? z c ? ? ? ? ?? ? ? ? ?? value saved in stack. ? ? ? n ?? ? ? ? z c ? ? ? ? ?? ? ? ? ?? 5 eb 12 2 2 14 fb 3i 1 +4i 2 3e 83 6e 3 8 7e 2e 73 73 52 e3 ed e7 f7 2 f7 11 2 10 ed 43 4 42 12 3 42 6 42 13 3 f9 ef ff 84 42 8 42 485 42 9 fd 63 f9 63 ef 6 ff 74 82 f3 42 73 42 10 3 e3 f3 ? ? ? ? ?? ? ? ? ?? # ## # n# # n n# # # # n # # # # # # # # e7 42 fd 4 5 c + 2i 1 +i 2 + appendix 6. machine instructions
appendix 7733 group users manual 21C54 symbol functions details imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y op n op op n op n n op op n op nn op op op addressing modes makes the contents of the specified bit in the memory 1. makes the contents of the i flag 1. makes the contents of the m flag 1. set the specified bit of the processor status register's lower byte (ps l ) to 1. stores the contents of the accumulator into the memory. stops the oscillation of the oscillator. stores the contents of the index register x into the memory. stores the contents of the index register y into the memory. transmits the contents of the accumulator a to the direct page register. transmits the contents of the accumulator a to the stack pointer. transmits the contents of the accumulator a to the index register x. transmits the contents of the accumulator a to the index register y. transmits the contents of the accumulator b to the direct page register. transmits the contents of the accumulator b to the stack pointer. transmits the contents of the accumulator b to the index register x. transmits the contents of the accumulator b to the index register y. transmits the contents of the direct page register to the accumulator a. transmits the contents of the direct page register to the accumulator b. makes the contents of the c flag 1. seb (note 5) mb ? 1 sec sei sem sep sta (note 1) stp stx sty tad tas c ? 1 i ? 1 m ? 1 psb ? 1 m ? a cc m ? x m ? y dpr ? a s ? a x ? a y ? a dpr ? b s ? b tax tay tbd tbs tdb x ? b tbx tby tda y ? b a ? dpr b ? dpr 42 2 2 04 83 38 21 78 21 2 f8 1 2 3 db 31 2 4 85 42 6 85 3 3 9 42 3 9 42 7 42 2 5 95 72 81 72 91 72 91 3 81 92 95 2 4 86 2 4 84 52 96 94 2 5 5b 21 1b 21 aa 21 a8 21 4 42 2 5b 42 42 1b 42 aa 42 4 a8 7b 21 42 4 7b transmits the contents of the stack pointer to the accumulator a. transmits the contents of the stack pointer to the accu- mulator b. a ? s b ? s tsa tsb 3b 21 42 42 transmits the contents of the stack pointer to the index register x. transmits the contents of the index register x to the ac- cumulator a. x ? s a ? x tsx txa transmits the contents of the index register x to the ac- cumulator b. transmits the contents of the index register x to the stack pointer. b ? x s ? x txb txs transmits the contents of the index register x to the index register y. y ? x txy transmits the contents of the index register y to the ac- cumulator a. a ? y tya tyb b ? y transmits the contents of the index register y to the index register x. stops the internal clock. exchanges the contents of the accumulator a and the con- tents of the accumulator b. tyx wit xab x ? y a b ? ? ba 21 21 42 2 4 8a 9a 21 9b 21 98 21 42 42 98 transmits the contents of the index register y to the ac- cumulator b. bb 21 cb 31 2 6 89 28 8a 3b e2 92 9 3 42 ###n# ### n# # # n appendix 6. machine instructions
appendix 7733 group users manual 21C55 addressing modes l(dir) l(dir),y abl abl,x (abs) l(abs) stk sr (sr),y blk abs,b abs,x abs,y dir,b,r abs,b,r ( abs,x ) 10 98 76 5 2 30 op n op op op op op op op n op n op op op op op n n n n op n n op op n n n n op n n n n abs ipl v m x d i c z 41 n 4 0c 9 97 3 533 544 7 3 42 4 74 74 75 85 9 97 9f 3 5 3 5 processor status register 22 6 3 83 3 2 8 ? ? ? ? ?? ? ? ? ? ? ? ? ? ?? ? ? 1 ?? ? ? ? ? ?1 ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? specified flag becomes 1. ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z ? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? ? n ?? ? ? ? z ? ? ? n ?? ? ? ? z ? ? ? ? ? ?? ? ? ? ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z 12 11 13 42 9d 42 99 5 9d 99 8f 9f 5 7 2 3 93 42 83 42 10 ? ? ? ? ? ? ?? ? ? ? ?? ##n#### # # ## # rel ##### # # 1 93 42 42 8f 8d 42 8d 8c 8e 10 87 42 87 appendix 6. machine instructions
appendix 7733 group users manual 21C56 the number of cycles shown in the table is described in the case of the fastest mode for each instruction. the number of cycles shown in the table is calculated for dpr l =0. the number of cycles in the addressing mode concerning the dpr when dpr l 1 0 must be incremented by 1. the number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer, or according to whether the memory read/write address is odd or even. it also differs when the external region memory is accessed by byte=h. notes 1. the operation code at the upper row is used for accumulator a, and the operation at the lower row is used for accumulator b. 2. when setting flag m=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 3. the number of cycles increments by 2 when branching. 4. the operation code on the upper row is used for branching in the range of C128 to +127, and the operation code on the lower row is used for branching in the range of C32768 to +32767. 5. when handling 16-bit data with flag m=0, the byte in the table is incremented by 1. 6. the number of cycles corresponding to the register to be pushed are added. the number of cycles when no pushing is done is 12. i 1 indicates the number of registers among a, b, x, y, dpr, and ps to be saved, while i 2 indicates the number of registers among dt and pg to be saved. 7. the number of cycles corresponding to the register to be pulled are added. the number of cycles when no pulling is done is 14. i 1 indicates the number of registers among a, b, x, y, dt, and ps to be restored, while i 2 =1 when dpr is to be restored. 8. the number of cycles is the case when the number of bytes to be transferred is even. when the number of bytes to be transferred is odd, the number is calculated as; 7 + (i/2) 5 7 + 4 note that, (i/2) shows the integer part when i is divided by 2. 9. the number of cycles is the case when the number of bytes to be transferred is even. when the number of bytes to be transferred is odd, the number is calculated as; 9 + (i/2) 5 7 + 5 note that, (i/2) shows the integer part when i is divided by 2. 10. the number of cycles is the case in the 16-bit ? 8-bit operation. the number of cycles is incremented by 16 for 32-bit ? 16- bit operation. 11. the number of cycles is the case in the 8-bit 5 8-bit operation. the number of cycles is incremented by 8 for 16-bit 5 16- bit operation. 12. when setting flag x=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 13. when flag m is 0, the byte in the table is incremented by 1. b 3 a 3 x 3 y 3 dpr 4 dt 3 ps 3 a 2 b 2 x 2 y 2 dpr 2 dt 1 pg 1 ps 2 type of register number of cycles type of register number of cycles appendix 6. machine instructions
appendix 7733 group users manual 21C57 symbols in machine instructions table description symbol description symbol imp imm a dir dir, b dir, x dir, y (dir) (dir,x) (dir), y l (dir) l (dir),y abs abs, b abs, x abs, y abl abl, x (abs) l (abs) (abs, x) stk rel dir, b, rel abs, b, rel sr (sr), y blk c z i d x m v n ipl implied addressing mode immediate addressing mode accumulator addressing mode direct addressing mode direct bit addressing mode direct indexed x addressing mode direct indexed y addressing mode direct indirect addressing mode direct indexed x indirect addressing mode direct indirect indexed y addressing mode direct indirect long addressing mode direct indirect long indexed y addressing mode absolute addressing mode absolute bit addressing mode absolute indexed x addressing mode absolute indexed y addressing mode absolute long addressing mode absolute long indexed x addressing mode absolute indirect addressing mode absolute indirect long addressing mode absolute indexed x indirect addressing mode stack addressing mode relative addressing mode direct bit relative addressing mode absolute bit relative addressing mode stack pointer relative addressing mode stack pointer relative indirect indexed y addressing mode block transfer addressing mode carry flag zero flag interrupt disable flag decimal operation mode flag index register length selection flag data length selection flag overflow flag negative flag processor interrupt priority level addition subtraction multiplication division logical and logical or C ? a cc a cch a ccl a a h a l b b h b l x x h x l y y h y l s pc pc h pc l pg dt dpr dpr h dpr l ps ps h ps l ps b m(s) mb ad g ad h ad l op n # i i 1 , i 2 exclusive or negation movement to the arrow direction accumulator accumulators upper 8 bits accumulators lower 8 bits accumulator a accumulator as upper 8 bits accumulator as lower 8 bits accumulator b accumulator bs upper 8 bits accumulator bs lower 8 bits index register x index register xs upper 8 bits index register xs lower 8 bits index register y index register ys upper 8 bits index register ys lower 8 bits stack pointer program counter program counters upper 8 bits program counters lower 8 bits program bank register data bank register direct page register direct page registers upper 8 bits direct page registers lower 8 bits processor status register processor status registers upper 8 bits processor status registers lower 8 bits processor status registers b-th bit contents of memory at address indicated by stack pointer b-th memory location value of 24-bit addresss upper 8-bit (a 23 Ca 16 ) value of 24-bit addresss middle 8-bit (a 15 Ca 8 ) value of 24-bit addresss lower 8-bit (a 7 Ca 0 ) operation code number of cycle number of byte number of transfer byte or rotation number of registers pushed or pulled + C ] / appendix 6. machine instructions
7733 group user s manual 21-58 appendix appendix 7. examples of handling unused pins the following are examples of handling unused pins. these are, however, just examples. in actual use, make the necessary adaptations and properly evaluate performance according to the user s application. 1. in single-chip mode table 1 examples of handling unused pins in single-chip mode handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins open aft er they are set to the output mode ( note 1 ). leave this pin open. connect this pin to pin vcc. connect these pins to pin vss. pins p0 C p8 __ e x out ( note 2 ) avcc avss, v ref , byte notes 1: when leaving these pins open after they are set to the outpu t mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. for unused pins, use the shortest possible wiring (within 20 mm from the microcomputer s pins). 2: this is applied when an external clock is input to pin x in . appendix 7. examples of handling unused pins p0 C p8 avss v ref byte m37733mhbxxxfp vss avcc e x out left open n when setting ports to input mode v cc p0 C p8 avss v ref byte m37733mhbxxxfp vss avcc e x out left open n when setting ports to output mode left open vcc fig. 9 examples of handling unused pins in single-chip mode
7733 group user s manual 21-59 appendix 2. in memory expansion mode table 2 examples of handling unused pins in memory expansion mode pins p4 2 C p4 7 , p5 C p8 ____ bhe ( note 3 ) ale ( note 4 ) _____ hlda x out ( note 6 ) _____ ____ hold , rdy avcc avss, v ref handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins open aft er they are set to the output mode ( notes 1, 2, and 7 ). leave this pin open. ( note 5 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be en hanced when the contents of the above ports direction registers are set periodically. this is bec ause these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputer s pins). 3: this is applied when h level is input to pin byte. 4: this is applied when h level is input to pin byte and the accessible area has a capacity of 64 kbytes. 5: when vss level is applied to pin cnvss, note the following: this pin functions as an input port from reset until the processor mode is switched to the memory exp ansion mode by software. therefore, a voltage level of this pin is undefined and the power sourc e current may increase while this pin functions as an input port. 6: this is applied when an external clock is input to pin x in . 7: set pin p4 2 / f 1 as pin p4 2 . (clock f 1 output is disabled.) and then, for this pin, do the same handling as that for pins p4 3 to p4 7 and p5 to p8. fig. 10 examples of handling unused pins in memory expansion mode p4 2 C p4 7 , p5 C p8 avss v ref hold rdy left open m37733mhbxxxfp hlda vcc vss avcc x out n when setting ports to input mode left open p4 2 C p4 7 , p5 C p8 avs s v ref left open vss avcc x out n when setting ports to output mode left open left open vcc m37733mhbxxxfp bhe ale hold rdy bhe ale hlda appendix 7. examples of handling unused pins
7733 group user s manual 21-60 appendix 3. in microprocessor mode table 3 examples of handling unused pins in microprocessor m ode handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins open aft er they are set to the output mode ( notes 1 and 2 ). leave this pin open. ( note 5 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputer s pins). 3: this is applied when h level is input to pin byte. 4: this is applied when h level is input to pin byte and the accessible area has a capacity of 64 kbytes. 5: when vss level is applied to pin cnvss, note the following: this pin functions as an input port from reset until the processor mode is switched to the microproce ssor mode by software. therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: this is applied when an external clock is input to pin x in . pins p4 3 C p4 7 , p5 C p8 ____ bhe ( note 3 ) ale ( note 4 ) _____ hlda , f 1 x out ( note 6 ) _____ ____ hold , rdy avcc avss, v ref fig. 11 examples of handling unused pins in microprocessor m ode p4 3 C p4 7 , p5 C p8 avss v ref hold rdy left open m37733mhbxxxfp hlda vcc vss avcc x out n when setting ports to input mode left open p4 3 C p4 7 , p5 C p8 avs s v ref left open vss avcc x out n when setting ports to output mode left open left open vcc m37733mhbxxxfp bhe ale hold rdy bhe ale hlda f 1 f 1 appendix 7. examples of handling unused pins
7733 group user s manual 21-61 appendix appendix 8. countermeasure examples against noise general countermeasure examples against noise are described below. although the effect of these countermeasures depends on each system, refer to the followi ng when a noise-related problem occurs. 1. shortest wiring length the wiring on a printed circuit board may function as an ant enna which feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less p ossibility of noise insertion into the microcomputer. ______ (1) wiring for pin reset ______ make the length of wiring connected to pin reset as short as possible. in particular, connect a ______ capacitor between pin reset and pin vss with the shortest possible wiring (within 20 mm ). reason ______ if noise is input to pin reset, the microcomputer restarts operation before the internal state of the microcomputer is completely initialized. this may cause a program runaway. ______ fig. 12 wiring for pin reset reset reset circuit noise vss vss vss m37733mhbxxxfp not acceptable reset circuit reset v ss m37733mhbxxxfp acceptable appendix 8. countermeasure examples against noise
7733 group user s manual 21-62 appendix (2) wiring for clock i/o pins l make the length of wiring connected to clock i/o pins as short as possible. l make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator and pin vss of the microcomputer, as short as possible (within 20 mm). l separate the vss pattern only for oscillation from all other vss patterns. (refer to figure 21. ) reason the microcomputer s operation synchronizes with a clock generated by the oscillation circuit. if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a malfunction or a program runaway. also, if the noise causes a potential difference between the vss level of the microcomputer and the vss level of an oscillator, the correct clock will not be input in the microcomputer. (3) wiring for pin cnvss connect pin cnvss to pin vss with the shortest possible wiring. reason the processor mode of the microcomputer is influenced by a potential at pin cnvss when pin cnv ss and pin v ss are connected. if the noise causes a potential difference between the two pins, the processor mode may become unstable. this may cause a malfunction or a program runaway. fig. 13 wiring for clock i/o pins fig. 14 wiring for pin cnvss noise cnvss vss cnvss vss not acceptable acceptable m37733mhbxxxfp m37733mhbxxxfp noise x in x out vss x in x out vss not acceptable acceptable m37733mhbxxxfp m37733mhbxxxfp appendix 8. countermeasure examples against noise
7733 group user s manual 21-63 appendix (4) wiring to pin cnvss [in single-chip and memory expansion modes] l connect pin cnvss to pin vss of the microcomputer with the s hortest possible wiring. l if the above countermeasure cannot be taken, insert an appro ximate 5 k w resistor between pins cnvss and vss and, again, make the distance between the resi stor and pin cnvss as short as possible. [in microprocessor mode] l connect pin cnvss to pin vcc with the shortest possible wiri ng. reason pin cnvss is connected to the internal rom in the low-impeda nce state. (noise is easily to be fed to the pin in this condition.) if noise enters pin cnvss, incorrect instruction codes or da ta are fetched from the built-in prom. this may cause a program runaway. fig. 15 built-in prom version: wiring for pin cnvss microprocessor mode ?? cnv ss v cc shortest possible wiring approx. 5 k w pin cnvss is connected to pin vss with the shortest possible wiring. cnv ss v ss single-chip and memory expansion modes m37733ehbxxxfp h the above countermeasure is not necessary for pin byte. m37733ehbxxxfp pin cnvss is connected to pin vcc with the shortest possible wiring. shortest possible wiring appendix 8. countermeasure examples against noise
7733 group user s manual 21-64 appendix 2. connection of bypass capacitor between vss line and vcc l ine connect an approximate 0.1 m f bypass capacitor as follows: l connect a bypass capacitor between pin vss and pin vcc, at e qual lengths. l the wiring connecting the bypass capacitor between pin vss a nd pin vcc should be as short as possible. l use thicker wiring for the vss and vcc lines than for the ot her signal lines. bypass capacitor vcc vss m37733mhbxxxfp wiring pattern wiring pattern fig. 16 bypass capacitor connection appendix 8. countermeasure examples against noise
7733 group users manual 21-65 appendix appendix 8. countermeasure examples against noise 3. wiring for analog input pins, analog power source pins, etc. (1) processing analog input pins l connect a resistor to the analog signal line, which is connected to an analog input pin, in series. additionally, connect the resistor to the microcomputer as close as possible. l connect a capacitor between pin avss and the analog input pin, as close to pin avss as possible. reason a signal which is input to the analog input pin is usually an output signal from a sensor. the sensor, which detects changes in status, is installed far from the printed circuit board. therefore, this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer. if a capacitor between an analog input pin and pin avss is grounded far away from pin avss, noise on the gnd line may enter the microcomputer through the capacitor. fig. 17 countermeasure example against noise for analog input pin using thermistor an i avss thermistor noise m37733mhbxxxfp ri ci reference values @ ri: approximate 100 w to 1000 w ci: approximate 100 pf to 1000 pf notes 1: design an external circuit for pin ani so that charge/discharge is available within 1 cycle of ad . 2: this resistor and the thermistor are used to divide resistance. (note 2 j not acceptable acceptable acceptable
7733 group user s manual 21-66 appendix (2) processing for analog power source pins, etc. l use independent power sources for pins vcc, avcc and v ref . l insert capacitors between pins avcc and avss, and between pi ns v ref and avss, respectively. reasons: prevents noise from affecting the a-d converter on the vcc line. avcc avss m37733mhbxxxfp reference values c1 0.47 f c2 0.47 f note : connect capacitors using the thickest, shortest wiring possible. v ref an i c1 c2 (sensor, etc.) fig. 18 processing for analog power source pins, etc. appendix 8. countermeasure examples against noise
7733 group user s manual 21-67 appendix 4. oscillator protection the oscillator, which generates the basic clock for the microcomputer operations, must be protected from the affect of other signals. (1) distance oscillator from signal lines with large current flows l install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. reason the microcomputer is used in systems which contain signal lines for controlling motors, leds, thermal heads, etc. noise occurs due to mutual inductance when a large current flows through the signal lines. (2) distance oscillator from signal lines with frequent potential level changes l install an oscillator and a connecting pattern away from signal lines in which potential levels change frequently. l do not cross these signal lines over clock- related or noise-sensitive signal lines. reason signal lines with frequently changing potential levels may affect other signal lines at the rising or falling edge. in particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. fig. 19 wiring for signal lines with large current flows fig. 20 wiring for signal lines with frequent potential level changes x in x out vss m m37733mhbxxxfp mutual inductance large current gnd x in x out vss h do not cross. h i/o pin for signal with frequently changing potential levels. m37733mhbxxxfp appendix 8. countermeasure examples against noise
7733 group user s manual 21-68 appendix (3) oscillator protection using vss pattern print a vss pattern on the bottom (soldering side) of a doub le-sided printed circuit board, under the oscillator mount position. connect the vss pattern to pin vss of the microcomputer with the shortest possible wiring, separating it from other vss patterns. fig. 21 vss pattern underneath mounted oscillator x in x out vss an example of vss pattern on the underside of an oscillator mounted pattern example of an oscillator unit separate vss lines for oscillation and supply. m37733mhbxxxfp appendix 8. countermeasure examples against noise
7733 group user s manual 21-69 appendix 5. setup for i/o ports setup for i/o ports is follows: l connect a resistor of 100 w or more to an i/o port in series. l read the data of an input port several times to confirm that input levels are equal. l periodically rewrite data to the output port s pi register, as the data may reverse due to noise. l rewrite data to port pi direction registers periodically. noise direction register port latch data bus port fig. 22 setup for i/o ports appendix 8. countermeasure examples against noise
7733 group users manual 21-70 appendix 6. reinforcement of the power source line l for the vss and vcc lines, use thicker wiring than that of other signal lines. l when using a multilayer printed circuit board, the vss pattern and the vcc pattern must each be one of the middle layers. l the following is necessary for double-sided printed circuit boards: ? on one side, the microcomputer is installed at the center, and the vss line is looped or meshed around it. the vacant area is filled with the vss line. ? on the opposite side, the vcc line is wired the same as the vss line. ? the power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputers power source lines with the shortest possible wiring. reasons with external devices connected to the microcomputer, the levels of many of the signal lines (total external address buses: 24 bits) may change simultaneously, causing noise on the power source line. appendix 8. countermeasure examples against noise
7733 group users manual 21-71 appendix appendix 9. q & a information which may be helpful in fully utilizing the 7733 group is provided in q & a format. in q & a, as a rule, one question and its answer are summarized within one page. the upper box on each page is a question, and a box below the question is its answer. (if a question or an answer extends to two or more pages, there is a page number at the lower right corner.) at the upper right corner of each page, the main function related to the contents of description in that page is listed. appendix 9. q & a
7733 group user s manual 21-72 appendix interrupt q (1/2) if an interrupt request (b) occurs while an interrupt routin e (a) is executed, is it true that the main routine is not executed at all from when the execution of th e interrupt routine (a) is completed until the execution of the intack sequence for the next interrupt (b) starts? conditions: l i = 0 by executing the rti instruction l interrupt priority level of interrupt (b) is higher than ip l of main routine. l interrupt priority level detection time = 2 cycles of f a an interrupt request is sampled by detecting a sampling puls e which is generated synchronously with the cpu s op-code fetch cycle. ( 1 ) if the next interrupt request (b) occurs before sampling pul se of the rti instruction is generated, sampling for this interrupt request is completed while the rti instruction is executed. therefore, the intack sequence for (b) is executed without e xecuting the main routine. (even one instruction is not executed.) i nt er r upt r out i ne ( a) main routine intack sequence ( b) s equenc e of ex ec ut i on ? rti instruction intack sequence for (b) interrupt request (b) interrupt routine (a) sampling pulse rti instruction appendix 9. q & a
7733 group users manual 21-73 appendix interrupt a ( 2 ) if the next interrupt request (b) occurs immediately after s ampling pulse is generated, this interrupt request is sampled when sampling pulse for the next instruction is generated. there- fore, one instruction in the main routine is executed, and t hen the intack sequence for (b) is executed. (2/2) main routine interrupt request (b) sampling pulse intack sequence for (b) one instruction is executed. interrupt routine (a) rti instruction appendix 9. q & a
7733 group users manual 21-74 appendix interrupt suppose that there is a routine where a certain interrupt re quest should not be accepted. (the other interrupt requests are acceptable.) although when the interrupt priority level selection bits fo r the above interrupt are set to 000 2 , in other words, when this interrupt is set to be disabled, this interrupt request is actually accepted immediately after the change of the priority level. why did this occur and what should i do about it? interrupt request is accepted in this interval : clb #07h, xxxic ; the interrupt priority level selection bits are set to 000 2 ; or the interrupt request bit is set to 0. lda a,data ; the first instruction of a routine where a certain interrupt request should not be accepted :; as for the change of the interrupt priority level, when the following are met, the microcomputer may pretend to accept an interrupt request immediately after thi s interrupt is set to be disabled: ? the next instruction (in the above example, it is the lda instruction) is already stored into a instruc- tion queue buffer for the biu. ? conditions for accepting the instruction which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed. when writing to the memory ? i/o, the cpu transfers an addre ss and data to the biu. and then, the cpu executes the next instruction in the instruction queue b uffer while the biu is writing the data into the actual address. interrupt priority level is determined a t the start of each instruction. in the above case, the cpu executes the next instruction before the biu completes the c hange of the interrupt priority level. therefore, when the interrupt priority level is detected synchronously with the execution of the next instruction, the interrupt priority level before the change is detected a nd its interrupt request is accepted. q a (1/2) previous instruction is executed. (instruction is prefetched.) cpu operation biu operation interrupt priority detection time sequence of execution interrupt priority level selection bits are set. change of interrupt priority levels is completed interrupt request is accepted. interrupt request is generated. clb instruction is executed. lda instruction is executed. appendix 9. q & a
7733 group users manual 21-75 appendix interrupt a to solve this problem, make sure that, by software, the exec ution of a routine where a certain interrupt request should not be accepted starts after the ch ange of the interrupt level is completed. the following lists a sample program. [ sample program ] after an instruction which writes value 000 2 to the interrupt priority level selection bits, fill the instruction queue buffer with several nop instructions and make the next instruction not to be ex- ecuted until the writing is completed. : clb #07h, xxxic ; the interrupt priority level selection bits are set to 000 2 . nop ; nop ; nop ; lda a,data ; the first instruction of a routine where a certain interru pt request should not be accepted (2/2) appendix 9. q & a
7733 group users manual 21-76 appendix interrupt q (1) if the edge sense or level sense is selected, an external interrupt request occurs when the level ____ of an input signal on the int i pin changes. this is independent of clock f 1 . at this time, if the edge sense is selected, the interrupt request bit is set to 1, also. (2) there are two methods: one is the method to use the external interrupts level sense; the other one is the method to use the timers event counter mode. method to use the external interrupts level sense as for hardware, input a logical sum of several interrupt signals (for example, a, b, and c) ____ to the int i pin and input each signal to the corresponding port. ____ as for software, check the ports input levels in an int i interrupt routine in order to detect a signal (one of signals a, b, and c) which is input. a (1) ____ at what timing of clock f 1 is an external interrupt (an input signal on the int i pin) detected? (2) ____ suppose that more than three external interrupt input pins ( int i ) are necessary, what should i do? method to use the timers event counter mode as for hardware, input an interrupt signal to the tai in or tbi in pin. as for software, set the timers operating mode to the event counter mode and set value 0000 16 to the timer. furthermore, select a valid edge. the timers interrupt request occurs when an interrupt signal (selected valid edge) is input. note : the same process can be realized by using the key input interrupt function, also. m37733mhbxxxfp port port port int i a b c appendix 9. q & a
7733 group users manual 21-77 appendix serial i/o (uart mode) q ____ if the cts function is selected in uart (clock asynchronous serial i/o ) mode, at what timing should ____ the cts inputs level be checked by the transmitter? a checked near the middle of the stop bit (if two stop bits ar e selected, the second stop bit). d 6 transmit data n: 1-bit length input level on cts i pin is checked near this timing. d 7 sp sp .............. .............. nn n n/2 n/2 d 6 transmit data input level on cts i pin is checked near this timing. d 7 sp .............. .............. nn n/2 n/2 appendix 9. q & a
7733 group users manual 21-78 appendix hold function ______ if l level is input to the hold pin, when is a bus actually opened? a q . . . . . . . interval while bus is open clock 1 hold hlda t pxz(hold-pz) : maximum of 50 ns _____ when interval 50 ns (max.) has passed since clock f 1 is risen immediately after the hlda pins output becomes l, a bus is opened. appendix 9. q & a
bytes 7733 group users manual 21-79 appendix processor mode a although when the processor mode bits are set in order to sw itch the processor mode, as described above, the mode is not switched until the write cycle for th e processor mode bits is completed. (the processor mode is actually switched simultaneously with the write cycles completion.) at this time, the program counter indicates the address which is next to the address (address xxxx 16 ) where the write instruction for the processor mode bits is s tored. also, access to the internal rom area is disabled. note that there is a possibility that less than four bytes of instructions are prefetched into instruction queue buffers. therefore, the address which resides in the external rom area and is accessed first after the mode is switched is one of addresse s xxxx 16 + 1 to xxxx 16 4. note also that instructions at addresses xxxx 16 1 to xxxx 16 3 in the internal rom area may be executed. to solve this problem, do the following processes by software. [process ] program a write instruction for the processor mode bits and the following instructions (at least three bytes) to the same addresses of the internal rom and externa l rom areas. (see below.) [process ] transfer a write instruction for the processor mode bits to an internal ram area and make the program branch to the address in order to execute the write instruct ion. and then, make the program branch to the program address in the external rom area. (contents of i nstruction queue buffers are initialized by a branch instruction.) ld m , b #00000010b , pm r no p no p no p ld m , b #00000010b , pm r no p no p no p xxxx 16 ex t er nal rom area i nt er nal rom ar ea xxxx 16 at l eas t t hr ee when the processor mode is switched, as described below, by setting the processor mode bits (bits 1 and 0 at address 5e 16 ) while a program is executed, is there any precaution on so ftware? single-chip mode ? microprocessor mode memory expansion mode microprocessor mode q appendix 9. q & a + + +
appendix 7733 group users manual 21-80 appendix 9. q & a use the sta and ldm instructions for setting the registers or the bits listed below. do not use read-modify-write instructions (for example, clb, seb, inc, dec, asl, lsr, rol, and ror ). uart0 baud rate register (address 31 16 ) uart1 baud rate register (address 39 16 ) uart2 baud rate register (address 65 16 ) uart0 transmission buffer register (addresses 33 16 , 32 16 ) uart1 transmission buffer register (addresses 3b 16 , 3a 16 ) uart2 transmission buffer register (addresses 67 16 , 66 16 ) timer a4 two-phase pulse signal processing selection bit (bit 7 at address 44 16 ) timer a3 two-phase pulse signal processing selection bit (bit 6 at address 44 16 ) timer a2 two-phase pulse signal processing selection bit (bit 5 at address 44 16 ) when writing data to the oscillation circuit control register 1 (address 6f 16 ), be sure to follow the procedure shown below. ? when initializing the clock prescaler write data 80 16 . ( ldm instruction) clock prescaler is reset. ? when writing to bits 0 to 2 write data 01010101 2 . ( ldm instruction) write data 00001 555 2 . ( ldm instruction) (note) bits 0 to 2 are set. note: in the case of the 7735 group, write data 0000 0 555 2 . a when writing data to the memory allocation control register (address 63 16 ), be sure to follow the procedure shown below. write data 01010101 2 . ( ldm instruction) write data 00000 555 2 . ( ldm instruction) bits 0 to 2 are set. sfr q is there any sfr where a certain write instruction can not be used? a next instruction next instruction
7733 group users manual 21-81 appendix debug q is there any precaution when debugging? a some functions of the 7733 group cannot be evaluated by a debugger. for the operations listed below, use the built-in prom version to make full evaluation. when debugging, be sure to read the users manual supplied with the debugger. <> operation when the signal output disable selection bit (bit 6 at address 6c 16 ) = 1 operation when the stand-by state selection bit (bit 0 at address 6d 16 ) = 1 a operations for reading from and writing to addresses 02 16 to 09 16 in the memory expansion or microprocessor mode appendix 9. q & a
appendix 7733 group users manual 21-82 appendix 9. q & a q questions about the memory allocation selection function are described below: for what purpose is this function used? is there any precaution on use of this function? memory this function is used in order to secure an external memory area to bank 0 16 in the memory expansion mode. if there is an external device which is frequently accessed, this devices memory allocation in bank 0 16 is effective for accessing this device, as well as internal ram and sfr, with using dpr and dt efficiently. in the m37733mhbxxxfp, all of bank 0 16 is specified as an area for internal resources. therefore, this function is used to secure an external memory area in bank 0 16 . note that the memory allocation selection bits are valid in the single-chip mode, also. in the single- chip mode, the memory allocation selection function is valid only for reduction of usable rom area. therefore, in the single-chip mode, we recommend to set these bits to 000 2 (the state immedi- ately after reset) and not to change them. note the following: ? when changing the memory allocation selection bits, follow the procedure in figure 2.4.1. ? when changing the memory allocation selection bits, make sure that the change is done within an area which is in the internal rom area both of after and before the change, for example addresses 00c000 16 to 00ffff 16 . ? we recommend to set the memory allocation selection bits only when a processor mode is set after reset and not to change them after this setting. ? when programming to the eprom and one time prom versions, program to addresses listed in table 19.1.3. ? as for debugging for an area in bank 0 16 or 1 16 which is specified as an external area, some considerations may be necessary. for details concerning the development support tools, refer to the respective operation manuals. a
part 2 part 2 7735 group chapter 1 overview chapter 2 central processing unit (cpu) chapter 3 programmable i/o ports chapter 4 interrupts chapter 5 key input interrupt function chapter 6 timer a chapter 7 timer b chapter 8 serial i/o chapter 9 a-d converter chapter 10 watchdog timer chapter 11 stop and wait modes chapter 12 connecting external devices chapter 13 reset chapter 14 clock generating circuit chapter 15 electrical characteristics chapter 16 standard characteristics chapter 17 applications chapter 18 low voltage version chapter 19 built-in prom version chapter 20 external rom version appendix
7735 group users manual 2 part 2 7735 group the differences between the 7735 group and the 7733 group are mainly described below. for the 7733 group, refer to part 1. 7733 group. the 7735 group differs from the 7733 group in the following: ? external bus mode in the memory expansion mode and the microprocessor mode ? external memory area (the 7735 group has the maximum of 1-mbyte external memory area.) ? setting conditions for bit 3 of the oscillation circuit control register 1 (in the 7735 group, this bit must be 0. note that, in the one time prom version and the eprom version, this bit is automatically set to 1 after reset. therefore, be sure to clear this bit to 0.) __ ____ ? functions of pin e / rde
chapter 1 chapter 1 overview 1.1 performance overview 1.2 pin configuration 1.3 pin description 1.4 block diagram
over view 1C2 7735 group users manual concerning chapter 1. overview, the 7735 group differs fro m the 7733 group in the following sections. therefore, only the differences are described in this chapte r: ? 1.1 performance overview ? 1.2 pin configuration ? 1.3 pin description the following section of the 7735 group is the same as that of the 7733 group. therefore, for this section, refer to part 1: ? 1.4 block diagram (page 1-11 in part 1) 1.1 performance overview concerning section 1.1 performance overview, the 7735 grou p differs from the 7733 group in the following: ? description of the memory expansion in table 1.1.1 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 1.1 performance overview (page 1-3 in part 1) table 1.1.1 m37735mhbxxxfps performance overview 1.1 performance overview performance possible (maximum of 1 mbytes) items memory expansion
over view 1C3 7735 group users manual 1.2 pin configuration figure 1.2.1 shows the m37735mhbxxxfp pin configuration. note: for the low voltage version, refer to chapter 18. low voltage version. fig. 1.2.1 m37735mhbxxxfp pin configuration (top view) 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out p4 0 /hold byte cnv ss p7 4 /an 4 /r x d 2 p7 5 /an 5 /ad trg /t x d 2 p7 6 /an 6 /x cout p7 7 /an 7 /x cin v ss av ss v ref av cc v cc p8 0 /cts 0 /rts 0 /clks 1 p8 1 /clk 0 p8 2 /r x d 0 /clks 0 p8 3 /t x d 0 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 /cs 0 p0 1 /cs 1 p0 2 /cs 2 p0 3 /cs 3 p0 4 /cs 4 p0 5 /rsmp p0 6 /a 16 p0 7 /a 17 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 1 4 3 2 5 6 7 8 9 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 p1 7 /a 15 /d 15 p2 0 /a 0 /d 0 p2 1 /a 1 /d 1 p2 2 /a 2 /d 2 p2 3 /a 3 /d 3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 m37735mhbxxxfp 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p4 1 /rdy p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 p7 1 /an 1 p7 2 /an 2 /cts 2 p7 3 /an 3 /clk 2 reset x in x out e/rde v ss p3 3 /hlda p3 2 /ale p3 1 /weh p3 0 /wel p2 7 /a 7 /d 7 p2 6 /a 6 /d 6 p2 5 /a 5 /d 5 p2 4 /a 4 /d 4 outline 80p6n-a 1.2 pin configuration
overview 1C4 7735 group users manual 1.3 pin description concerning section 1.3 pin description, the 7735 group differs from the 7733 group in the following: ___ ? description of pin e in table 1.3.1 ? description of pins p0 0 Cp0 7 , p2 0 Cp2 7 and p3 0 Cp3 3 in table 1.3.2 ? 1.3.1 examples of handling unused pins the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 1.3 pin description (page 1-5 in part 1) table 1.3.1 pin description (1) functions [single-chip mode] __ this pin outputs internal enable signal e . when e s level is l, the microcomputer reads data and instruction codes or writes data. also, output of internal enable _ signal e can be stopped by software. [memory expansion mode] [microprocessor mode] ________ this pin outputs read enable signal rde . this signals level is l in the data read period of the read cycle. pin _ e name internal enable output input/output output 1.3 pin description
overview 1C5 7735 group users manual input/output i/o output i/o i/o output pin p0 0 Cp0 7 _______ _______ cs 0 C cs 4 , _____ rsmp , a 16 , a 17 p2 0 Cp2 7 a 0 /d 0 C a 7 /d 7 p3 0 Cp3 3 ________ wel , ________ weh , ale, _____ hlda table 1.3.2 pin description (2) functions [single-chip mode] same as the 7733 group. [memory expansion mode] [microprocessor mode] _______ _______ ____________ these pins respectively output signals cs 0 C cs 4 , rsmp , and addresss high-order 2 bits (a 16 and a 17 ). _______ _______ l signal cs 0 C cs 4 these signals are the chip select signals. when the microcomputer accesses a certain area, the corresponding pin outputs l level. (refer to table 2.5.3. ) ____________ l signal rsmp this signal is the ready sampling signal and is used ________ to generate signal rdy for accessing external memory area. [single-chip mode] same as the 7733 group. [memory expansion mode] [microprocessor mode] input/output of data (d 0 Cd 7 ) and output of addresss low-order 8 bits (a 0 Ca 7 ) are performed with the time sharing method. [single-chip mode] same as the 7733 group. [memory expansion mode] [microprocessor mode] ________ _________ these pins respectively output signals wel , weh , ale, _____ and hlda . ________ _________ l signal wel , weh ____ signal wel is the write enable low signal. ____ signal weh is the write enable high signal. these signals levels are l in the data write period of the write cycle. the operations of these signals depend on the level of pin byte. (refer to table 12.1.1. ) l signal ale this signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. _____ l signal hlda this signal informs the external whether the microcomputer enters the hold state or not. __________ in hold state, pin hlda outputs l level. name i/o port p0 i/o port p2 i/o port p3 1.3 pin description
overview 1C6 7735 group users manual 1.3.1 examples of handling unused pins the following are examples of handling unused pins. these are, however, just examples. in actual use, make the necessary adaptations and properly evaluate performance according to the users system. (1) in single-chip mode table 1.3.4 examples of handling unused pins in single-chip mode notes 1: when leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until the they are switched to the output mode by software. therefore, voltage levels of these pins are undefined and the power source current may increase while these ports function as input ports. software reliability can be enhanced when the contents of the above ports direction registers are set periodically. this is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. for unused pins, use the shortest possible wiring (within 20 mm from the microcomputers pins). 2: this is applied when an external clock is input to pin x in . pins p0Cp8 _ e x out ( note 2 ) avcc avss, v ref , byte handling example connect these pins to pin vcc or vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode ( note 1 ). leave this pin open. connect this pin to pin vcc. connect these pins to pin vss. fig. 1.3.1 examples of handling unused pins in single-chip mode p0?8 avss v ref byte m37735mhbxxxfp vss avcc e x out left open when setting ports to input mode vcc p0?8 avss v ref byte m37735mhbxxxfp vss avcc e x out left open when setting ports to output mode left open vcc 1.3 pin description
overview 1C7 7735 group users manual (2) in memory expansion mode table 1.3.5 examples of handling unused pins in memory expansion mode pins p4 2 Cp4 7 , p5Cp8 ( note 5 ) _________ ________ ________ weh , wel , rde , _____ _______ _______ __________ hlda, cs 0 C cs 4 , rsmp x out ( note 4 ) _____ ____ hold , rdy avcc avss, v ref handling example connect these pins to pin vcc or vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode ( notes 1 and 2 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. notes 1: when leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. software reliability can be enhanced when the contents of the above ports direction registers are set periodically. this is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 20 mm from the microcomputers pins). 3: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 4: this is applied when an external clock is input to pin x in . 5: set pin p4 2 / f 1 as pin p4 2 . (clock f 1 output is disabled.) and then, for this pin, do the same handling as that for pins p4 3 to p4 7 and p5 to p8. fig. 1.3.2 examples of handling unused pins in memory expansion mode p4 2 ?4 7 , p5?8 hold rdy m37735mhbxxxfp vcc vss avcc x out cs 0 cs 4 p4 2 ?4 7 , p5?8 hold rdy vss avcc x out cs 0 cs 4 vcc m37735mhbxxxfp when setting ports to input mode when setting ports to output mode left open left open left open left open left open avss v ref avss v ref weh wel rde hlda rsmp weh wel rde hlda rsmp 1.3 pin description
over view 1C8 7735 group users manual (3) in microprocessor mode table 1.3.6 examples of handling unused pins in microprocess or mode handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. pins p4 3 Cp4 7 , p5Cp8 _________ ________ ________ weh , wel , rde _____ _______ _______ ___________ hlda , f 1 , cs 0 Ccs 4 , rsmp x out ( note 4 ) _____ ____ hold , rdy av cc av ss , v ref notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputers pins). 3: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the microproce ssor mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. 4: this is applied when an external clock is input to pin x in . fig. 1.3.3 examples of handling unused pins in microprocesso r mode p4 3 Cp4 7 , p5Cp8 1 rsmp hold rdy m37735mhbxxxfp weh wel rde hlda vcc vss avcc x out cs 0 C cs 4 p4 3 Cp4 7 , p5Cp8 1 rsmp hold rdy vss avcc x out cs 0 C cs 4 vcc m37735mhbxxxfp when setting ports to input mode when setting ports to output mode left open left open left open left open left open avss v ref avss v ref weh wel rde hlda 1.3 pin description
chapter 2 chapter 2 central processing unit (cpu) 2.1 central processing unit 2.2 bus interface unit 2.3 accessible area 2.4 memory allocation 2.5 processor modes
central processing unit (cpu) 7735 group users manual 2C2 concerning chapter 2. central processing unit (cpu), the 7735 group differs from the 7733 group in the following sections. therefore, only the differences are described in this chapter: ? 2.2 bus interface unit ? 2.3 accessible area ? 2.5 processor modes the following sections of the 7735 group are the same as those of the 7733 group. therefore, for these section, refer to part 1: ? 2.1 central processing unit (page 2C2 in part 1) ? 2.4 memory allocation (page 2C18 in part 1) 2.2 bus interface unit concerning section 2.2 bus interface unit, the 7735 group differs from the 7733 group in the following. ? external buses in figure 2.2.1 ? signal names in figure 2.2.3 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 2.2 bus interface unit (page 2C10 in part 1) 2.2 bus interface unit
central processing unit (cpu) 7735 group users manual 2C3 2.2 bus interface unit fig. 2.2.1 buses and bus interface unit (biu) m37735mhbxxxfp a 17 and a 16 a 15 / d 15 to a 8 / d 8 a 7 / d 7 to a 0 / d 0 internal bus d 15 to d 8 central processing unit (cpu) sfr : special function register notes 1: cpu bus, internal bus, and external bus are independent of each other. 2: for details about signals on the external buses, refer to chapter ?2. connecting external devices. internal bus a 17 to a 0 external devices internal control signals cpu bus internal bus internal bus d 7 to d 0 internal memory internal peripheral devices (sfr) external bus control signals bus interface unit (biu) bus conversion circuit
central processing unit (cpu) 7735 group users manual 2C4 2.2 bus interface unit fig. 2.2.3 basic operating waveforms of bus interface unit (biu) rde (a) rde (b) address internal address bus (a 0 to a 17 ) data (even address) internal data bus (d 0 to d 7 ) data (odd address) internal data bus (d 8 to d 15 ) address (odd address) address (even address) data (even address) data (odd address) invalid data invalid data internal address bus (a 0 to a 17 ) internal data bus (d 0 to d 7 ) internal data bus (d 8 to d 15 )
central processing unit (cpu) 7735 group users manual 2C5 2.3 accessible area concerning section 2.3 accessible area, the 7735 group dif fers from the 7733 group in the following: ? accessible area which is allocated to addresses 0 16 to 0fffff 16 (maximum of 1 mbytes) ? figure 2.3.1 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 2.3 accessible area (page 2C16 in part 1) 2.3 accessible area fig. 2.3.1 m37735mhbxxxfps accessible area 000000 16 000080 16 00ffff 16 010000 16 fe0000 16 ff0000 16 ffffff 16 001000 16 020000 16 000fff 16 00007f 16 01ffff 16 ?sfr : special function register notes 1: banks 10 16 to ff 16 cannot be accessed. 2: memory allocation of internal area in bank 0 16 depends on the microcomputers type and settings of the memory allocation selection b its. the above diagram shows the m37735mhbxxxfps accessible area immediately after reset. for the other microcomputers of the 7735 grou p, refer to appendix 1. memory allocation of 7735 group. for settings of the memory allocation selection bits, refer to section 2.4 memory allocation. sfr area internal ram area bank 0 16 internal rom area bank 1 16 bank ff 16 bank fe 16 represents the memory allocation of internal areas. indicates that nothing is allocated.
appendix 1. this applies when the contents of memory allocation selectio n bits (bits 2 to 0 at central processing unit (cpu) 7735 group user s manual 2 C 6 2.5 processor modes concerning section 2.5 processor modes, the 7735 group dif fers from that of the 7733 group in the following: ? fig. 2.5.1 memory map in each processor mode ? fig. 2.5.2 pin configuration in each processor mode (top view) ? table 2.5.1 relationship between processor modes and func tions of p0 to p4 _______ _______ ? 2.5.4 relationship between access addresses and chip sele ct signals ( cs 0 C cs 4 ) (this section is added in part 2.) the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 2.5 processor modes (page 2 C 24 in part 1) 2.5 processor modes fig. 2.5.1 memory map in each processor mode (m37735mhbxxxfp ) notes 1: represents external area. by accessing this area, an external device connected to the m37735mhbxxxfp can be accessed . 2: address 63 16 ) = 000 2 . 3: for the other microcomputers of the 7735 group, refer to sec tion memory allocation of 7735 group. 4: banks 10 16 to ff 16 cannot be accessed. 000000 16 01ffff 16 000080 16 020000 16 ffffff 16 000fff 16 001000 16 0fffff 16 100000 16 sfr area internal rom area single-chip mode internal ram area sfr area memory expansion mode sfr area microprocessor mode internal ram area internal ram area internal rom area ( note 4 ) ( note 4 )
central processing unit (cpu) 7735 group users manual 2C7 2.5 processor modes fig. 2.5.2 pin configuration in each processor mode (top vie w) : these pins functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. p2 4 p2 5 p2 6 p2 7 p3 0 p3 1 p3 2 p3 3 v ss e x out x in reset cnv ss byte p4 0 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 p0 1 p0 2 p0 3 p0 4 p0 5 p0 6 p0 7 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 0 p2 1 p2 2 p2 3 p4 1 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 14 3 25 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 6789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 43 42 41 m37735mhbxxxfp 22 23 24 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 ] 1 ] 1 ] 1 connect this pin to vss in the single-chip mode. a 4 /d 4 a 5 /d 5 a 6 /d 6 a 7 /d 7 wel weh ale hlda v ss rde x out x in reset cnv ss byte hold rdy a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 a 0 /d 0 a 1 /d 1 a 2 /d 2 a 3 /d 3 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 cs 0 cs 1 cs 2 cs 3 cs 4 rsmp a 16 a 17 a 8 /d 8 a 9 /d 9 14 3 2 56789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 43 42 41 m37735mhbxxxfp p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 ] 2 a 10 /d 10 ] 2 1 in the microprocessor mode : these pins functions in the single-chip mode differ from those in the memory expansion or microprocessor mode.
in the memory expansion mode, this pin functions as a progra mmable i/o port. furthermore, it can be switched to be a clo ck these signals are affected by the signal output disable sel ection bit (bit 6 at address 6c central processing unit (cpu) 7735 group users manual 2C8 2.5 processor modes table 2.5.1 relationship between processor modes and functio ns of p0 to p4 notes 1: when an internal area is accessed, signals cs 0 to cs 4 are not output. (the output level is fixed to h.) 2 : 16 ). (refer to chapter 12. connecting external devices. ) 3 : pin p4 2 can also function as a clock 1 output pin. (refer to chapter 12. connecting external devices. ) 4: 1 output pin when selected by software. in the microprocessor mode, this pin is affected by the signal output disable sele ction bit (bit 6 at address 6c 16 ). (refer to chapter 12. connecting external devices. ) d(even): data at even address p0 p1 p0 5 hlda p3 2 p3 3 a 8 to a 15 p3 p2 p4 a 16 , a 17 p0 6 and p0 7 a 8 to a 15 a 0 to a 7 a 0 to a 7 d ale hlda p3 1 p3 3 (h level output) rsmp p rdy p4 1 e / rde e rde ( note 2 ) p p p p p p0 0 to p0 4 cs 0 to cs 4 ( note 1 ) p3 0 wel ( note 2 ) p3 1 weh ( note 2 ) p3 0 wel ( note 2 ) p3 2 ale hold p4 0 p4 2 1 ( note 4 ) ( note 2 ) d(odd): data at odd address p4 3 to p4 7 pin name single-chip mode memory expansion and microprocessor modes processor mode n when external data bus is 16 bits wide (byte = l) n when external data bus is 8 bits wide (byte = h) n when external data bus is 16 bits wide (byte = l) n when external data bus is 8 bits wide (byte = h) p: functions as a programmable i/o port. p: functions as a programmable i/o port. p: functions as a programmable i/o port. p: functions as a programmable i/o port. p: functions as a programmable i/o port (note 3) . p: functions as a programmable i/o port. n when external data bus is 16 bits wide (byte = l) n when external data bus is 8 bits wide (byte = h) d(odd) d(even) d: data 3:
central processing unit (cpu) 7735 group users manual 2C9 _______ _______ 2.5.4 relationship between access addresses and chip select signals cs 0 to cs 4 _______ _______ table 2.5.3 lists the relationship between access addresses and chip select signals cs 0 to cs 4 . table 2.5.4 lists the relationship between the memory allocation selection bits and addresses for chip _______ _______ select signals cs 0 , cs 1 in the memory expansion mode. _______ _______ table 2.5.3 relationship between access addresses and chip select signals cs 0 to cs 4 2.5 processor modes chip select signal _______ cs 0 _______ cs 1 _______ cs 2 _______ cs 3 _______ cs 4 microprocessor mode 00 1000 16 to 00 7fff 16 00 8000 16 to 03 ffff 16 04 0000 16 to 07 ffff 16 08 0000 16 to 0b ffff 16 0c 0000 16 to 0f ffff 16 area the former half of bank 00 16 except for internal memory area ?the latter half of bank 00 16 except for internal memory area ?banks 01 16 to 03 16 banks 04 16 to 07 16 banks 08 16 to 0b 16 banks 0c 16 to 0f 16 memory expansion mode ( note ) 02 0000 16 ( note ) to 03 ffff 16 04 0000 16 to 07 ffff 16 08 0000 16 to 0b ffff 16 0c 0000 16 to 0f ffff 16 note: this applies when each of bits 1 and 0 of the memory allocation control register (address 63 16 ) = 0. for details, refer to table 2.5.4. table 2.5.4 relationship between memory allocation selection bits and addresses for chip select _______ _______ signals cs 0 , cs 1 in memory expansion mode access addresses _______ cs 1 020000 16 to 03ffff 16 020000 16 to 03ffff 16 020000 16 to 03ffff 16 010000 16 to 03ffff 16 b2 0 0 1 1 b1 0 0 1 1 b0 0 1 0 1 memory allocation selection bits ] memory allocation selection bits ] : bits 0 to 2 of the memory allocation control register (address 63 16 ) internal rom area 001000 16 to 01ffff 16 (124 kbytes) 002000 16 to 01ffff 16 (120 kbytes) 008000 16 to 01ffff 16 (96 kbytes) 008000 16 to 00ffff 16 (32 kbytes) ______ cs 0 001000 16 to 001fff 16 001000 16 to 007fff 16 001000 16 to 007fff 16 access addresses
central processing unit (cpu) 7735 group users manual 2C10 2.5 processor modes memo
chapter 3 chapter 3 programmable i/o ports 3.1 programmable i/o ports 3.2 port peripheral circuits 3.3 pull-up function 3.4 internal peripheral devices i/o functions (ports p4 2 and p5 to p8)
programmable i/o por ts 7735 group users manual 3C2 3.2 port peripheral circuits concerning chapter 3. programmable i/o ports, the 7735 gro up differs from the 7733 group in the following section. therefore, only the difference is describ ed in this chapter: ? 3.2 port peripheral circuits the following sections are the same as those of the 7733 gro up. therefore, for th e s e sections , refer to part 1: ? 3.1 programmable i/o ports (page 3-2 in part 1) ? 3.3 pull-up function (page 3-8 in part 1) ? 3.4 internal peripheral devices i/o functions (ports p4 2 and p5 to p8) (page 3-10 in part 1) 3.2 port peripheral circuits concerning section 3.2 port peripheral circuits, the 7735 group differs from the 7733 group in the follow- ing: _ ____ ? pin e / rde in figure 3.2.2 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 3.2 port peripheral circuits (page 3-6 in part 1) fig. 3.2.2 port peripheral circuits (2) ? e / rde hold acknowledge
chapter 4 chapter 4 interrupts 4.1 overview 4.2 interrupt sources 4.3 interrupt control 4.4 interrupt priority level 4.5 interrupt priority level detection circuit 4.6 interrupt priority level detection time 4.7 how interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) 4.8 return from interrupt routine 4.9 multiple interrupts ____ 4.10 external interrupts ( inti interrupt) 4.11 precautions for interrupts
7735 group users manual interrupts 4C2 interrupts of the 7735 group are the same as those of the 7733 group. therefore, for interrupts, refer to the corresponding sections in part 1: ? 4.1 overview (page 4-2 in part 1) ? 4.2 interrupt sources (page 4-4 in part 1) ? 4.3 interrupt control (page 4-6 in part 1) ? 4.4 interrupt priority level (page 4-10 in part 1) ? 4.5 interrupt priority level detection circuit (page 4-11 in part 1) ? 4.6 interrupt priority level detection time (page 4-13 in part 1) ? 4.7 how interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) (page 4-14 in part 1) ? 4.8 return from interrupt routine (page 4-17 in part 1) ? 4.9 multiple interrupts (page 4-17 in part 1) ____ ? 4.10 external interrupts ( int i interrupt) (page 4-19 in part 1) ? 4.11 precautions for interrupts (page 4-23 in part 1)
chapter 5 chapter 5 key input interrupt function 5.1 overview 5.2 block description 5.3 initial setting example for related registers
7735 group users manual 5-2 key input interrupt function the key input interrupt function of the 7735 group is the same as that of the 7733 group. therefore, the key input interrupt function, refer to the corresponding sections in part 1: ? 5.1 overview (page 5-2 in part 1) ? 5.2 block description (page 5-3 in part 1) ? 5.3 initial setting example for related registers (page 5-7 in part 1)
chapter 6 chapter 6 timer a 6.1 overview 6.2 block description 6.3 timer mode 6.4 event counter mode 6.5 one-shot pulse mode 6.6 pulse width modulation (pwm) mode
7735 group users manual 6-2 timer a timer a of the 7735 group is the same as that of the 7733 group. therefore, for timer a, refer to the corresponding sections in part 1: ? 6.1 overview (page 6-2 in part 1) ? 6.2 block description (page 6-3 in part 1) ? 6.3 timer mode (page 6-9 in part 1) ? 6.4 event counter mode (page 6-19 in part 1) ? 6.5 one-shot pulse mode (page 6-32 in part 1) ? 6.6 pulse width modulation (pwm) mode (page 6-41 in part 1)
chapter 7 chapter 7 timer b 7.1 overview 7.2 block description 7.3 timer mode 7.4 event counter mode 7.5 pulse period/pulse width measurement mode 7.6 clock timer
7735 group users manual 7-2 timer b timer b of the 7735 group is the same as that of the 7733 group. therefore, for timer b, refer to the corresponding sections in part 1: ? 7.1 overview (page 7-2 in part 1) ? 7.2 block description (page 7-3 in part 1) ? 7.3 timer mode (page 7-10 in part 1) ? 7.4 event counter mode (page 7-17 in part 1) ? 7.5 pulse period/pulse width measurement mode (page 7-25 in part 1) ? 7.6 clock timer (page 7-34 in part 1)
chapter 8 chapter 8 serial i/o 8.1 overview 8.2 block description 8.3 clock synchronous serial i/o mode 8.4 clock asynchronous serial i/o (uart) mode
serial i/o 7735 group users manual 8C2 the serial i/o of the 7735 group is the same as that of the 7733 group. therefore, for serial i/o, refer to the corresponding sections in part 1: ? 8.1 overview (page 8-2 in part 1) ? 8.2 block description (page 8-4 in part 1) ? 8.3 clock synchronous serial i/o mode (page 8-21 in part 1) ? 8.4 clock asynchronous serial i/o (uart) mode (page 8-44 in part 1)
chapter 9 chapter 9 a-d converter 9.1 overview 9.2 block description 9.3 a-d conversion method 9.4 absolute accuracy and differential non-linearity error 9.5 one-shot mode 9.6 repeat mode 9.7 single sweep mode 9.8 repeat sweep mode 9.9 precautions for a-d converter
a-d converter 7735 group users manual 9C2 the a-d converter of the 7735 group is the same as that of the 7733 group. therefore, for the a-d converter, refer to the corresponding sections in part 1: ? 9.1 overview (page 9-2 in part 1) ? 9.2 block description (page 9-3 in part 1) ? 9.3 a-d conversion method (page 9-11 in part 1) ? 9.4 absolute accuracy and differential non-linearity error (page 9-14 in part 1) ? 9.5 one-shot mode (page 9-17 in part 1) ? 9.6 repeat mode (page 9-20 in part 1) ? 9.7 single sweep mode (page 9-23 in part 1) ? 9.8 repeat sweep mode (page 9-27 in part 1) ? 9.9 precautions for a-d converter (page 9-31 in part 1)
chapter 10 chapter 10 watchdog timer 10.1 block description 10.2 operation description 10.3 precautions for watchdog timer
watchdog timer 7735 group users manual 10-2 10.2 operation description concerning chapter 10. watchdog timer, the 7735 group differs from the 7733 group in the following section. therefore, only the differences are described in this chapter: ? 10.2 operation description the following sections are the same as those of the 7733 group. therefore, for these sections, refer to part 1: ? 10.1 block description (page 10-2 in part 1) ? 10.3 precautions for watchdog timer (page 10-10 in part 1) 10.2 operation description concerning section 10.2 operation description, the 7735 group differs from the 7733 group in the following: ? figures 10.2.2 and 10.2.3 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 10.2 operation description (page 10-5 in part 1)
watchdog timer 7735 group users manual 10-3 fig. 10.2.2 structure of oscillation circuit control register 1 fig. 10.2.3 procedure for writing data to oscillation circuit control register 1 10.2 operation description in the m37735mhbxxxfp, set bit 3 of the oscillation circuit control register 1 to 0. write data ?1010101 2 .?( ldm instruction) ?when writing to bits 0 to 3 write data ?0000xxx 2 .?( ldm instruction) next instruction (b3 in figure 10.2.2) (b2 to b0 in figure 10.2.2) 2: because this bit is ??at reset, clear this bit to ??with the initial setting program after reset. 3: the case where data ?1010101 2 ?is written with the procedure shown below is not included. 4: for the 7733 group, refer to figure 14.3.3 in part 1. 5: represents that bits 3 to 7 are not used for the watchdog timer. a aaaaaaaaaaaaa a aaaaaaaaaaaaaaa bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to ??in the one time prom and eprom versions (notes 1 and 2) . must be fixed to ?? (note 3) . clock prescaler reset bit 0 0 0 0 undefined 0 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input fro m the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. a b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown below. by writing ??to this bit, clock prescaler is initialized. rw 1 (note 4) 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. must be fixed to ??in the mask rom and external rom versions (note 1) . (note 1) (note 1) (note 1) 0
watchdog timer 7735 group users manual 10-4 10.2 operation description memo
chapter 11 chapter 11 stop and wait modes 11.1 overview 11.2 clock generating circuit 11.3 stop mode 11.4 wait mode
stop and wait modes 7735 group users manual 11C2 11.2 clock generating circuit concerning chapter 11. stop and wait modes, the 7735 group differs from the 7733 group in the following sections. therefore, only the differences are described in this chapter: ? 11.2 clock generating circuit ? 11.3 stop mode ? 11.4 wait mode the following section of the 7735 group is the same as that of the 7733 group. therefore, for this section, refer to part 1: ? 11.1 overview (page 11-2 in part 1) 11.2 clock generating circuit concerning section 11.2 clock generating circuit, the 7735 group differs from the 7733 group in the following: ? figures 11.2.3 and 11.2.4 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 11.2 clock generating circuit (page 11-3 in part 1) in the m37735mhbxxxfp, be sure to set bit 3 of the oscillation circuit control register 1 to 0. fig. 11.2.3 structure of oscillation circuit control register 1 2: because this bit is ??at reset, clear this bit to ??with the initial setting program after reset. 3: the case where data ?1010101 2 ?is written with the procedure shown in figure 11.2.4. is not included. 4: for the 7733 group, refer to figure 11.2.3 in part 1. 5: represents that bits 3 to 7 are not used for the stop and wait modes. bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to ??in the one time prom and eprom versions (notes 1 and 2) . must be fixed to ?? (note 3) . clock prescaler reset bit 0 0 0 0 undefined 0 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input fro m the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown in figure 11.2.4. by writing ??to this bit, clock prescaler is initialized. rw 1 (note 4) 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. must be fixed to ??in the mask rom and external rom versions (note 1) . (note 1) (note 1) (note 1) 0
stop and wait modes 7735 group users manual 11C3 11.3 stop mode fig. 11.2.4 procedure for writing data to oscillation circuit control register 1 11.3 stop mode concerning section 11.3 stop mode, the 7735 group differs from the 7733 group in the following: ? table 11.3.2 and figure 11.3.1 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 11.3 stop mode (page 11-6 in part 1) write data ?1010101 2 .?( ldm instruction) ?when writing to bits 0 to 3 write data ?0001xxx 2 .?( ldm instruction) next instruction (b3 in figure 11.2.3) (b2 to b0 in figure 11.2.3)
stop and wait modes 7735 group users manual 11C4 table 11.3.2 pin state in stop mode state single-chip mode memory expansion microprocessor mode mode pins when the standby state selection bit * 1 = 0 when the standby state selection bit * 1 = 1 n when the signal output disable selection bit = 0, h level is output n when the signal output disable selection bit = 1, l level is output. n when the signal output disable selection bit = 0, h level is output. n when the signal output disable selection bit = 1, l level is output. same as in the micro- processor mode h level is output. __ e ____ rde, ____ wel, ____ weh, ____ ____ cs 0 C cs 4 , _____ rsmp, _____ hlda ale a 0 /d 0 Ca 15 /d 15 , a 16 , a 17 output levels can be set. (refer to section 11.3.1 output levels of external bus and bus control signals in stop mode. ) 11.3 stop mode l level is output. n when the clock f 1 output selection bit *2 = 1 f 1 : l level is output. n when the clock f 1 output selection bit = 0 p4 2 : retains the same state in which the stp instruction is executed. retains the same state in which the stp instruction is executed. n when the signal output disable selection bit *3 = 0 f 1 : l level is output. n when the signal output disable selection bit = 1 p4 2 : bit 2s value of the port p4 register is output (note) . p0 to p8 (not including p4 2 ) : retains the same state in which the stp instruction is executed. p4 3 to p4 7 , p5 to p8 :retains the same state in which the stp instruction is executed. ports p4 2 / f 1 standby state selection bit *1 : bit 0 at address 6d 16 (refer to figure 11.3.1. ) clock f 1 output selection bit *2 : bit 7 at address 5e 16 (refer to section 12.1 signals required for accessing external devices. ) signal output disable selection bit *3 : bit 6 at address 6c 16 (refer to section 12.1 signals required for accessing external devices. ) note: make sure to set bit 2 of the port p4 direction register to 1.
stop and w ait modes 7735 group users manual 11C5 fig. 11.3.1 output level setting example in stop mode (memor y expansion or microprocessor mode) 11.3 stop mode stp instruction is executed. note 2: this bits value also affects the pin state in the wait mod e. (refer to figure 11.4.1. ) setting of the output levels for the external bus, chip sele ct signals, and bus control signals (not including rde ) b7 b0 port p0 direction register (address 4 16 ) port p1 direction register (address 5 16 ) port p2 direction register (address 8 16 ) port p3 direction register (address 9 16 ) must be fixed to ff 16. 1 1 11111 1 b7 b0 set output level by the bit which corresponds to each pin. 0: l level output 1: h level output note 3: this bit's value also affects the following: ? output state of bus control signals and other s after the stop mode is terminated (refer to chapter 12. connecting external devices ) ? pin state in the wait mode. (refer to figure 11.4.1. ) furthermore, description of pin p4 2 / 1 is applied only in the microprocessor mode. setting of rde signals output level (setting of pin p4 2 / 1 s state) b7 b0 oscillation circuit control register 0 (address 6c 16 ) signal output disable selection bit ( note 3 ) 0: in the stop mode, pin e/rde outputs h level, and pin p4 2 / 1 outputs l level. 1: in the stop mode, pin e/rde outputs l level, and pin p4 2 / 1 outputs bit 2s value of port p4 register. port function control register (address 6d 16 ) standby state selection bit ( note 2 ) b7 b0 setting of the standby state selection bit to 1 01 b7 b0 port p4 direction register (address c 16 ) 1 b7 b0 port p4 register (address a 16 ) 0: l level output 1: h level output ? when setting the signal output disable selection bit to 1 in the microprocessor mode ? when setting the clock 1 output selection bit to 0 in the memory expansion mode ? when setting the signal output disable selection bit to 0 in the microprocessor mode ? when setting the clock 1 output selection bit to 1 in the memory expansion mode note 1: this is applied only in the microprocessor mode. in the memory expansion mode, it may be 0 or 1 because the i/o port function is selected. (note 1) port p0 register (address 2 16 ) port p1 register (address 3 16 ) port p2 register (address 6 16 ) port p3 register (address 7 16 )
stop and wait modes 7735 group users manual 11C6 11.4 wait mode 11.4 wait mode concerning section 11.4 wait mode, the 7735 group differs from the 7733 group in the following: ? table 11.4.2 and figure 11.4.1 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 11.4 wait mode (page 11-13 in part 1)
stop and wait modes 7735 group users manual 11C7 table 11.4.2 pin state in wait mode state single-chip mode memory expansion microprocessor mode mode pins when the standby state selection bit * 1 = 0 when the standby state selection bit * 1 = 1 n when the signal output disable selection bit = 0, h level is output. n when the signal output disable selection bit = 1, l level is output. n when the signal output disable selection bit = 0, h level is output. n when the signal output disable selection bit = 1, l level is output. same as in the micro- processor mode h level is output. __ e ____ rde, ____ wel, ____ weh, ____ ____ cs 0 C cs 4 , _____ rsmp, _____ hlda ale a 0 /d 0 Ca 15 /d 15 , a 16 , a 17 output level can be set. (refer to section 11.4.2 output levels of external bus and bus control signals in wait mode ) l level is output. retains the same state in which the wit instruction is ex- ecuted. n when the signal output disable selection bit *3 = 0 f 1 : stopped when the system clock stop bit at wait state = 0. l level is output when the system clock stop bit at wait state = 1. n when the signal output disable selection bit = 1 p4 2 : bit 2s value of port p4 register is output (note) . n when the clock f 1 output selection bit *2 = 1 f 1 : operating when the system clock stop bit at wait state *4 = 0. l level is output when the system clock stop bit at wait state = 1. n when the clock f 1 output selection bit = 0 p4 2 : retains the same state in which the wit instruction is executed. p4 2 / f 1 p0 to p8 (not including p4 2 ) : retains the same state in which the wit instruction is executed. p4 3 to p4 7 , p5 to p8 : retains the same state in which the wit instruction is executed. ports standby state selection bit *1 : bit 0 at address 6d 16 (refer to figure 11.4.1. ) clock f 1 output selection bit *2 : bit 7 at address 5e 16 (refer to section 12.1 signals required for accessing external devices. ) signal output disable selection bit *3 : bit 6 at address 6c 16 (refer to section 12.1 signals required for accessing external devices. ) system clock stop bit at wait state *4 : bit 5 at address 6c 16 (refer to section 11.4.1 state of clocks f 2 to f 512 in wait mode. ) note: make sure to set bit 2 of the port p4 direction register to 1. 11.4 wait mode
stop and w ait modes 7735 group users manual 11C8 fig. 11.4.1 output level setting example in wait mode (memor y expansion or microprocessor mode) 11.4 wait mode ? when setting the signal output disable selection bit to 1 in the microprocessor mode ? when setting the clock 1 output selection bit to 0 in the memory expansion mode note 2 : this bits value also affects the pin state in the stop mo de. (refer to figure 11.3.1 .) setting of the output levels for the external bus, chip sele ct signals, and bus control signals (not including rde) b7 b0 port p0 direction register (address 4 16 ) must be fixed to ff 16 . 11 11 11 11 port p1 direction register (address 5 16 ) port p2 direction register (address 8 16 ) port p3 direction register (address 9 16 ) b7 b0 port p0 register (address 2 16 ) set output level by bit which corresponds to each pin. 0: l level output 1: h level output port p1 register (address 3 16 ) port p2 register (address 6 16 ) port p3 register (address 7 16 ) setting of e/rde signals output level (setting of pin p4 2 / 1 s state) b7 b0 oscillation circuit control register 0 (address 6c 16 ) signal output disable selection bit (note 3) 0: in the wait mode, pin e/rde outputs h level. pin p4 2 / 1 operates when system clock stop bit at wait state = 0 and outputs l level when this bit = 1. 1: in the wait mode, pin e/rde outputs l level. pin p4 2 / 1 outputs bit 2s value of port p4 register. port function control register (address 6d 16 ) standby state selection bit (note 2) b7 b0 setting of standby state selection bit to 1 01 b7 b0 port p4 direction register (address c 16 ) 1 b7 b0 port p4 register (address a 16 ) 0: l level output 1: h level output wit instruction is executed. note 3 : this bits value also affects the following: ? output state of bus control signals and othe rs after the wait mode is terminated (refer to chapter 12. connecting external devices. ) ? pin state in the stop mode. (refer to figure 11.3.1. ) furthermore, description of pin p4 2 / 1 is applied only in the microprocessor mode. ? when setting the signal output disable selection bit to 0 in the microprocessor mode ? when setting the clock 1 output selection bit to 1 in the memory expansion mode note 1: this is applied only in the microprocessor mode. in the memory expansion mode, it may be 0 or 1 because the i/o port function is selected. (note 1)
12.1 signals required for accessing external devices 12.2 software wait 12.3 ready function 12.4 hold function chapter 12 chapter 12 connecting external devices
connecting external devices 7735 group users manual 12C2 functions for connecting external devices are described in this chapter. reading or writing data from or to external devices are performed by the bus interface unit (biu). (refer to _ section 2.2 bus interface unit. ) the biu operates on the basis of internal enable signal e (usually, _ internal clock f divided by 2) but does not output internal enable signal e to the external. the biu outputs ____ ____ ____ signals rde , wel , and weh . ____ ____ ____ _ signals rde , wel , and weh are generated from internal enable signal e and are output at the same timing _ as that of internal enable signal e . when external devices are accessed, the biu outputs some of these signals, in other words, outputs only signals which are required for the access at that time. 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C3 12.1 signals required for accessing external devices functions and operations of signals required for accessing external devices are described below. when connecting external devices which require a long access time, refer to sections 12.2 software wait, 12.3 ready function, and 12.4 hold function, also. when connecting external devices, make sure that the microcomputer operates in the memory expansion or microprocessor mode. (refer to section 2.5 processor modes. ) when the microcomputer operates in ______ these modes, ports p0 to p4 and pin e/rde function as i/o pins of signals required for accessing external devices. figure 12.1.1 shows the pin configuration in the memory expansion or microprocessor mode. table 12.1.1 __ ____ lists the functions of ports p0 to p4 and pin e/rde in the memory expansion or microprocessor mode. 12.1 signals required for accessing external devices
connecting external devices 7735 group user? manual 12? fig. 12.1.1 pin configuration in memory expansion or micropr ocessor mode (top view) 12.1 signals required for accessing external devices a 4 /d 4 (p2 4 ) a 5 /d 5 (p2 5 ) a 6 /d 6 (p2 6 ) a 7 /d 7 (p2 7 ) wel(p3 0 ) weh(p3 1 ) ale(p3 2 ) hlda(p3 3 ) v ss rde x out x in reset cnv ss byte hold a 11 /d 11 (p1 3 ) a 12 /d 12 (p1 4 ) a 13 /d 13 (p1 5 ) a 14 /d 14 (p1 6 ) a 15 /d 15 (p1 7 ) a 0 /d 0 (p2 0 ) a 1 /d 1 (p2 1 ) a 2 /d 2 (p2 2 ) a 3 /d 3 (p2 3 ) rdy p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 cs 0 (p0 0 ) cs 1 (p0 1 ) cs 2 (p0 2 ) cs 3 (p0 3 ) cs 4 (p0 4 ) rsmp(p0 5 ) a 16 (p0 6 ) a 17 (p0 7 ) a 8 /d 8 (p1 0 ) a 9 /d 9 (p1 1 ) a 10 /d 10 (p1 2 ) p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 14 3 25 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 678 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 43 42 41 m37735 mhbxxxfp 22 23 24 p4 7 p4 6 p4 5 p4 4 p4 3 * 1 p4 2 / 1 a 4 /d 4 (p2 4 ) a 5 /d 5 (p2 5 ) a 6 /d 6 (p2 6 ) a 7 /d 7 (p2 7 ) wel(p3 0 ) weh(p3 1 ) ale(p3 2 ) hlda(p3 3 ) v ss rde x out x in reset cnv ss byte hold rdy a 11 (p1 3 ) a 12 (p1 4 ) a 13 (p1 5 ) a 14 (p1 6 ) a 15 (p1 7 ) a 0 /d 0 (p2 0 ) a 1 /d 1 (p2 1 ) a 2 /d 2 (p2 2 ) a 3 /d 3 (p2 3 ) p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 cs 0 (p0 0 ) cs 1 (p0 1 ) cs 2 (p0 2 ) cs 3 (p0 3 ) cs 4 (p0 4 ) rsmp(p0 5 ) a 16 (p0 6 ) a 17 (p0 7 ) a 8 (p1 0 ) a 9 (p1 1 ) a 10 (p1 2 ) 14 3 2 56789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 43 42 41 m37735 mhbxxxfp p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 * 2 * 1 when external data bus is 8 bits wide (byte = ?? : external address bus, external data bus, chip select signals, and bus control signals h 2 1 in the microprocessor mode when external data bus is 16 bits wide (byte = ?? : external address bus, external data bus, chip select signals, and bus control signals h 1 in the microprocessor mode by setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin? level can be fixed in the stop or wait mode. by setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin? level can be fixed in the stop or wait mode. 1 1 h "h"level is output
connecting external devices 7735 group users manual 12C5 rsmp a 8 /d 8 to a 15 /d 15 rsmp ale a 8 to a 15 d(odd) ale a 0 /d 0 to a 7 /d 7 a 8 to a 15 a 0 to a 7 d(even) a 0 to a 7 d d : data ale ale rsmp p 1 e/rde rde (note 2) 1 a 8 /d 8 to a 15 /d 15 p4 3 to p4 7 a 0 /d 0 to a 7 /d 7 a 8 to a 15 a 0 /d 0 to a 7 /d 7 (note 3) ale hlda wel hlda 1 p4 3 to p4 7 a 16 , a 17 a 16 , a 17 a 16 , a 17 cs 0 to cs 4 cs 0 to cs 4 (note 1) cs 0 to cs 4 wel wel (note 2) wel (note 2) wel hlda hlda hlda weh weh (note 2) (h level output) weh weh rdy rdy rdy hold hold hold pin name 16 bits (byte = l) 8 bits (byte = h) external data bus width notes 1: when the internal area is accessed, signals cs 0 to cs 4 are not output. (output levels are fixed to h.) 2: these signals are affected by the signal output disable sel ection bit (bit 6 at address 6c 16 ). (refer to table 12.1.4 .) 3: in the memory expansion mode, this pin functions as a progr ammable i/o port. furthermore, it can be switched to be a clock 1 output pin when selected by software. in the microprocessor mode, this signal is affected by the signal output disable selecti on bit (bit 6 at address 6c 16 ). (refer to table 12.1.3 .) p : functions as programmable i/o port d(odd) : data at odd address d(even) : data at even address __ ____ table 12.1.1 functions of ports p0 to p4 and pin e/rde in memory expansion or microprocessor mode 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C6 ____ ____ 12.1.1 external bus (a 0 /d 0 to a 15 /d 15 , a 16 and a 17 ) and chip select signals ( cs 0 to cs 4 ) the address (a 0 to a 17 ) and chip select signals are output and specify the external area. figures 12.1.2 and 12.1.3 show the external areas specified by these signals. an area specified by a chip select signal does not the internal area. (when the internal area is accessed, the chip select signal is not output.) pins a 8 to a 15 of the external address bus and pins d 0 to d 15 of the external data bus share the same pins. when pin bytes level, which is described later, is l (in other words, when the external data bus is 16 bits wide), pins a 0 /d 0 to a 15 /d 15 perform address output and data input/output with the time-sharing method. when pin bytes level is h (in other words, when the external data bus is 8 bits wide), pins a 0 / d 0 to a 7 /d 7 perform address output and data input/output with the time-sharing method and pins a 8 to a 15 output the address. fig. 12.1.2 external area (memory expansion mode) 12.1 signals required for accessing external devices : external area specified by address and chip select signal 000000 16 001000 16 memory expansion mode (for m37735mhbxxxfp) 020000 16 0fffff 16 040000 16 080000 16 0c0000 16 cs 1 cs 2 cs 3 cs 4 000080 16 memory allocation selection bits (b2,b1,b0) = 000000 16 001000 16 020000 16 0fffff 16 040000 16 080000 16 0c0000 16 cs 1 cs 2 cs 3 cs 4 000080 16 002000 16 cs 0 (0,0,1) 000000 16 001000 16 020000 16 0fffff 16 040000 16 080000 16 0c0000 16 cs 1 cs 2 cs 3 cs 4 000080 16 008000 16 cs 0 (1,1,0) 000000 16 001000 16 0fffff 16 040000 16 080000 16 0c0000 16 cs 1 cs 2 cs 3 cs 4 000080 16 008000 16 cs 0 (1,1,1) (0,0,0) h the memory allocation selection bits must be set as above. 010000 16 internal ram area sfr area internal rom area internal ram area sfr area internal rom area internal ram area sfr area internal rom area internal ram area sfr area internal rom area
connecting external devices 7735 group users manual 12C7 : external area specified by address and chip select signal microprocessor mode (for m37735mhbxxxfp) cs 1 cs 2 cs 3 cs 4 cs 0 000000 16 0fffff 16 040000 16 080000 16 0c0000 16 001000 16 008000 16 000080 16 internal ram area sfr area fig. 12.1.3 external area (microprocessor mode) 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C8 12.1.2 external data bus width selection signal (pin bytes level) this signal is used to select the external data bus width from 8 bits and 16 bits. when this signal level is l, the external data bus is 16 bits wide; when this signal level is h, the external data bus is 8 bits wide. (refer to table 12.1.1. ) this signal level must be fixed to either h or l. this signal is valid only for the external areas. (when the internal area is accessed, the data bus is always 16 bits wide.) ____ ____ ____ 12.1.3 read enable signal ( rde ) and write enable signals ( wel , weh ) these signals are output when data is read or written from or to the external area. when the internal area is accessed, these signals are stopped at h level by setting the signal output disable selection bit (bit 6 at address 6c 16 ) to 1. (refer to table 12.1.4. ) table 12.1.2 functions of read enable signal and write enable signals external data bus state data is read out. 1-byte data is written to even address. 1-byte data is written to odd address. 1-word data is written. data is read out. data is written. external data bus width 16 bits (byte = l) 8 bits (byte = h) ____ rde h l h h h h l h ____ wel h h l h l h h l ____ weh h h h l l h h h 12.1.4 address latch enable signal (ale) this signal is used to latch an address from a multiplexed signal. this multiplexed signal consists of the address and data and is input or output to or from pins a 0 /d 0 to a 15 /d 15 , a 16 /d 0 to a 23 /d 7 . when this signal level is h, take the address into a latch and output it simultaneously. when this signal level is l, retain the latched address. ____ _____ 12.1.5 signals related to ready function ( rdy , rsmp ) these signals are required to use the ready function. (refer to section 12.3 ready function. ) _____ _____ 12.1.6 signals related to hold function ( hold , hlda ) these signals are required to use the hold function. (refer to section 12.4 hold function. ) 12.1.7 clock f 1 this signal has the same period as internal clock f . whether clock f 1 is output or stopped can be selected by software. however, the method of this selection depends on the processor mode. table 12.1.3 lists the method to select whether to output or stop clock f 1 . figure 12.1.4 shows the clock f 1 output start timing. 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C9 table 12.1.3 method to select whether to output or stop clock f 1 clock f 1 output clock f 1 stopped remark processor mode single-chip or memory expansion mode microprocessor mode clear the signal output disable selection bit *2 to 0. set the signal output disable selection bit to 1. (note) clock f 1 is output after reset. the clock f 1 output selection bit is ignored. set the clock f 1 output selection bit *1 to 1. clear the clock f 1 output selection bit to 0. (pin p4 2 functions as a programmable i/o port.) clock f 1 is stopped after reset. the signal output disable selection bit is ignored. clock f 1 output selection bit *1 : bit 7 at address 5e 16 signal output disable selection bit *2 : bit 6 at address 6c 16 (refer to table 12.1.4 .) note: when bit 2 at address c 16 (port p4 direction register) is set to 1, bit 2 of the port p4 register is output. table 12.1.4 functions of signal output disable bit processor mode conditions signal output disable selection bit 0 memory expansion or microprocessor mode signals ____ rde, ____ wel, ____ weh ____ rde, ____ wel, ____ weh ____ rde, ____ wel, ____ weh clock f 1 1 when the external area is accessed when the internal area is accessed when the standby state selection bit = 1 in the stop or wait mode when the standby state selection bit = 0 in the stop or wait mode operating operating stopped at h level stopped at h level stopped at l level stopped at h level stopped (output levels can be set.) (refer to figures 11.3.1 and 11.4.1 .) stopped (note) microprocessor mode enable signal __ e when not in the stop or wait mode single-chip mode when in the stop or wait mode operating stopped at h level stopped at l level stopped at l level h all functions listed in table 12.1.4 are not emulated by a debugger. h for the stop and wait modes and the standby state selection bit, refer to chapter 11. stop and wait modes. note: when bit 2 at address c 16 (port direction register) is set to 1, bit 2 of the port p4 register is output. :not affected by the signal output disable selection bit. each signals state operating (independent of the f 1 output selection bit) 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C10 fig. 12.1.4 clock f 1 output start timing (when clock f 1 output selection bit is set from 0 to 1) fig. 12.1.5 structure of oscillation circuit control registe r 0 clock 1 e : there is a possibility that the first cycle of clock 1 output is not an exact square; the shaded section may be lost. : this is applied when 1 is written to the clock 1 output selection bit while pin p4 2 outputs l level. the clock 1 output selection bit is set to 1. bit bit name functions at reset rw 0 1 2 3 4 5 6 7 x cout drivability selection bit main clock stop bit system clock selection bit port-xc selection bit not implemented. 0 0 0 0 un- defined 0 0: drivability low 1: drivability high when the port-xc selection bit = 0, 0: main clock 1: main clock divided by 8 when the port-xc selection bit = 1, 0: main clock 1: sub clock 1 un- defined oscillation circuit control register 0 (address 6c 16 ) b1 b0 b2 b3 b4 b5 b6 b7 notes 0: main clock oscillation or external clock input is available. 1: main clock oscillation or external clock input is stopped. rw rw C not implemented. C rw ( note 1 ) 0: operate as i/o ports (p7 7 , p7 6 ). 1: operate as pins x cin and x cout . rw ( notes 2 and 3 ) rw ( note 2 ) system clock stop bit at wait state (note 4) 0: output is enabled. 1: output is disabled. (refer to tables 12.1.3 and 12.1.4 ) 0: operates in the wait mode. 1: stopped in the wait mode. signal output disable selection bit rw ( note 1 ) 1: nothing can be written to this bit after reset. writing to this bit is enabled when the port-xc selection bit = 1. 2: when selecting the sub clock as the system clock, set bit 3 to 1 after setting bit 4 to 1. if the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to 1 . 3: although this bit can be set to 1, it cannot be cleared t o 0 after this bit is once set to 1. 4: when setting the system clock stop bit at wait state to 1, perform it immediately before the wit instruction is executed. furthermore, clear this bit to 0 immediately after the wait mode is terminated. 5: represents that bits 0 to 5 and 7 are not used for a ccess control of external area. (functions of these bits are valid.) 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C11 12.1 signals required for accessing external devices fig. 12.1.6 relationship between setting of signal output di sable selection bit and stop timing of each signal weh wel rde clock 1 (in the microprocessor mode) note: these signals can be stopped only when accessing internal a rea (in the memory expansion and microprocessor modes). internal enable signal e (in single-chip mode) h (note) (note) (note) value 1 is written to the signal output disable selection bit. signal is stopped.
connecting external devices 7735 group users manual 12C12 12.1.8 operation of bus interface unit (biu) figures 12.1.7 to 12.1.9 show operating waveform examples of signals which are input to or output from the external when accessing external devices. these waveforms are described in relation to the basic operating waveforms. (refer to section 2.2.3 operation of bus interface unit (biu). ) (1) when fetching an instruction into an instruction queue buffer when an instruction which is next fetched resides at an even address when the external data bus is 16 bits wide, the biu fetches two bytes of the instruction at a time with waveform (a). when the external data bus is 8 bits wide, the biu fetches only one byte of the instruction with the first half of waveform (i). when an instruction which is next fetched resides at an odd address when the external data bus is 16 bits wide, the biu fetches only one byte of the instruction with waveform (g). when the external data bus is 8 bits wide, the biu fetches only one byte of the instruction with the first half of waveform (i). when branched to an odd address by executing a branch instruction or others with the 16-bit external data bus, at first, the biu fetches one byte of an instruction with waveform (g) and then fetches instructions by the two bytes with waveform (a). (2) when reading or writing data from or to memory ? i/o when accessing 16-bit data which starts from an even address, waveform (a), (b), (i) or (j) is applied. when accessing 16-bit data which starts from an odd address, waveform (c), (d), (i) or (k) is applied. a when accessing 8-bit data which resides at an even address, waveform (e), (f) or the first half of waveform (i) or (j) is applied. ? when accessing 8-bit data which resides at an odd address, waveform (g), (h) or the first half of waveform (k) is applied. for instructions which are affected by data length flag (m) and index register length flag (x), an operation is applied as follows.: ?when m or x = 0, operation or is applied. ?when m or x = 1, operation a or ? is applied. settings of flags m and x and selection of the external data bus width do not affect each other. 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C13 data (even) data (odd) address address rde ale cs 0 to cs 4 a 16 , a 17 weh wel ? address a 0 /d 0 to a 7 /d 7 a 8 /d 8 to a 15 /d 15 address address address address (note 3) rde ale cs 0 to cs 4 a 16 , a 17 weh wel ? address (note 3) address a 0 /d 0 to a 7 /d 7 a 8 /d 8 to a 15 /d 15 address address address address rde ale cs 0 to cs 4 a 16 , a 17 weh wel ? address (note 2) address a 0 /d 0 to a 7 /d 7 a 8 /d 8 to a 15 /d 15 ? (note 1) (note 2) (note 1) rde (a) read starting from even address ale cs 0 to cs 4 a 0 /d 0 to a 7 /d 7 a 16 , a 17 address a 8 /d 8 to a 15 /d 15 address weh wel ? ? address (note 1) notes 1: these pins which function as the external bus enter the floating state. while these pins are in the floating state, data on the data bus is fetched into the data buffer of the biu. 2: these pins which function as the external bus enter the floating state. while these pins are in the floating state, data on the data bus is not fetched fetched into the data buffer of the biu. 3: invalid data (undefined value) ? ? l when external data bus is 16 bits wide (byte = ??) <16-bit data access> (b) write starting from even address (c) read starting from odd address (d) write starting from odd address (note 1) data (even) data (odd) fig. 12.1.7 operating waveform example of signals which are input to or output from the external (1) 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C14 rde ale cs 0 to cs 4 a 0 /d 0 to a 7 /d 7 a 16 , a 17 address a 8 /d 8 to a 15 /d 15 address weh wel ? ? address (note 2) (note 1) address address (note 3) rde ale cs 0 to cs 4 a 16 , a 17 weh wel ? address data (even) a 0 /d 0 to a 7 /d 7 a 8 /d 8 to a 15 /d 15 ? address address (note 3) rde ale cs 0 to cs 4 a 16 , a 17 weh wel ? address data (odd) a 0 /d 0 to a 7 /d 7 a 8 /d 8 to a 15 /d 15 ? rde ale cs 0 to cs 4 a 0 /d 0 to a 7 /d 7 a 16 , a 17 address a 8 /d 8 to a 15 /d 15 address weh wel ? ? address (note 1) (note 2) (e) read starting from even address l when external data bus is 16 bits wide (byte = ??) <8-bit data access> (f) write starting from even address (g) read starting from odd address (h) write starting from odd address notes 1: these pins which function as the external bus enter the floating state. while these pins are in the floating state, data on the data bus is fetched into the data buffer of the biu. 2: these pins which function as the external bus enter the floating state. while these pins are in the floating state, data on the data bus is not fetched into the data buffer of the biu. 3: invalid data (undefined value) fig. 12.1.8 operating waveform example of signals which are input to or output from the external (2) 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C15 address address rde ale cs 0 to cs 4 a 16 , a 17 weh wel ? a 0 /d 0 to a 7 /d 7 a 8 to a 15 address data (even) address data (odd) address address (i) read starting from even or odd address rde ale cs 0 to cs 4 a 0 /d 0 to a 7 /d 7 a 16 , a 17 address a 8 to a 15 address weh wel ? ? address address (note) (note) address address address address rde ale cs 0 to cs 4 a 16 , a 17 weh wel ? a 0 /d 0 to a 7 /d 7 a 8 to a 15 address data (odd) address data (even) address address l when external data bus is 8 bits wide (byte = ??) <8/16-bit data access> h when 16-bit data is accessed, the low-order 8 bits of data are accessed first, and then, the high-order 8 bits are accessed. 8-bit data access 16-bit data access (j) write starting from even address (k) write starting from odd address 8-bit data access 16-bit data access 8-bit data access 16-bit data access note: these pins which function as the external bus enter the floating state. while these pins are in the floating state, data on the data bus is fetched into the data buffer of the biu. fig. 12.1.9 operating waveform example of signals which are input to or output from the external (3) 12.1 signals required for accessing external devices
connecting external devices 7735 group users manual 12C16 12.2 software wait the software wait facilitates access to external devices which require a long access time. there are two types of software waits: wait 0 and wait 1. the software wait is set by the wait bit (bit 2 at address 5e 16 ) and the wait selection bit (bit 0 at address 5f 16 ). (refer to table 12.2.1. ) figure 12.2.1 shows the structures of the processor mode register 0 (address 5e 16 ) and processor mode register 1 (address 5f 16 ). figure 12.2.2 shows bus timing examples when the software wait is used. the software wait is valid only for the external area. (access to the internal areas is always performed with no wait.) for external devices which can not be accessed even when using the software wait, by using the ready _____ function (signal rsmp ), a wait which is equivalent to 1 cycle of clock f 1 can furthermore be generated. (refer to section 12.3 ready function. table 12.2.1 setting method of software wait wait bit wait selection bit software wait bus cycle 1 0 0 invalid (no wait) wait 0 wait 1 cycle of internal clock f divided by 2 (clock f 1 s cycle 5 2) cycle in the no-wait state 5 2 (clock f 1 s cycle 5 4 ) cycle in the no-wait state 5 1.5 (clock f 1 s cycle 5 3 ) 0 0 1 12.2 software wait
of the external area. connecting external devices 7735 group users manual 12C17 fig. 12.2.1 structures of processor mode register 0 and proc essor mode register 1 b2 b3 b4 b5 b6 b7 b1 processor mode register 1 (address 5f 16 ) b0 bit bit name function at reset 0 7 to1 wait selection bit 0 : wait 0 1 : wait 1 0 not implemented. un- defined rw rw _ bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits wait bit software reset bit interrupt priority detection time selection bits must be fixed to 0. clock f 1 output selection bit (note 2) 0 0 0 0 0 0 00: single-chip mode 01: memory expansion mode 10: microprocessor mode 11: do not select. 0: software wait is inserted when accessing external area. 1: no software wait is inserted when accessing external area. microcomputer is reset by setting this bit to 1. this bit is 0 at reading. 00: 7 cycles of f 01: 4 cycles of f 10: 2 cycles of f 11: do not select. 0: clock f 1 output is disabled. (p4 2 functions as a programmable /o port.) 1: clock f 1 output is enabled. (port p4 2 functions as a clock f 1 output pin.) 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) (note 1) notes 1: when the vcc-level voltage is applied to pin cnvss, this bit is set to 1 after reset. (at reading, this bit is always 1.) 2 : this bit is ignored in the microprocessor mode. (it may be 0 or 1.) 3: represents that bits 3 to 6 are not used for access control (functions of these bits are valid.) b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw wo rw rw rw rw 12.2 software wait
connecting external devices 7735 group users manual 12C18 fig. 12.2.2 bus timing examples when software wait is used ( byte = l ). << no wait>> clock 1 rsmp cs 0 to cs 4 a 16 , a 17 a 0 /d 0 to a 15 /d 15 h ale 1-bus cycle (note) <> clock 1 rsmp cs 0 to cs 4 a 16 , a 17 a 0 /d 0 to a 15 /d 15 h ale 1-bus cycle (note) <> clock 1 rsmp cs 0 to cs 4 a 16 , a 17 a 0 /d 0 to a 15 /d 15 h ale data 1-bus cycle (note) address l this waveform is always applied when the internal area is ac cessed. note : when the external data bus is 8 bits wide (byte = h ), o perating waveform of a 8 /d 8 to a 15 /d 15 is the same as that of a 16 and a 17 . address address address data address data address address address data address data address address address data h one of the following is applied.: ?one of signals rde, wel, and weh ?signals wel and weh 12.2 software wait
connecting external devices 7735 group users manual 12C19 p4 2 / f 1 timers a and b, serial i/o, a-d converter, watchdog timer item state 12.3 ready function the ready function facilitates access to external devices wh ich require a long access time. ____ by applying l level to pin rdy in the memory expansion or microprocessor mode, the microco mputer ____ enters the ready state. while pin rdy s level is l, this state is retained. table 12.3.1 lists the microcomputers state in the ready state. in the ready state, oscillation of the oscillator does not s top. therefore, the internal peripheral devices can operate even in the ready state. the ready function is valid for the internal and external areas. table 12.3.1 microcomputers state in ready state clock f 1 output selection bit *1 : bit 7 at address 5e 16 signal output disable selection bit *2 : bit 6 at address 6c 16 ____ notes 1: when l level which was input to pin rdy is sampled at one of the following timings, this signal is not accepted. (note that f cpu is stopped at l level.) ____ ____ ____ l when the levels of signals rde , wel , and weh are h while the bus is in use (refer to in figure 12.3.2 .) l immediately before a wait generated by the software wait (r efer to ? in figure 12.3.2. ) 2: this is applied when these pins function as programmable i/o ports. oscillation f cpu operating stopped at l level ____ retains the same state in which rdy was accepted. in the memory expansion mode n when the clock f 1 output selection bit *1 = 1 outputs clock f 1 . n when the clock f 1 output selection bit = 0 ____ retains the same state in which rdy was accepted. in the microprocessor mode n when the signal output disable selection bit *2 = 1 ____ retains the same state in which rdy was accepted. n when the signal output disable selection bit = 0 outputs clock f 1 . operating ____ ____ ____ rde , wel , weh , cs 0 to cs 4 , _____ hlda , ale, a 0 /d 0 to a 15 /d 15 , a 16 , a 17 p4 3 to p4 7 , p 5 to p 8 (note 2) 12.3 ready function
connecting external devices 7735 group users manual 12C20 m37735mhbxxxfp rdy rsmp cs n n : 0 to 4 chip select signal _____ fig. 12.3.1 connection example when signal rsmp is used 12.3.1 operation in ready state ____ when l level is input to pin rdy , this signal is accepted at the falling edge of clock f 1 and the microcomputer ____ enters the ready state. the ready state can be terminated by setting pin rdy s level to h again. when ____ h level is input to pin rdy , this signal is also accepted at the falling edge of clock f 1 and the ready state is terminated. figure 12.3.2 shows timings when the ready st ate is accepted and terminated. when generating a wait which is equivalent to 1 cycle of clo ck f 1 by using the ready function, use signals _____ ____ rsmp and cs n (n = 0 to 4). these signals facilitate to generate a signal input to pin rdy . figure 12.3.1 _____ _____ shows a connection example when signal rsmp is used. note that signal rsmp is affected by the software _____ wait. figure 12.3.3 shows the relationship between the softw are wait and signal rsmp . refer to section 17.1 memory expansion for the way to use the ready function. 12.3 ready function
connecting external devices 7735 group users manual 12C21 : ready state : software wait ? one of signals rde, wel, and weh ? signals wel and weh h one of the following is applied.: <> sampling timing clock 1 cpu rdy ale ? a bus is not in use. bus is in use. ? ready state is terminated. l level which is input to pin rdy is accepted, so that signal h is stopped at h level for 1cycle of clock 1 (area ), and cpu is stopped at l level. l level which is input to pin rdy is not accepted, but cpu is stopped at l level. a l level which is input to pin rdy is accepted, so that signal h is stopped at l level for 1cycle of clock 1 (area ), and cpu is stopped at l level. ? l level which is input to pin rdy is not accepted because it is sampled immediately before a wait generated by software wait (area ), but cpu is stopped at l level. sampling timing clock 1 cpu rdy ale <> bus is in use. sampling timing clock 1 cpu rdy ale <> bus is in use. ?? a ?? a h h h _____ fig. 12.3.2 timings when ready state is accepted and termina ted (when not using signal rsmp ) 12.3 ready function
connecting external devices 7735 group users manual 12C22 h one of the following is applied.: : ready state : software wait <> h cpu ale rdy clock 1 rsmp cs 0 to cs 4 <> rdy ale clock 1 cpu h rsmp cs 0 to cs 4 clock 1 ale cpu h <> rdy cs 0 to cs 4 rsmp ? one of signals rde, wel, and weh ? signals wel and weh _____ fig. 12.3.3 relationship between software wait and signal rsmp 12.3 ready function
connecting external devices 7735 group users manual 12C23 12.4 hold function when an external circuit which accesses the bus without usin g the central processing unit (cpu), for example dma, is used, it is necessary to generate a timing f or transferring the right to use of the bus from the cpu to the external circuit. the hold function is used t o generate this timing. _____ by applying l level to pin hold in the memory expansion or microprocessor mode, the microco mputer _____ enters the hold state. while pin hold s level is l, this state is retained. table 12.4.1 lists the microcomputers state in the hold state. in the hold state, oscillation of the oscillator does not st op. therefore, the internal peripheral devices can operate even in the hold state. (note that the watchdog time r stops.) table 12.4.1 microcomputers state in hold state item state operating stopped at l floating oscillation f cpu ____ ____ ____ rde , wel , weh , cs 0 to cs 4 , _____ rsmp , a 0 /d 0 to a 15 /d 15 , a 16 , a 17 outputs l level. _____ hlda , ale p4 2 / f 1 p4 3 to p4 7 , p5 to p8 (note) timers a and b, serial i/o, a-d converter watchdog timer in the memory expansion mode n when the clock f 1 output selection bit *1 = 1 outputs clock f 1 . n when the clock f 1 output selection bit = 0 _____ retains the same state in which hold was accepted. in the microprocessor mode n when the signal output disable selection bit *2 = 1 _____ retains the same state in which hold was accepted. n when the signal output disable selection bit = 0 outputs clock f 1 . _____ re tains the same state in which hold was accepted. operating stopped clock f 1 output selection bit *1 : bit 7 at address 5e 16 signal output disable selection bit *2 : bit 6 at address 6c 16 note: this is applied when these pins function as programmable i/ o ports. 12.4 hold function
connecting external devices 7735 group users manual 12C24 a clock 1 ale at reading at writing rde l determination timing of pin hold s input level a not determined determined word data is accessed by the two bus cycles. (in this case, no wait) a a ww 12.4.1 operation in hold state _____ when l level is input to pin hold while the bus is not in use, this signal is accepted at the falling edge _____ of clock f 1 . when l level is input to pin hold while the bus is in use, this signal is accepted at the clo ck ____ ____ ____ f 1 s falling edge which precedes the rising edge of signal rde , wel , or weh by the clock f 1 s cycle divided by 2. (refer to figures 12.4.2 to 12.4.6. ) note that when word data which starts from an odd address is accessed by the two bus cycles, determination is performed o nly in the second bus cycle. (refer to figure 12.4.1. ) _____ when l level which was input to pin hold is accepted, f cpu is stopped at the next rising edge of clock _____ f 1 . at this time, pin hlda outputs l level, and so the external is informed that the microcomputer is in _____ ____ ____ the hold state. after one cycle of clock f 1 has passed since pin hlda s level becomes l, pins rde , wel , ____ _____ weh , cs 0 to cs 4 , rsmp and the external bus enter the floating state. _____ the hold state can be terminated by setting pin hold s level to h again. when h level is input to pin _____ _____ hold , this signal is accepted at the falling edge of clock f 1 . when h level which was input to pin hold _____ is accepted, pin hlda s level goes from l to h. and then, the hold state is t erminated after one cycle of clock f 1 has passed. figures 12.4.2 to 12.4.6 show the timing when the hold state is accepted and terminated. _____ h in the ready state, determination of pin hold s input level is not performed. fig.12.4.1 determination when word data which starts from odd address i s accessed by the two bus cycles 12.4 hold function
connecting external devices 7735 group users manual 12C25 12.4 hold function external address bus because the bus is not in use, the address which was output immediately before is output again, instead of a new address. hlda hold bhe ale h external address bus/ external data bus sampling timing note: the same operation is performed independent of the software wait (no wait, wait 0, or wait 1). this diagram shows the operation when no wait is s elected. cs 0 to cs 4 clock 1 external data bus data length external data bus width software wait 16 8, 16 no wait, not in use l state when l level is input to pin hold wait 1, wait 0 8, 16 8 <> address b 1 5 1 1 5 1 bus is in use. bus is not in use. address a data address a floating floating bus is in use. hold state h rde, wel, weh fig. 12.4.2 timing when hold state is accepted and terminate d (1)
connecting external devices 7735 group users manual 12C26 external data bus data length 8 16 8, 16 16 (when accessed starting from even address) no wait in use state when l level is input to pin hold external data bus width software wait ale h hlda hold cs 0 to cs 4 address a 1 5 1 1 5 1 hold state sampling timing <> external address bus/ external data bus external address bus clock 1 data floating bhe address a floating address b floating bus is not in use. when l level which is input to pin hold is accepted, the address which was output immediately before is output again, instead of a new add ress. bus is in use. h rde, wel, weh bus is in use. fig. 12.4.3 timing when hold state is accepted and terminate d (2) 12.4 hold function
connecting external devices 7735 group users manual 12C27 address a external address bus/ external data bus external data bus data length external data bus width software wait 8 16 8, 16 16 (when accessed starting from even address) wait 1 in use l state when l level is input to pin hold ale h hlda hold cs 0 to cs 4 address a address b 1 5 1 1 5 1 hold state sampling timing <> external address bus clock 1 data floating floating floating bhe bus is in use. bus is in use. bus is not in use. when l level which is input to pin hold is accepted, the address which was output immediately before is output again, instead of a new add ress. h rde, wel, weh fig. 12.4.4 timing when hold state is accepted and terminate d (3) 12.4 hold function
connecting external devices 7735 group users manual 12C28 external data bus data length external data bus width software wait 8 16 8, 16 16 (when accessed starting from even address) wait 0 in use l state when l level is input to pin hold ale hlda hold address a address b 1 5 1 1 5 1 hold state data sampling timing <> external address bus/ external data bus external address bus clock 1 address a floating floating floating bhe h cs 0 to cs 4 bus is in use. bus is in use. bus is not in use. when l level which is input to pin hold is accepted, the address which was output immediately before is output again, instead of a new add ress. h rde, wel, weh fig. 12.4.5 timing when hold state is accepted and terminate d (4) 12.4 hold function
connecting external devices 7735 group users manual 12C29 when l level which is input to pin hold is the accepted, the address which was output immediately before is output again, instead of a new add ress. sampling is not performed until 16-bit data input/output is finished. ( l level which is input to pin hold is not accepted.) external address bus/ external data bus ale hlda hold address 1 5 1 1 5 1 hold state not sampled external data bus data length external data bus width software wait 16 8 16 (when accessed starting from even address) no wait in use l state when l level is input to pin hold sampling timing bus is in use. <> external address bus clock 1 data high-order address floating floating floating bus is in use. bhe data low-order address h cs 0 to cs 4 h rde, wel, weh bus is not in use. fig. 12.4.6 timing when hold state is accepted and terminate d (5) 12.4 hold function
connecting external devices 7735 group users manual 12C30 memo 12.4 hold function
chapter 13 chapter 13 reset 13.1 hardware reset 13.2 software reset
reset 7735 group users manual 13C2 concerning chapter reset, the 7735 group differs from the 7733 group in the following section. therefore, only the differences are described in this chapter: ? 13.1 hardware reset the following section of the 7735 group is the same as that of the 7733 group. therefore, for this section, refer to part 1: ? 13.2 software reset (page 13-12 in part 1) 13.1 hardware reset concerning section 13.1 hardware reset, the 7735 group dif fers from the 7733 group in the following: ______ ? table 13.1.1 pin state while pin reset is at l level ? figure 13.1.6 state of sfr area and internal ram area imm ediately after reset (4) the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 13.1 hardware reset (page 13-2 in part 1) 13.1 hardware reset mask rom version built-in prom version external rom version pin cnv ss s level v ss or v cc v ss v cc v cc pin state floating h level is output. floating h level is output. floating ?floating when h level is applied to both or one of pins p5 1 and p5 2 ?h or l level is output when l level is applied to both of pins p5 1 and p5 2 . h level is output. h or l level is output. h level is output. l level is output. 1 (operating) is output. floating ______ table 13.1.1 pin state while pin reset is at l level pin (port) name p0 to p8 _ ____ e/rde p0 to p8 _ ____ e/rde p0, p1, p3 to p8 p2 _ ____ e/rde a 0 /d 0 to a 7 /d 7 , a 8 /d 8 to a 15 /d 15 , a 16 , a 17 ___ ___ ____ cs 0 to cs 4 , wel, ____ _____ _ ____ weh, hlda, e/rde ale 1 ______ ____ hold, rdy, p4 3 to p4 7 , p5 to p8
reset 7735 group users manual 13C3 13.1 hardware reset figure 13.1.6 for the 7735 group differs from that for the 7 733 group only in ] 3. fig. 13.1.6 state of sfr area and internal ram area immediat ely after reset (4) 0 ro uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address oscillation circuit control register 0 serial transmit control register a-d / uart2 trans./rece. interrupt control register uart0 transmission interrupt control register uart1 transmission interrupt control register int 2 /key input interrupt control register watchdog timer frequency selection flag register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw( ] 2) rw rw rw rw b7 b0 wo rw rw rw rw rw rw rw rw rw rw state immediately after reset ? ? ? ? ? 0 00 0 ? 0 ? ( h 1) b7 b0 ? 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 port function control register uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register rw rw wo rw rw rw 00 0 0 0 1 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 ? ? ? 00 0 0 0 0 00 0 0 0 0 value fff 16 is set to the watchdog timer. (refer to section chapter 10. watchdog timer. ) for access characteristics at address 6c 16 , also refer to figure 14.3.2 in part 1. state immediately after reset for bit 3 at address 6f 16 vary according to the microcomputer. (refer to figure 14.3.3 in part 2 ; this bits function of the 7735 group differs from that o f the 7733 group.) this bit must be fixed to 0 in the 7735 group. do not write data to address 62 16 . n internal ram area (m37735mhbxxxfp: addresses 80 16 to fff 16 ) at hardware reset (not including the case where the stop or wait mode is te rminated)...undefined. at software reset...retains the state immediately before res et . when the stop or wait mode is terminated (when hardware reset is applied)...retains the state imme diately before the stp or wit i nstruction is executed. ? rw ] 3 00 0 ] 1 ] 2 ] 3 ] 4 (reserved area) ] 4 memory allocation control register uart2 transmit/receive mode register uart2 baud rate register (brg2) uart2 transmission buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register oscillation circuit control register 1 rw 0 ? 0 00 0 rw ? 00 0 0 0 0 0 wo wo wo rw ro 1 00 0 rw rw ro ro 00 0 0 00 1 0 ro 00 0 00 0 ? rw ? ? 0 00 0 0 00 0 ? 0
reset 7735 group users manual 13C4 13.1 hardware reset memo
chapter 14 chapter 14 clock generating circuit 14.1 overview 14.2 oscillation circuit example 14.3 clock control
clock generating circuit 7735 group users manual 14-2 14.3 clock control concerning chapter 14. clock generating circuit, the 7735 group differs from the 7733 group in the following section. therefore, only the differences are described in this chapter: ? 14.3 clock control the following sections are the same as those of the 7733 group. therefore, for these sections, refer to part 1: ? 14.1 overview (page 14-2 in part 1) ? 14.2 oscillation circuit example (page 14-3 in part 1) 14.3 clock control concerning section 14.3 clock control, the 7735 group differs from the 7733 group in the following: ? figures 14.3.3 and 14.3.4 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 14.3 clock control (page 14-5 in part 1)
clock genera ting circuit 7735 group users manual 14-3 fig. 14.3.3 structure of oscillation circuit control regist er 1 fig. 14.3.4 procedure for writing data to oscillation circu it control register 1 14.3 clock control in the m37735mhbxxxfp, set bit 3 of the oscillation circuit control register 1 to 0. notes 1: when writing to this register, follow the procedure shown in figure 14.3.4. 2: because this bit is 1 at reset, clear this bit to 0 wit h the initial setting program after reset. 3: the case where data 01010101 2 is written with the procedure shown in figure 14.3.4 is not included. 4: for the 7733 group, refer to figure 14.3.3 in part 1. 5: represents that bits 3 to 7 are not used for the clo ck generating circuit. bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to 0 in the one time prom and eprom versions (notes 1 and 2) . must be fixed to 0 (note 3) . clock prescaler reset bit 0 0 0 0 undefined 0 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input fro m the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. b1 b0 b2 b3 b4 b5 b6 b7 by writing 1 to this bit, clock prescaler is initialized. rw 1 (note 4) 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. must be fixed to 0 in the mask rom and external rom versio ns (note 1) . (note 1) (note 1) (note 1) 0 write data 01010101 2 . ( ldm instruction) ? when writing to bits 0 to 3 write data 00000xxx 2 . ( ldm instruction) next instruction (b3 in figure 14.3.3) (b2 to b0 in figure 14.3.3)
clock generating circuit 7735 group users manual 14-4 14.3 clock control memo
chapter 15 chapter 15 electrical characteristics 15.1 absolute maximum ratings 15.2 recommended operating conditions 15.3 electrical characteristics 15.4 a-d converter characteristics 15.5 internal peripheral devices 15.6 ready and hold 15.7 single-chip mode 15.8 memory expansion mode and microprocessor mode : with no wait 15.9 memory expansion mode and microprocessor mode : with wait 1 15.10 memory expansion mode and microprocessor mode : with wait 0 15.11 measuring circuit for ports p0 to p8 and pins f 1 and _ e
electrical characteristics 7735 group users manual 15C2 electrical characteristics of the m37735mhbxxxfp are described in this chapter. for the low voltage version, refer to section 18.4 electrical characteristics. concerning chapter 15. electrical characteristics, the 7735 group differs from the 7733 group in the following sections. therefore, only the differences are described in this chapter: ? 15.6 ready and hold ? 15.8 memory expansion mode and microprocessor mode : with no wait ? 15.9 memory expansion mode and microprocessor mode : with wait 1 ? 15.10 memory expansion mode and microprocessor mode : with wait 0 the following sections are the same as those of the 7733 group. therefore, refer to part 1: ? 15.1 absolute maximum ratings (page 15-2 in part 1) ? 15.2 recommended operating conditions (page 15-3 in part 1) ? 15.3 electrical characteristics (page 15-4 in part 1) ? 15.4 a-d converter characteristics (page 15-5 in part 1) ? 15.5 internal peripheral devices (page 15-6 in part 1) ? 15.7 single-chip mode (page 15-13 in part 1) _ ? 15.11 measuring circuit for ports p0 to p8 and pins f 1 and e (page 15-21 in part 1)
electrical characteristics 7735 group users manual 15C3 15.6 ready and hold timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note) , unless otherwise noted) 15.6 ready and hold h the rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. hold input setup time rdy input hold time hold input hold time limits t su(rdyC f 1 ) t su(holdC f 1 ) t h( f 1 Crdy) t h( f 1 Chold) rdy input setup time max. ns ns ns ns min. parameter symbol unit 55 55 0 0 note: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) hlda output delay time t d( f 1 Chlda) ns min. max. 50 limits unit conditions parameter fig. 15.11.1 in part 1 symbol
electrical characteristics 7735 group users manual 15C4 15.6 ready and hold 1 with no wait 1 with wait rdy input ready wel, weh, rde output wel, weh, rde output rdy input t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) measuring conditions ? v cc = 5 v 10 % ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 hold input hlda output t h( 1 Chold) t d( 1 Chlda) t su(holdC 1 ) hold t d( 1 Chlda)
electrical characteristics 7735 group users manual 15C5 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) symbol t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( f 1 Crsmp) t d(weC f 1 ) t d(rdeC f 1 ) 15.8 memory expansion mode and microprocessor mode : with no wait 15.8 memory expansion mode and microprocessor mode : with no wait timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. t c t w(h) t w(l) t r t f t su(dCrde) t h(rdeCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 40 15 15 32 0 parameter max. 8 8 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: when the main clock division selection bit = 1, the minimu m value of tc = 80 ns. 3: when the main clock division selection bit = 1, values of tw (h) /tc and tw (l) /tc must be set to values from 0.45 through 0.55. switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits data formula (min.) max. 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) parameter chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time ____ ____ wel, weh pulse width floating start delay time floating release delay time ____ rde pulse width _____ rsmp output delay time _____ rsmp hold time f 1 output delay time C 22 C 30 C 20 C 32 C 30 conditions fig. 15.11.1 in part 1 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . 45 5 18 C 28 C 28 C 22 C 18 C 35 C 28 min. 12 4 12 12 18 22 5 9 4 18 50 20 48 10 0 0
electrical characteristics 7735 group users manual 15C6 15.8 memory expansion mode and microprocessor mode : with no wait t h(weCdq) t su(aCale) address/data output a 0 /d 0 Ca 15 /d 15 (byte = l ) a 0 /d 0 Ca 7 /d 7 (byte = h ) t d(weC 1 ) t d(csCwe) t d(weC 1 ) t w(we) t d(rsmpCwe) x in 1 cs 0 Ccs 4 output wel output weh output rde output with no wait (wait bit = 1) t d(rdeC 1 ) memory expansion mode and microprocessor mode : t d(anCwe) ale output <> <> t w(h) t w(l) t f t r t c t h(aleCa) t w(h) t w(l) t f t r t c t h(weCcs) address output a 8 Ca 15 (byte = h ) a 16 , a 17 t w(ale) address address t d(aCwe) t d(weCdq) data input d 0 Cd 15 (byte = l ) d 0 Cd 7 (byte = h ) rsmp output t d(aleCwe) t h(weCan) t d(rdeC 1 ) t h(rdeCcs) t d(csCrde) address t h(rdeCan) t d(anCrde) address address address data t pzx(rdeCdz) t d(aCrde) t su(dCrde) t h(rdeCd) t d(rsmpCrde) measuring conditions (cs 0 C cs 4 , a 0 /d 0 C a 15 /d 15 , a 16 , a 17 , ale, wel, weh, rde, rsmp ) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v port pi output (i = 4C8) port pi input (i = 4C8) measuring conditions (ports p4Cp8) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v t d(weCpiq) t su(pidCrde) t h(rdeCpid) data t su(aCale) t w(ale) t h(aleCa) t pxz(rdeCdz) t d(aleCrde) t w(rde) data address 1 Crsmp) t h( 1 Crsmp) t h(
electrical characteristics 7735 group users manual 15C7 symbol t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( f 1 Crsmp) 15.9 memory expansion mode and microprocessor mode : with wa it 1 15.9 memory expansion mode and microprocessor mode : with wa it 1 timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. t c t w(h) t w(l) t r t f t su(dCrde) t h(rdeCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 40 15 15 32 0 parameter max. 8 8 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: when the main clock division selection bit = 1, the minimu m value of tc = 80 ns. 3: when the main clock division selection bit = 1, values of tw (h) /tc and tw (l) /tc must be set to values from 0.45 through 0.55. switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns data formula (min.) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) parameter chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time ____ ____ wel, weh pulse width floating start delay time floating release delay time ____ rde pulse width _____ rsmp output delay time _____ rsmp hold time f 1 output delay time conditions fig. 15.11.1 in part 1 45 5 18 C 28 C 28 C 28 C 22 C 18 C 35 1 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) C 22 C 30 C 20 C 32 C 30 t d(weC f 1 ) t d(rdeC f 1 ) notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . min. 12 4 12 12 18 22 5 9 4 18 130 20 128 10 0 0 max. limits
electrical characteristics 7735 group users manual 15C8 15.9 memory expansion mode and microprocessor mode : with wa it 1 t h(aleCa) t d(weCdq) t d(anCrde) t h(weCdq) t su(aCale) address/data output a 0 /d 0 Ca 15 /d 15 (byte = l) a 0 /d 0 Ca 7 /d 7 (byte = h) t d(weC 1 ) t d(csCwe) t d(weC 1 ) t w(we) t d(rsmpCwe) x in 1 cs 0 Ccs 4 output wel output weh output rde output when external memory area is accessed with wait 1 (wait bit = 0 and wait selection bit = 1) t d(rdeC 1 ) memory expansion mode and microprocessor mode : t d(anCwe) ale output <> <> t w(h) t w(l) t f t r t c t h(aleCa) t h(weCcs) address output a 8 Ca 15 (byte = h) a 16 , a 17 address t w(ale) data t d(aCwe) data input d 0 Cd 15 (byte = l) d 0 Cd 7 (byte = h) rsmp output t d(aleCwe) t h(weCan) t d(rdeC 1 ) t h(rdeCcs) t d(csCrde) t h(rdeCan) t d(aleCrde) t pxz(rdeCdz) t pzx(rdeCdz) t d(aCrde) t su(dCrde) t h(rdeCd) t w(rde) t d(rsmpCrde) measuring conditions (cs 0 Ccs 4 , a 0 /d 0 Ca 15 /d 15 , a 16 , a 17 , ale, wel, weh, rde, rsmp) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v port pi output (i = 4C8) port pi input (i = 4C8) measuring conditions (port p4Cp8) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v t d(weCpiq) t su(pidCrde) t h(rdeCpid) address address t w(h) t w(l) t f t r t c address address address data t w(ale) t su(aCale) address t h( 1 Crsmp) t h( 1 Crsmp) address
electrical characteristics 7735 group users manual 15C9 symbol t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t d( f 1 Crsmp) 15.10 memory expansion mode and microprocessor mode : with w ait 0 15.10 memory expansion mode and microprocessor mode : with w ait 0 timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. t c t w(h) t w(l) t r t f t su(dCrde) t h(rdeCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 40 15 15 32 0 parameter max. 8 8 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: when the main clock division selection bit = 1, the minimu m value of tc = 80 ns. 3: when the main clock division selection bit = 1, values of tw (h) /tc and tw (l) /tc must be set to values from 0.45 through 0.55. switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits data formula (min.) 3 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) C 33 C 33 C 45 C 22 C 23 C 35 C 25 C 30 parameter chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time ____ ____ wel, weh pulse width floating start delay time floating release delay time ____ rde pulse width _____ rsmp output delay time _____ rsmp hold time f 1 output delay time 45 5 18 1 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) conditions fig. 15.11.1 in part 1 C 22 C 30 C 20 C 32 C 30 t d(weC f 1 ) t d(rdeC f 1 ) notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 . max. min. 87 4 87 75 18 57 45 15 10 18 130 20 128 10 0 0
electrical characteristics 7735 group users manual 15C10 15.10 memory expansion mode and microprocessor mode : with w ait 0 t d(weCdq) t d(weCpiq) t d(anCrde) t su(aCale) address/data output a 0 /d 0 Ca 15 /d 15 (byte = l) a 0 /d 0 Ca 7 /d 7 (byte = h) t d(csCwe) t d(weC 1 ) t w(we) t d(rsmpCwe) x in 1 cs 0 Ccs 4 output wel output weh output rde output when external memory area is accessed with wait 0 (wait bit = 0 and wait selection bit = 0) memory expansion mode and microprocessor mode : t d(anCwe) ale output <> <> t w(h) t w(l) t f t r t c t h(weCcs) address output a 8 Ca 15 (byte = h) a 16 , a 17 t w(ale) address data t d(aCwe) data input d 0 Cd 15 (byte = l) d 0 Cd 7 (byte = h) rsmp output t d(aleCwe) t h(weCan) t d(rdeC 1 ) t h(rdeCcs) t d(csCrde) t h(rdeCan) t d(aleCrde) t pxz(rdeCdz) t pzx(rdeCdz) t d(aCrde) t su(dCrde) t h(rdeCd) t w(rde) t d(rsmpCrde) measuring conditions (cs 0 Ccs 4 , a 0 /d 0 Ca 15 /d 15 , a 16 , a 17 , ale, wel, weh, rde, rsmp ) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v port pi output (i = 4C8) port pi input (i = 4C8) measuring conditions (ports p4Cp8) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v t su(pidCrde) t h(rdeCpid) address address t h(weCdq) t w(h) t w(l) t f t r t c data data address t w(ale) t h(aleCa) t su(aCale) address t h(aleCa) t h( 1 Crsmp) t h( 1 Crsmp) 1 ) 1 ) t d(weC t d(rdeC
chapter 16 chapter 16 standard characteristics 16.1 standard characteristics
standard characteristics 7735 group users manual 16C2 concerning chapter 16. standard characteristics, the 7735 group is the same as the 7733 group. therefore, for this chapter, refer to part 1: ? 16 standard characteristics (part 1)
chapter 17 chapter 17 applications 17.1 memory expansion 17.2 serial i/o 17.3 watchdog timer 17.4 power saving 17.5 timer b
applications 7735 group users manual 17C2 17.1 memory expansion concerning chapter 17. applications, the 7735 group differs from the 7733 group in the following sections. therefore, only the differences are described in this chapter: ? 17.1 memory expansion ? 17.4 power saving the following sections of the 7735 group are the same as those of the 7733 group. therefore, for these sections, refer to part 1: ? 17.2 serial i/o (page 17-28 in part 1) ? 17.3 watchdog timer (page 17-41 in part 1) ? 17.5 timer b (page 17-54 in part 1) 17.1 memory expansion memory ? i/o expansion examples of the m37735mhbxxxfp are described below. ? for functions and operations of pins used in memory ? i/o expansion, refer to chapter 12. connecting external devices. ? for timing characteristics, refer to chapter 15. electrical characteristics. 17.1.1 memory expansion model memory expansion to the external is available in the memory expansion or microprocessor mode. in the m37735mhbxxxfp, the desired memory expansion model can be selected from two models listed in table 17.1.1. this selection depends on the level of the external data bus width selection signal (byte). (1) 8-bit external data bus model the external data bus is 8 bits wide and the accessible area can be expanded up to 1 mbytes. the low-order 8 bits of the external address bus (a 7 to a 0 ) are multiplexed with the external data bus. therefore, one 8-bit address latch is necessary in order to latch a 7 to a 0 . (2) 16-bit external data bus model the external data bus is 16 bits wide and the accessible area can be expanded up to 1 mbytes. the low-order 16 bits of the external address bus (a 15 to a 0 ) are multiplexed with the external data bus. therefore, two 8-bit address latches are necessary in order to latch a 7 to a 0 and a 15 to a 8 .
applications 7735 group users manual 17C3 17.1 memory expansion table 17.1.1 memory expansion models external data bus byte m37735mhbxxxfp byte m37735mhbxxxfp 8 bits wide byte = ? 16 bits wide byte = ? a 0 to a 15+n d 0 to d 7 8 16 + n e (n 2) d q latch latch latch e a 0 to a 15+n d 0 to d 15 8 16 n 16 + n d q e d q p0 p1 p2 ale ale p0 p1 p2 8 8 n 8 (n 2) h for functions and operations of pins used in memory expansion, refer to chapter 12. connecting external devices. for timing characteristics, refer to chapter 15. electrical characteristics. h in memory expansion, the address bus can be expanded up to 18 bits wide. accordingly, be sure to strengthen the 7735 groups vss line on the system. (refer to section appendix 8. countermeasure examples against noise. )
applications 7735 group users manual 17C4 17.1.2 calculation ways for timing when expanding memory, use a memory of which specifications satisfy the following timing requirements: address access time (t a(ad) ) and data setup time for writing data (t su(d) ). calculation ways for t a(ad) and t su(d) are described below. address access time of external memory [t a(ad) ] t a(ad) = t d(a-rde) + t w(rde) C t su(d-rde) C (address decode time ] 1 + address latch delay time ] 2 ) address decode time ] 1 : time necessary for validating a chip select signal after an address is decoded address latch delay time ] 2 : delay time necessary for latching an address data setup time of external memory for writing data [t su(d) ] t su(d) = t w(we) C t d(we-dq) table 17.1.2 lists the calculation formulas and constants for each parameter in the above formulas. figure 17.1.1 shows bus timing diagrams. table 17.1.2 calculation formulas and constants for each parameter (unit: ns) software wait wait bit wait selection bit t d(a-rde) t w(rde) t w(we) t su(d-rde) t d(we-dq) wait 1 0 1 wait 0 0 0 C 32 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) C 28 3 5 10 9 2 ? f(f 2 ) C 45 4 5 10 9 2 ? f(f 2 ) C 30 4 5 10 9 2 ? f(f 2 ) C 30 C 30 2 5 10 9 2 ? f(f 2 ) 32 45 wait bit: bit 2 at address 5e 16 wait selection bit: bit 0 at address 5f 16 note: the above is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0. no wait 1 0 or 1 17.1 memory expansion
applications 7735 group users manual 17C5 fig. 17.1.1 bus timing diagrams ale high-order address t d(an-rde) t d(an-rde) t su(a-ale) t d(ale-rde) t su(d-rde) t w(rde) port p0 (a 16, a 17 ) port p1 (a 8 to a 15 ) port p2 (a 0 /d 0 to a 7 /d 7 ) data t d(we-dq) high-order address t w(ale) aaaaaa aaaaaa aaaaaa t a(ad) t su(d) rde wel, weh t w(we) cs 4 to cs 0 t d(cs-rde) t d(cs-we) data (odd address) ale low-order address high-order address t d(an-rde) t su(a-ale) t su(a-ale) t d(ale-rde) t su(d-rde) t w(rde) port p0 (a 16, a 17 ) port p2 (a 0 /d 0 to a 7 /d 7 ) data (even address) t d(we-dq) high-order address t w(ale) aaaaaa aaaaaa t a(ad) t su(d) rde wel, weh t w(we) cs 4 to cs 0 t d(cs-rde) t d(cs-we) aaaaaa aaaaaa aaaaaa port p1 (a 8 /d 8 to a 15 /d 15 ) t su(d-rde) t d(we-dq) external memory? output data when byte = ??(external data bus = 16 bits wide) when byte = ??(external data bus = 8 bits wide) : specifications of the 7735 group (the others are specifications of external memory.) when data is written when data is read middle-order address middle-order address when data is written when data is read external memory? output data low-order address low-order address low-order address middle-order address middle-order address external memory? output data 17.1 memory expansion
applications 7735 group user? manual 17? figure 17.1.2 shows the relationship between t a(ad) , t su(d) and the system clock frequency. for t a(ad) in figure 17.1.2, an address decode time and an address latch delay time are not considered. the actual t a(ad) is a value obtained by subtracting the above times from the value shown in fig.17.1.2. data setup time t su(d) [mhz] [ns] 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 100 200 300 400 500 175 147 91 496 425 369 325 288 258 232 210 191 175 160 147 135 125 115 106 98 91 85 210 125 106 78 67 58 50 42 36 30 25 20 15 11 8 5 [ mhz] [ns] 7 8 9 591 10 11 12 13 14 15 16 17 18 19 20 21 135 22 125 23 24 25 0 100 200 283 300 400 500 600 700 766 800 900 1000 668 527 241 47 4 180 158 138 463 533 408 362 241 208 891 429 391 357 328 302 279 259 224 209 195 182 171 622 324 292 265 241 220 202 185 171 158 146 116 108 336 122 108 95 84 74 65 58 50 44 38 33 28 no wait wait 1 is valid. wait 0 is valid. address access time t a(ad) h system clock (main clock) frequency f(x in ) h address decode time and address latch delay time are not considered. no wait system clock (main clock) frequency f(x in ) wait 1 or wait 0 is valid. fig. 17.1.2 relationship between ta (ad) , tsu (d) and f(x in ) 17.1 memory expansion
applications 7735 group users manual 17C7 17.1.3 points in memory expansion (1) timing for reading data figure 17.1.3 shows the timing at which data is read from an external memory. when data is read, the external data bus enters a floating state and reads data from an external memory. the floating state of the external data bus is retained from when an interval of t pxz(rde-dz) ____ has passed after signal rdes falling edge until an interval of t pzx(rde-dz) has passed after signal ____ rdes rising edge. t pxz(rde-dz) is a constant which is independent of f(x in ); t pzx(rde-dz) is a constant which is dependent on f(x in ). table 17.1.3 lists the value of t pxz(rde-dz) and the calculation formula for t pzx(rde-dz) . note that the external data bus is multiplexed with the external address bus. therefore, when reading data, it is necessary to consider timing to avoid collision between data being read-in and an address which is output preceding or following the data. (refer to (3) precautions on memory expansion. ) fig. 17.1.3 timing at which data is read from external memory t en (oe) address address t pzx (rde-dz) t su (d-rde) t a (oe) t a (ce) , t a (s) t df , t dis (oe) h 2 h 3 t w(rde) data t pxz (rde-dz) t en (ce) , t en (s) external memory data output h 1 this is applied when the external data bus = 16 bits wide (byte = ??. external memory output enable signal (read signal) oe rde external memory chip select signals ce, s h 2 when the external memory? specifications are smaller than t pxz (rde-dz) , there is a possibility that the tail of an address collides with the head of data. ? refer to ?3) precautions on memory expansion. h 3 when the external memory? specifications are greater than t pzx (rde-dz) , there is a possibility that the tail of data collides with the head of an address. ? refer to ?3) precautions on memory expansion. address output a 0 / d 0 to a 7 /d 7 a 8 /d 8 to a 15 /d 15 h 1 : specifications of the 7735 group (the others are specifications of external memory.) 17.1 memory expansion
applications 7735 group users manual 17C8 table 17.1.3 value of t pxz(rde-dz) and calculation formula for t pzx(rde-dz) (unit: ns) wait 0 0 0 wait 1 0 1 5 1 5 10 9 2 ? f(f 2 ) C 20 software wait wait bit wait selection bit t pxz(rde-dz) t pzx(rde-dz) no wait 1 0 or 1 wait bit: bit 2 at address 5e 16 wait selection bit: bit 0 at address 5f 16 note: the above is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0. 17.1 memory expansion
applications 7735 group users manual 17C9 (2) timing for writing data figure 17.1.4 shows the timing for writing data to an external memory. when data is written, the data is output from when an interval of t d ( we-dq ) has passed after signal ____ ____ ____ ____ wel/wehs falling edge until an interval of t h ( we-dq ) has passed after signal wel/wehs rising edge. t d ( we-dq ) is a constant which is independent of f(x in ); t h ( we-dq ) is a constant which is dependent on f(x in ). table 17.1.4 lists the value of t d ( we-dq ) and the calculation formula for t h ( we-dq ). make sure that the data output timing for writing data satisfies the following specifications of the external memory: data setup time (t su ( d )) and data hold time (t h ( d )) for writing data. fig. 17.1.4 timing at which data is written to external memory table 17.1.4 value of t d(we-dq) and calculation formula for t h(we-dq) (unit: ns) wait 0 0 0 wait 1 0 1 45 C 22 1 5 10 9 2 ? f(f 2 ) no wait 1 0 or 1 wait bit: bit 2 at address 5e 16 wait selection bit: bit 0 at address 5f 16 note: the above is applied when the system clock selection bit (bit 3 at address 6c 16 ) = 0. software wait wait bit wait selection bit t d ( we-dq ) t h ( we-dq ) external memory write signals w, we external memory chip select signals ce, s (the others are specifications of external memory.) : specifications of the 7735 group h this is applied when the external data bus = 16 bits wide (byte = ??). wel, weh address and data output h a 0 /d 0 to a 7 /d 7 a 8 / d 8 to a 15 /d 15 t su (d) t h (d) address data address t w(we) t h (we-dq) t d (we-dq) 17.1 memory expansion
applications 7735 group users manual 17C10 (3) precautions on memory expansion when specifications of the 7735 group do not match those of an external memory as described in the following to a , some considerations about the circuit are necessary: when using an external memory which requires a long address access time (t a(ad) ) when using an external memory which outputs data within an interval of t pxz(rde-dz) after signal ____ rdes falling edge a when using an external memory which outputs data for more than an interval of t pzx(rde-dz) ____ after signal rdes rising edge when using an external memory which requires a long address access time (t a(ad) ) when an external memory requires a long address access time (t a(ad) ) which does not satisfy the 7735 groups t su(d-rde), try to lower f(x in ) or extend a bus cycle by inserting a wait. there are two methods for insertion of a wait: the software wait and the ready function. for the software wait, refer to section 12.2 software wait ; for the ready function, refer to section 12.3 ready function. l wait 1 (software wait) ____ ____ ____ insert a wait equivalent to one cycle of clock f 1 while signal rde / wel / weh is at l-level. l wait 0 (software wait) ____ ____ ____ insert a wait equivalent to one cycle of clock f 1 while signal rde / wel / weh is at h- and l- levels. l ready function insert a wait in an arbitrary duration. figure 17.1.5 shows a ready generating circuit example (with no wait). in figure 17.1.5, when ____ f(x in ) > 20.7 mhz, the setup time for the rdy input (t su(rdy- f 1 ) ) is insufficient. in this case, refer to the ready generating circuit example (with wait 1) shown in figure 17.1.6. in figure 17.1.6, t su(rdy- f 1 ) is satisfied when f(x in ) 25 mhz. note that a wait generated by the ready function is also valid for the access to the internal area. therefore, in figures 17.1.5 and 17.1.6, areas where the wait _____ is inserted are specified by using signals rsmp and cs 0 . for circuits where the software wait is used, refer to figures 17.1.2 to 17.1.5. 17.1 memory expansion
applica tions 7735 group users manual 17C11 17.1 memory expansion fig. 17.1.5 ready generating circuit example (with no wait) m37735mhbxxxfp cs 0 rdy ac32 cs 0 rsmp 1 rde cs 0 rsmp rdy t d(rde- 1 ) t d(rsmp-rde) t c t su(rdy- 1 ) h wait generated by the ready function is inserted only to an area where accessed by signal cs 2 . circuit conditions: f (x in ) 21.3 mhz, no wait, propagation delay time of ac32 (max.: 8.5 ns) h condition to satisfy the relationship of t su ( rdy- 1 ) 3 55 ns is t c +t d(rsmp-rde) 3 63.5 ns. accordingly, when f(x in ) 21.3 mhz, this example satisfies the relationship of t su ( rdy- 1 ) 3 55 ns. : wait generated by the ready function 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) 2 f(x cin ) or
applica tions 7735 group user? manual 17?2 17.1 memory expansion fig. 17.1.6 ready generating circuit example (with wait 1) wait generated by the ready function is inserted only to an area where accessed by signal cs 2. m37735mhbxxxfp t h( 1 -rdy) t su(rdy- 1 ) cs 0 rdy hc32 cs 0 rsmp h t d(rde- 1 ) propagation delay time of hc32 rde rdy 1 cs 0 rsmp t d(rsmp-rde) : wait generated by the ready function : software wait h make sure that the propagation delay time is within (when f(x in ) = 25 mhz, 75 ns). 3 5 10 f(x in ) + t d ( rsmp?de ) ?t su(rdy 1 ) 9 circuit conditions: f(x in ) 25 mhz, wait 1 is valid, 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) 2 f(x cin ) or
applica tions 7735 group users manual 17C13 17.1 memory expansion when using an external memory which outputs data within an i nterval of t pxz(rde-dz) after signal ____ rdes falling edge when there is a possibility that the tail of an address coll ides with the head of data because the ____ external memory outputs data within an interval of t pxz(rde-dz) after signal rdes falling edge, delay ____ only the signal rde s front falling edge and realize the relationship of t pxz(rde-dz) -d < t en(oe) . in this ___ ____ case, the falling edge of the read signal ( oe ) for the memory, which is generated from signal rde , is delayed. (refer to figure 17.1.7. ) fig. 17.1.7 timing example when data output is delayed external memory output enable signal (read signal) address output external memory data output t pxz(rde-dz) rde oe d address address data t en ( oe ) t a ( oe ) when t en(oe) t pxz(rde-dz) (= 5 ns), make sure that signal rdes falling edge precedes signal oes falling edge (refer to d) and the relationship of t pxz(red-dz) -d t en(oe) is realized. note:
applications 7735 group users manual 17C14 a when using an external memory which outputs data for more than an interval of t pzx(rde-dz) ____ after signal rde s rising edge when there is a possibility that the tail of data collides with the head of an address because the ____ external memory outputs the data for more than an interval of t pzx(rde-dz) after signal rdes rising edge, try to carry out the following: l by using bus buffers and others, delete the tail of data which is output from the memory. l use a memory which is made by mitsubishi electric corporation and can be connected without bus buffers. figures 17.1.8 to 17.1.11 show bus buffer usage examples and the corresponding timing diagrams. table 17.1.5 lists memories which can be connected without bus buffers (made by mitsubishi electric corporation). the reason why these memories do not need buffers is that timing parameters t df or t dis(oe) is guaranteed. (make sure that the read signal rises within 5 ns after signal ____ rdes rising edge.) table 17.1.5 memories which can be connected without bus buffers (made by mitsubishi electric corporation) 17.1 memory expansion memory m5m27c256ak-85, -10, -12, -15 m5m27c512ak-10, -12, -15 m5m27c100k-12, -15 m5m27c101k-12, -15 m5m27c102k-12, -15 m5m27c201k, jk-10, -12, -15 m5m27c202k, jk-10, -12, -15 m5m27c256ap, fp, vp, rv-12, -15 m5m27c512ap, fp-15 m5m27c100p-15 m5m27c101p, fp, j, vp, rv-15 m5m27c102p, fp, j, vp, rv-15 m5m27c201p, fp, j, vp, rv-12, -15 m5m27c202p, fp, j, vp, rv-12, -15 m5m28f101p, fp, j, vp, rv-10, -12, -15 m5m28f102fp, j, vp, rv-10, -12, -15 m5m5256cp, fp, kp, vp, rv-55ll, -55xl, -70ll, -70xl, -85ll, -85xl, -10ll, -10xl m5m5278cp, fp, j-20, -20l m5m5278cp, fp, j-25, -25l m5m5278dp, j-12 m5m5278dp, fp, j-15, -15l m5m5278dp, fp, j-20, -20l type usage condition t df /t dis(oe) (max.) 8 ns 10 ns 6 ns 7 ns 8 ns 2 ? f(f 2 ) 20 mhz 2 ? f(f 2 ) 25 mhz eprom one time prom frash memory sram note: specifications of the above memories are available if a comment t df/ t dis = 15 ns, microcomputer and kit is added. 15 ns (when guaranteed as kit) ( note )
applica tions 7735 group users manual 17C15 17.1 memory expansion fig. 17.1.8 bus buffer usage example (1) f(x cin ) dir f245 byte a 8 /d 8 to a 15 /d 15 e dq oc als573 oc dir ba e dq oc als573 ale a 16 , a 17 address bus m37735mhbxxxfp oc ba rde weh f11 rd wo we x in x out f245 h 1 h 1 a 0 /d 0 to a 0 /d 7 cnv ss wel h 2 25 mhz data bus (even) data bus (odd) h 1, h 2 make sure that the following relationships are satisfied: l the sum of output disable time of h 1 and propagation delay time of h 2 is 20 ns or less. l the sum of output enable time of h 1 and propagation delay time of h 2 is 5 ns or more. circuit conditions: wait 1 is valid, 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) 2 , or
applications 7735 group users manual 17C16 17.1 memory expansion rde oc 5 (max.) 128 (min.) 20 (min.) f11 (t phl ) f11 (t plh ) d aa f245 (t phz /t plz ) weh, wel 130 (min.) f11 (t plh ) d aa d f245 (t phl /t plh ) f245 (t phz /t plz ) f245 (t pzh /t pzl ) oc 45 (max.) a 8 /d 8 to a 15 /d 15 a 0 /d 0 to a 7 /d 7 a 8 /d 8 to a 15 /d 15 a 0 /d 0 to a 7 /d 7 data output (b) from external memory data output (a) to external memory (unit: ns) fig. 17.1.9 timing diagram for bus buffer usage example (1)
applica tions 7735 group users manual 17C17 17.1 memory expansion fig. 17.1.10 bus buffer u sage example (2) ( when a memory which requires a long data hold time f o r writing is connected ) dir als245a byte 16 mhz e d q oc als573 oc dir a b e dq oc als573 ale a 16 , a 17 oc a b 1d 1q 1t 2d 2q 2t 1 f74 f04 x in x out als245a a 8 /d 8 to a 15 /d 15 m37735mhbxxxfp a 0 /d 0 to a 7 /d 7 h 2 cnv ss h 2 rde weh rd wo we wel f32 f11 h 1 data bus (even) data bus (odd) address bus these circuits make the rising edge of the write signal earlier by 1/2 1 , so that the write hold time is extended. h 1 make sure that the propagation delay time is 20 ns or le ss. circuit conditions: wait 1 is valid, 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) f(x cin ) or 2 h 1, h 2 make sure that the following relationships are satisfied: l the sum of propagation delay time of h 1 and output disable time of h 2 is 42.5 ns or less. l the sum of propagation delay time of h 1 and output enable time of h 2 is 5 ns or more.
applica tions 7735 group users manual 17C18 17.1 memory expansion fig. 17.1.11 timing diagram for bus buffer usage example (2) a 8 /d 8 to a 15 /d 15 a 0 /d 0 to a 7 /d 7 data output b from external memory 5 (max.) 42.5 (min.) d a als245a (t phz /t plz ) oc als245a (t pzh /t pzl ) d a d f32(t plh ) als245a (t phz /t plz ) a 8 /d 8 to a 15 /d 15 a 0 /d 0 to a 7 /d 7 data output a to external memory wo, we 2q 1q 1 wel, weh 45 (max.) als245a (t phl /t plh ) 220(min.) 218(min.) rde f11 (t phl ) f11 (t plh ) oc f04 (t phl )+f74 (t plh ) f11(t plh ) (unit: ns) write hold time a
applica tions 7735 group users manual 17C19 17.1.4 memory expansion example figure 17.1.12 shows a memory expansion example (with one 12 8-kbyte rom and two 32-kbyte srams, microprocessor mode). figure 17.1.13 shows the corresponding timing diagram. 17.1 memory expansion byte cnv ss 25 mhz x in x out m37735mhbxxxfp data bus ac573 dq e rd d0 to d15 wo m5m27c102k-15 d 0 to d 15 oe a 0 to a 15 ce a1 to a16 s s a 0 to a 14 a 0 to a 14 dq 1 to dq 8 dq 1 to dq 8 oe w oe w a1 to a15 a1 to a15 d0 to d7 m5m5256p-15 d8 to d15 we address bus a 16 a 0 /d 0 to a 7 /d 7 ale rde weh h wel cs 1 cs 2 data bus (even) data bus (odd) 0000 16 0080 16 087f 16 8000 16 1ffff 1 40000 16 4ffff 16 external rom area (m5m27c102k-15) sfr area internal ram area external ram area (m5m5256p-15 5 2) memory map not used not used a 8 /d 8 to a 15 /d 15 ac573 dq e h 2 circuit conditions: wait 0 is valid, 1 = 2 , f(x in ) 8 , f(x in ) 16 , f(x in ) f(x cin ) h make sure that the propagation delay time is 33 ns or less. or fig. 17.1.12 rom and sram expansion example
applications 7735 group users manual 17C20 17.1 memory expansion fig. 17.1.13 timing diagram for rom and sram expansion example 128 (min.) 75(min.) 5 (max.) ta (a), ta (ad) tsu (d-rde) ta (s) ta (oe) a a 130 (min.) wel, weh, w rde, oe 20 (min.) a 0 / d 0 to a 15 / d 15 a d a a 16 a ce, s, cs 1 , cs 2 address output (a 0 to a 15 ) to external memory ac573 ( t phl ) a 0 / d 0 to a 15 / d 15 aa d 45 (max.) 75(min.) s, cs 2 tsu (d) external memory data output (unit: ns) 15 (max.) (guaranteed as kit.)
applications 7735 group users manual 17C21 17.1.5 i/o expansion example i/o expansion is realized with the memory-mapped method. the method and points in i/o expansion are the same as those in memory expansion. figure 17.1.15 shows a port expansion example using the m5m81c55p-2. in this example, the m5m81c55p- 2 is connected to the external data bus and programmable i/o ports expand by 22 bits. a reset signal for __ an external device is supplied from port p4 3 and io/m is supplied from port p4 4 . note that, when f(x in ) > 10 mhz, bus buffer als245a or others is necessary. 17.1 memory expansion fig. 17.1.14 port expansion example where m5m81c55p-2 is used cnvss byte a 0 /d 0 to a 7 /d 7 ale m37735mhbxxxfp wel circuit condition: wait 0 is valid. ce ad 0 to ad 7 port c port b port a m5m81c55p-2 wr p4 4 10 mhz x in x out i/o rde io/m ale rd cs 1 p4 3 reset
applications 7735 group users manual 17C22 17.4 power saving concerning section 17.4 power saving, the 7735 group differs from the 7733 group in the following: ? bit 3 of the oscillation circuit control register 1 (address 6f 16 ) must be fixed to 0. ? external bus pins functions for ports p0 to p3 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 17.4 power saving (page 17-44 in part 1)
chapter 18 chapter 18 low voltage version 18.1 performance overview 18.2 pin configuration 18.3 functional description 18.4 electrical characteristics 18.5 standard characteristics 18.6 applications
low volt age version 7735 group users manual 18-2 18.1 performance overview concerning chapter 18. low voltage version, the 7735 group differs from the 7733 group in the following sections. therefore, only the differences are desc ribed in this chapter: ? 18.1 performance overview ? 18.2 pin configuration ? 18.3 functional description ? 18.4 electrical characteristics ? 18.6 applications the following section is the same as that of the 7733 group. therefore, refer to part 1: ? 18.5 standard characteristics ( page 18-27 in part 1 ) 18.1 performance overview concerning section 18.1 performance overview, the 7735 gro up differs from the 7733 group in the following: ? description of the memory expansion in table 18.1.1 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 18.1 performance overview (page 18-3 in part 1.) table 18.1.1 m37735mhlxxxhp performance overview items memory expansion performance possible (maximum of 1 mbytes)
low vol t age version 7735 group users manual 18-3 18.2 pin configuration 18.2 pin configuration figure 18.2.1 shows the m37735mhlxxxhp pin configuration. fig. 18.2.1 m37735mhlxxxhp pin configuration (top view) p3 2 / al e p3 1 / we h p3 3 / hl da x ou t e/ rde cnv ss r eset p4 0 / ho l d 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p8 6 / r x d 1 p8 7 / t x d 1 p0 0 / cs 0 p0 1 / cs 1 p0 2 / cs 2 p0 3 / cs 3 p0 4 / cs 4 p0 5 / rs m p p0 6 / a 16 p0 7 / a 17 p1 0 / a 8 / d 8 p1 1 / a 9 / d 9 p1 2 / a 10 / d 10 p1 3 / a 11 / d 11 p1 4 / a 12 / d 12 p1 5 / a 13 / d 13 p1 6 / a 14 / d 14 p1 7 / a 15 / d 15 p2 0 / a 0 / d 0 p2 1 / a 1 / d 1 60 59 58 7 5 74 73 72 71 69 68 67 66 65 70 80 79 78 77 76 64 63 62 61 30 26 27 28 29 31 32 33 34 35 36 21 23 22 24 25 37 38 39 40 p4 1 / rdy p4 2 / 1 byt e x i n v ss p3 0 / we l p2 7 / a 7 / d 7 p2 6 / a 6 / d 6 p2 5 / a 5 / d 5 p2 4 / a 4 / d 4 p2 3 / a 3 / d 3 p2 2 / a 2 / d 2 p6 6 / tb 1 i n p6 5 / tb 0 i n p6 4 / i nt 2 p6 3 / i nt 1 p6 2 / i nt 0 p6 1 / ta 4 i n p6 0 / ta 4 ou t p5 7 / ta 3 i n / ki 3 p5 6 / ta 3 ou t / ki 2 p5 5 / ta 2 i n / ki 1 p5 4 / ta 2 ou t / ki 0 p5 3 / ta 1 i n p5 2 / ta 1 ou t p5 1 / ta 0 in p5 0 / ta 0 ou t p4 7 p8 5 / cl k 1 p8 4 / ct s 1 / rt s 1 p8 3 / t x d 0 p8 2 / r x d 0 / cl k s 0 p8 1 / cl k 0 p8 0 / ct s 0 / rt s 0 / cl k s 1 v cc av cc v re f av ss v ss p7 7 / an 7 / x ci n p7 6 / an 6 / x co ut p7 5 / an 5 / ad tr g / tx d 2 p7 4 / an 4 / rx d 2 p7 3 / an 3 / cl k 2 p7 2 / an 2 / ct s 2 p7 1 / an 1 p7 0 / an 0 p6 7 / tb 2 i n / sub m 37735m h l xxxh p p4 3 p4 4 p4 5 p4 6 1 2 3 4 5 outline 80p6d-a
low voltage version 7735 group users manual 18-4 18.3 functional description the m37735mhlxxxhp has the same functions as the m37735mhbxxxfp except for the power-on reset conditions. for power-on reset conditions, refer to section 18.3.1 power-on reset conditions in part 1. for the other functions, refer to the following: l part 1. 7733 group ? 4. interrupts ? 5. key input interrupt function ? 6. timer a ? 7. timer b ? 8. serial i/o ? 9. a-d converter l part 2. 7735 group ? 2. central processing unit (cpu) ? 3. programmable i/o ports ? 10. watchdog timer ? 11. stop and wait modes ? 12. connecting external devices ? 13. reset ? 14. clock generating circuit 18.3 functional description
low vol t age version 7735 group users manual 18-5 18.4.6 ready and hold timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. 18.4 electrical characteristics concerning section 18.4 electrical characteristic, the 773 5 group differs from the 7733 group in the following sections: ? 18.4.6 ready and hold ? 18.4.8 memory expansion mode and microprocessor mode : with no wait ? 18.4.9 memory expansion mode and microprocessor mode : with wait 1 ? 18.4.10 memory expansion mode and microprocessor mode : with wait 0 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 18.4 electrical characteristics (page 18-7 in part 1) 18.4 electrical characteristics limits t su(rdyC f 1 ) t su(holdC f 1 ) t h( f 1 Crdy) t h( f 1 Chold) max. ns ns ns ns min. parameter symbol unit 80 80 0 0 ____ rdy input setup time _____ hold input setup time ____ rdy input hold time _____ hold input hold time note: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. t d( f 1 Chlda) ns min. max. 120 limits unit conditions parameter symbol _____ hlda output delay time fig. 18.4.1 switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz, unless otherwise noted)
low volt age version 7735 group users manual 18-6 18.4 electrical characteristics 1 with no wait 1 with wait rdy input ready rde, wel, weh output rde, wel, weh output rdy input t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) measuring conditions ? v cc = 2.7 to 5.5 v ? input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 hold input hlda output t h( 1 Chold) t d( 1 Chlda) t su(holdC 1 ) hold t d( 1 Chlda)
low vol t age version 7735 group users manual 18-7 limits symbol t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( f 1 Crsmp) t d(weC f 1 ) t d(rdeC f 1 ) t d( f 1 Chlda) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) parameter chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time ____ ____ wel, weh pulse width floating start delay time floating release delay time ____ rde pulse width _____ rsmp output delay time _____ rsmp hold time f 1 output delay time _____ hlda output delay time 18.4.8 memory expansion mode and microprocessor mode : with no wait timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz, unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns data formula (min.) C 63 C 63 C 63 C 43 C 43 C 73 conditions fig. 18.4.1 t c t w(h) t w(l) t r t f t su(dCrde) t h(rdeCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 83 33 33 80 0 parameter max. 15 15 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: when the main clock division selection bit = 1, the minimu m value of t c = 166 ns. 3: when the main clock division selection bit = 1, values of t w (h) /t c and t w (l) /t c must be set to values from 0.45 through 0.55. 90 10 30 120 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) C 43 C 35 C 30 C 38 C 58 note: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 in part 1. max. min. 20 4 20 20 40 40 10 9 4 40 131 53 128 25 0 0 18.4 electrical characteristics
low volt age version 7735 group users manual 18-8 t h(weCdq) t su(aCale) address/data output a 0 /d 0 Ca 15 /d 15 (byte = l) a 0 /d 0 Ca 7 /d 7 (byte = h) t d(weC 1 ) t d(csCwe) t d(weC 1 ) t w(we) t d(rsmpCwe) x in 1 cs 0 Ccs 4 output wel output weh output rde output with no wait (wait bit = 1) t d(rdeC 1 ) memory expansion mode and microprocessor mode : t d(anCwe) ale output <> <> t w(h) t w(l) t f t r t c t h(aleCa) t w(h) t w(l) t f t r t c t h(weCcs) address output a 8 Ca 15 (byte = h) a 16 , a 17 t w(ale) t d(aCwe) t d(weCdq) data input d 0 Cd 15 (byte = l) d 0 Cd 7 (byte = h) rsmp output t d(aleCwe) t h(weCan) t d(rdeC 1 ) t h(rdeCcs) t d(csCrde) t h(rdeCan) t d(anCrde) t pzx(rdeCdz) t d(aCrde) t su(dCrde) t h(rdeCd) t d(rsmpCrde) measuring conditions (cs 0 Ccs 4 , a 0 /d 0 Ca 15 /d 15 , a 16 , a 17 , ale, wel, weh, rde, rsmp ) ?v cc = 2.7C5.5 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.16 v cc , v ih = 0.5 v cc port pi output (i = 4C8) port pi input (i = 4C8) measuring conditions (ports p4Cp8) ?v cc = 2.7C5.5 v ?input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v t d(weCpiq) t su(pidCrde) t h(rdeCpid) t su(aCale) t w(ale) t h(aleCa) t d(aleCrde) t w(rde) address address address address data address data address address data t pxz(rdeCdz) 1 Crsmp) t h( 1 Crsmp) t h( 18.4 electrical characteristics
low vol t age version 7735 group users manual 18-9 symbol t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( f 1 Crsmp) t d(weC f 1 ) t d(rdeC f 1 ) t d( f 1 Chlda) 1 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 18.4.9 memory expansion mode and microprocessor mode : with wait 1 timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz, unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits data formula (min.) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) t c t w(h) t w(l) t r t f t su(dCrde) t h(rdeCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 83 33 33 80 0 parameter max. 15 15 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: when the main clock division selection bit = 1, the minimu m value of t c = 166 ns. 3: when the main clock division selection bit = 1, values of t w (h) /t c and t w (l) /t c must be set to values from 0.45 through 0.55. parameter chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time ____ ____ wel, weh pulse width floating start delay time floating release delay time ____ rde pulse width _____ rsmp output delay time _____ rsmp hold time f 1 output delay time _____ hlda output delay time 90 10 30 120 1 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) note: f(f 2 ) represents the clock f 2 frequency. for the relationship with the main clock and sub clock, refe r to table 14.3.1 in part 1. C 43 C 35 C 30 C 38 C 58 C 63 C 63 C 63 C 43 C 43 C 73 conditions fig. 18.4.1 max. min. 20 4 20 20 40 40 10 9 4 40 298 53 295 25 0 0 18.4 electrical characteristics
low volt age version 7735 group users manual 18-10 t h(aleCa) t d(weCdq) t d(anCrde) t h(weCdq) t su(aCale) address/data output a 0 /d 0 Ca 15 /d 15 (byte = l) a 0 /d 0 Ca 7 /d 7 (byte = h) t d(weC 1 ) t d(csCwe) t d(weC 1 ) t w(we) t d(rsmpCwe) x in 1 cs 0 Ccs 4 output wel output weh output rde output when external memory area is accessed with wait 1 (wait bit = 0 and wait selection bit = 1) t d(rdeC 1 ) memory expansion mode and microprocessor mode : t d(anCwe) ale output <> <> t w(h) t w(l) t f t r t c t h(aleCa) t h(weCcs) address output a 8 Ca 15 (byte = h) a 16 , a 17 t w(ale) t d(aCwe) data input d 0 Cd 15 (byte = l) d 0 Cd 7 (byte = h) rsmp output t d(aleCwe) t h(weCan) t d(rdeC 1 ) t h(rdeCcs) t d(csCrde) t h(rdeCan) t d(aleCrde) t pxz(rdeCdz) t pzx(rdeCdz) t d(aCrde) t su(dCrde) t h(rdeCd) t w(rde) t d(rsmpCrde) measuring conditions (cs 0 Ccs 4 , a 0 /d 0 Ca 15 /d 15 , a 16 , a 17 , ale, wel, weh, rde, rs mp) ?v cc = 2.7C5.5 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input il = 0.16 v cc , v ih = 0.5 v cc port pi output (i = 4C8) port pi input (i = 4C8) measuring conditions (ports p4Cp8) ?v cc = 2.7C5.5 v ?input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v t d(weCpiq) t su(pidCrde) t h(rdeCpid) t w(h) t w(l) t f t r t c t w(ale) t su(aCale) address address address address address data address address address data 1 Crsmp) t h( 1 Crsmp) t h( 18.4 electrical characteristics : v
low vol t age version 7735 group users manual 18-11 1 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 18.4.10 memory expansion mode and microprocessor mode : with wait 0 timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or les s, unless otherwise noted. switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz, unless otherwise noted) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits data formula (min.) parameter chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale puls e width address output setup time address hold time ale output delay time data output delay time data hold time ____ ____ wel, weh pulse width floating start delay time floating release delay time ____ rde pulse width _____ rsmp output delay time _____ rsmp hold time f 1 output delay time _____ hlda output delay time t c t w(h) t w(l) t r t f t su(dCrde) t h(rdeCd) min. ns ns ns ns ns ns ns limits unit external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time data input setup time data input hold time 83 33 33 80 0 parameter max. 15 15 symbol notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: when the main clock division selection bit = 1, the minimu m value of t c = 166 ns. 3: when the main clock division selection bit = 1, values of t w (h) /t c and t w (l) /t c must be set to values from 0.45 through 0.55. 1 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) C 43 C 35 C 30 C 38 C 58 C 68 C 68 C 88 C 43 C 43 C 73 C 43 C 43 symbol t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( f 1 Crsmp) t d(weC f 1 ) t d(rdeC f 1 ) t h( f 1 Chlda) conditions fig. 18.4.1 90 10 30 120 max. min. 182 4 182 162 40 123 93 40 40 40 298 53 295 25 0 0 18.4 electrical characteristics
low volt age version 7735 group users manual 18-12 t d(weCdq) t d(weCpiq) t d(anCrde) t su(aCale) address/data output a 0 /d 0 Ca 15 /d 15 (byte = l) a 0 /d 0 Ca 7 /d 7 (byte = h) t d(csCwe) t d(weC 1 ) t w(we) t d(rsmpCwe) x in 1 cs 0 Ccs 4 output wel output weh output rde output when external memory area is accessed with wait 0 (wait bit = 0 and wait selection bit = 0) memory expansion mode and microprocessor mode : t d(anCwe) ale output <> <> t w(h) t w(l) t f t r t c t h(weCcs) address output a 8 Ca 15 (byte = h) a 16 , a 17 t w(ale) t d(aCwe) data input d 0 Cd 15 (byte = l) d 0 Cd 7 (byte = h) rsmp output t d(aleCwe) t h(weCan) t d(rdeC 1 ) t h(rdeCcs) t d(csCrde) t h(rdeCan) t d(aleCrde) t pxz(rdeCdz) t d(aCrde) t su(dCrde) t h(rdeCd) t w(rde) t d(rsmpCrde) measuring conditions (cs 0 Ccs 4 , a 0 /d 0 Ca 15 /d 15 , a 16 , a 17 , ale, wel, weh, rde, rsmp ) ?v cc = 2.7C5.5 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input il = 0.16 v cc , v ih = 0.5 v cc port pi output (i = 4C8) port pi input (i = 4C8) measuring conditions (ports p4Cp8) ?v cc = 2.7C5.5 v ?input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v t su(pidCrde) t h(rdeCpid) t h(weCdq) t w(h) t w(l) t f t r t c t w(ale) t h(aleCa) t su(aCale) t h(aleCa) address address address data data address address data t pzx(rdeCdz) 1 ) t d(weC 1 ) t d(rdeC 1 Crsmp) t h( 1 Crsmp) t h( 18.4 electrical characteristics : v
low vol t age version 7735 group users manual 18-13 18.6 applications some application examples of connecting external memorys for the low voltage version are described below. for the basic description of the memory expansion, refer to chapter 17. applications. applications shown here are just examples. modify the desire d application to suit the users need and make sufficient evaluations before actually using it. 18.6.1 memory expansion the following items of the 7735 groups low voltage version are the same as section 17.1 memory expansion in part 1, but a part of the caluculation way and constants for each p arameter is different: ?memory expansion model ?caluculation way for address access time of external memory ?bus timing ?memory expansion way address access time of external memory t a(ad) t a(ad) = t d(a-rde) + t w(rde) C t su(d-rde) C (address decode time ] 1 + address latch delay time ] 2 ) address decode time ] 1 : time necessary for validating a chip select signal after an address is decoded address latch delay time ] 2 : time necessary for latching an address data setup time of external memory for writing data t su(d) t su(d) = t w(we) C t d(weCdq) table 18.6.1 lists the caluculation formulas and constants f or each parameter of the low voltage version. figure 18.6.1 shows the relationship between t a(ad) and 2 ? f(f 2 ). figure 18.6.2 shows the relationship between t su(d) and 2 ? f(f 2 ). table 18.6.1 caluculation formulas and constants for each pa rameter (unit : ns) wait 1 0 1 wait 0 0 0 no wait 1 0 or 1 4 5 10 9 2 ? f(f 2 ) 80 90 wait bit : bit 2 at address 5e 16 wait selection bit : bit 0 at address 5f 16 note: this is applied to the case where the system clock selectio n bit (bit 3 at address 6c 16 ) = 0. C 63 C 38 C 35 C 35 C 38 C 88 3 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) software wait wait bit wait selection bit t d(a-rde) t w(rde) t w(we) t su(d-rde) t d(we-dq) 2 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 18.6 applications
mhz] low voltage version 7735 group user? manual 18-14 fig. 18.6.2 relationship between t su(d) and 2 f(f 2 ) fig. 18.6.1 relationship between t a(ad) and 2 f(f 2 ) 18.6 applications [ [ns] 2 3 4 5 6 7 8 9 10 11 12 152 0 500 1000 1500 2000 2500 3000 3500 3294 2127 1194 960 794 669 571 430 377 2319 1485 1069 819 652 533 235 1319 569 247 194 69 819 319 119 91 273 494 1544 319 374 444 419 no wait wait 1 is valid. wait 0 is valid. address access time ta (ad) external clock input frequency 2 f(f 2 ) ] address decode time and address latch delay time are not idd [mhz] [ns] 2 3 4 5 6 7 8 9 10 11 12 0 500 1000 1500 2000 208 41 541 875 675 541 1875 1208 319 275 238 875 275 208 160 125 97 75 56 375 446 375 no wait wait 1 or wait 0 is valid. external clock input frequency 2?(f 2 ) data setup time tsu (d)
low vol t age version 7735 group users manual 18-15 18.6.2 memory expansion example figure 18.6.3 shows a memory expansion example and figure 18 .6.4 shows the corresponding timing diagram. in this example, an atmel companys eprom (at27lv256r) is us ed as the external rom. fig. 18.6.3 memory expansion example x in x out m37735mhlxxxhp byte data bus h c573 dq e rd d0 to d7 at27lv256r-15di d 0 to d 7 oe a 0 to a 14 ce a0 to a14 s 1 a 0 to a 16 dq 1 to dq 8 oe w a0 to a16 d0 to d7 m5m51008afp-15vll wr address bus a 0 /d 0 to a 7 /d 7 ale rde cnv ss wel cs 1 cs 2 0000 16 0080 16 087f 16 8000 16 ffff 16 40000 16 5ffff 16 external rom area (at27lv256r-15di) sfr area internal ram area external ram area (m5m51008afp-15vll) memory map not used not used a 8 to a 16 10 mhz h circuit conditions : wait 1 h make sure that the propagation delay time is 85 ns (max.) or less. 1 = , , , or 2 f(x in ) 8 f(x in ) 16 f(x in ) 2 f(x cin ) supply voltage : vcc = 3.0 to 5.5 v (can operate with no wait when f(x in ) 8.0 mhz.) 18.6 applications
low volt age version 7735 group users manual 18-16 18.6 applications fig. 18.6.4 timing diagram rde, oe 295 (min.) t su( d-rde) 298 (min.) (unit : ns) wel, w 20 (min.) ce, s 1 , 4 (min.) cs 2 , s 1 20 (min.) a 8 to a 16 a a a 0 / d 0 to a 7 / d 7 a a 90 (min.) a extermal memory data output a d 10 (max.) t a(a), t acc t a(s1) ,t ce t a(oe) ,t oe hc573 ( t phl/plh) a 8 to a 16 a a 0 / d 0 to a 7 / d 7 53 (min.) t dis(oe) ,t df t dis(s1) a cs 1 , cs 2 t su(d) l at writing at reading a d
low vol t age version 7735 group users manual 18-17 18.6 applications 18.6.3 ready generating circuit example when validating wait only for a certain area (for example, rom area) in figure 18.6.3, use the ready function. figure 18.6.5 shows a ready generating circuit example. m37735mhlxxxhp cs 0 rdy ac32 cs 0 rsmp 1 rde cs 0 rsmp rdy td (rde- 1 ) td (rsmp-rde) tc tsu (rdy- 1 ) ] wait generated by the ready function is inserted only to an area where accessed by signal cs 0 . circuit conditions : f(x in ) 12 mhz, no wait, propagation delay time of ac32 (max. : 28 ns) ] condition to satisfy the relationship t t c+ t d(rsmp-rde) 3 108 ns accordingly, when f (x in ) 12 mhz, this example satisfies the relationship t : wait generated by the ready function 1 = , , , or 2 f(x in ) 8 f(x in ) 16 f(x in ) 2 f(x cin ) su(rdy- 1 ) 3 80 ns is su(rdy- 1 ) 3 80 ns. fig. 18.6.5 ready generating circuit example
low voltage version 7735 group users manual 18-18 memo 18.6 applications
chapter 19 chapter 19 built-in prom version 19.1 eprom mode 19.2 usage precaution
built-in prom version 7735 group users manual 19-2 concerning chapter 19. built-in prom version, the 7735 group differs from the 7733 group in the following section. therefore, only the differences are described in this chapter: ? 19.1 eprom mode the following section of the 7735 group is the same as that of the 7733 group. therefore, for this section, refer to part 1: ? 19.2 usage precaution (page 19-10 in part 1) 19.1 eprom mode concerning section 19.1 eprom mode, the 7735 group differs from the 7733 group in the following: ? figures 19.1.1 and 19.1.2 ? bit 3 of the oscillation circuit control register 1 (address 6f 16 ) is 1 at reset. after reset, this bit must be cleared to 0 in the single-chip mode. this writing must be performed with the procedure shown in figure 14.3.4. the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 19.1 eprom mode (page 19-3 in part 1) 19.1 eprom mode
buil t -in prom version 7735 group users manual 19-3 19.1 eprom mode fig. 19.1.1 pin connections in eprom mode (m37735ehbfp) 66 p8 2 /rxd 0 /clks 0 67 p8 1 /clk 0 1 p6 6 /tb1 in 2 p6 5 /tb0 in 3 p6 4 /int 2 4 p6 3 /int 1 5 p6 2 /int 0 6 p6 1 /ta4 in 7 p6 0 /ta4 out 8 p4 1 /rdy 64 p8 4 /cts 1 /rts 1 63 p8 5 /clk 1 62 p8 6 /rxd 1 61 p8 7 /txd 1 60 p0 0 /cs 0 59 p0 1 /cs 1 58 p0 2 /cs 2 57 p0 3 /cs 3 9 10 p5 7 /ta3 in /ki 3 11 p5 6 /ta3 out /ki 2 12 p5 5 /ta2 in /ki 1 13 p5 4 /ta2 out /ki 0 14 p5 3 /ta1 in 15 p5 2 /ta1 out 16 p5 1 /ta0 in 17 p5 0 /ta0 out 18 p4 7 19 p4 6 20 p4 5 21 p4 4 22 p4 3 23 p4 2 / 1 24 56 p0 4 /cs 4 55 p0 5 /rsmp 54 p0 6 /a 16 53 p0 7 /a 17 52 p1 0 /a 8 /d 8 51 p1 1 /a 9 /d 9 50 p1 2 /a 10 /d 10 49 p1 3 /a 11 /d 11 48 p1 4 /a 12 /d 12 47 p1 5 /a 13 /d 13 46 p1 6 /a 14 /d 14 45 p1 7 /a 15 /d 15 44 p2 0 /a 0 /d 0 43 p2 1 /a 1 /d 1 42 p2 2 /a 2 /d 2 41 p2 3 /a 3 /d 3 80 p7 1 /an 1 79 p7 2 /an 2 /cts 2 78 p7 3 /an 3 /clk 2 77 p7 4 /an 4 /rxd 2 76 p7 5 /an 5 /ad trg /txd 2 75 p7 6 /an 6 /x cout 74 p7 7 /an 7 /x cin 73 v ss 72 av ss 71 v ref 70 av cc 69 v cc 68 p8 0 /cts 0 /rts 0 /clks 1 65 p8 3 /txd 0 39 p2 5 /a 5 /d 5 38 p2 6 /a 6 /d 6 25 p4 0 /hold 26 byte 27 cnv ss 28 reset 29 x in 30 x out 31 e/rde 32 v ss 33 p3 3 /hlda 34 p3 2 /ale 35 p3 1 /weh 36 p3 0 /wel 37 p2 7 /a 7 /d 7 40 p2 4 /a 4 /d 4 m37735ehbfp a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 9 a 10 a 11 a 12 a 13 a 14 d 0 d 1 d 2 d 3 oe ce v pp d 4 d 5 d 6 d 7 v ss * a 15 pgm v cc p7 0 /an 0 p6 7 /tb2 in / sub a 16 outline 80p6n-a * : connect these pins to a resonator or an oscillator. : eprom pin.
built -in prom version 7735 group users manual 19-4 19.1 eprom mode fig. 19.1.2 pin connections in eprom mode (m37735ehlhp) x out p3 2 /ale p3 0 /wel p3 1 /weh d 2 a 14 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 4 3 2 5 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 /cs 0 p0 1 /cs 1 p0 2 /cs 2 p0 3 /cs 3 p0 4 /cs 4 p0 5 /rsmp p0 6 /a 16 p0 7 /a 17 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 p1 7 /a 15 /d 15 p2 0 /a 0 d 0 p2 1 /a 1 /d 1 60 59 58 75 74 73 72 71 69 68 67 66 65 70 80 79 78 77 76 64 63 62 61 30 26 27 28 29 31 32 33 34 35 36 21 23 22 24 25 37 38 39 40 p4 2 / 1 p4 1 /rdy p4 0 /hold byte cnv ss reset x in e/rde v ss p3 3 /hlda p2 7 /a 7 /d 7 p2 6 /a 6 /d 6 p2 5 /a 5 /d 5 p2 4 /a 4 /d 4 p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 p5 6 /ta3 out /ki 2 p5 5 /ta2 in /ki 1 p5 4 /ta2 out /ki 0 p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out p4 7 p8 5 /clk 1 p8 4 /cts 1 /rts 1 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 p7 0 /an 0 p6 7 /tb2 in / sub m 37735e h lh p p4 3 p4 4 p4 5 p4 6 p2 3 /a 3 /d 3 p2 2 /a 2 /d 2 v cc a 15 a 13 a 12 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 d 0 d 1 d 7 d 6 d 5 d 4 d 3 v pp v ss * ce pgm oe a 16 outline 80p6d-a * : connect these pins to a resonator or an oscillator. : eprom pin.
chapter 20 chapter 20 external rom version 20.1 performance overview 20.2 pin configuration 20.3 pin description 20.4 block description 20.5 memory allocation 20.6 processor modes 20.7 timer a 20.8 reset 20.9 electrical characteristics 20.10 low voltage version
external rom version 7735 group users manual 20C2 the external rom version can operate only in the microprocessor mode. functions of the external rom version differ from those of the mask rom version in the following. therefore, only the differences are described in this chapter: ?memory allocation ?operation is available only in the microprocessor mode ?rom area change function is not available. ?timer a has the pulse output port mode. ?power source current and current consumption for the other functions, refer to the following: ? chapters 4. interrupts to 9. a-d converter in part 1 ? chapter 2. central processing unit (cpu) in part 2 ? chapter 3. programmable i/o port in part 2 ? chapters 10. watchdog timer to 17. applications in part 2 h for product expansion information of the 7735 group, contact the appropriate office, as listed in contact addresses for further information.
external rom version 7735 group users manual 20C3 20.1 performance overview 20.1 performance overview performance overview of the external rom version differs from that of the mask rom version in the following: memory size and current consumption. for the other items, refer to section 1.1 performance overview in part 2. table 20.1.1 lists the m37735s4bfps performance overview. table 20.1.1 m37735s4bfps performance overview items memory size current consumption ram performance 2048 bytes 57 mw (when f(x in ) = 25-mhz external square wave input, vcc = 5 v, and the main clock is the system clock, typ.) 300 m w (when f(x cin ) = 32 khz, vcc = 5 v, the sub clock is the system clock, and the main clock is stopped, typ.)
external rom version 7735 group users manual 20C4 20.2 pin configuration 20.2 pin configuration figure 20.2.1 shows the m37735s4bfp pin configuration. note: for the low voltage version, refer to section 20.10 low voltage version. fig. 20.2.1 m37735s4bfp pin configuration (top view) 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 /rtp1 3 p5 6 /ta3 out /ki 2 /rtp1 2 p5 5 /ta2 in /ki 1 /rtp1 1 p5 4 /ta2 out /ki 0 /rtp1 0 p5 3 /ta1 in /rtp0 3 p5 2 /ta1 out /rtp0 2 p5 1 /ta0 in /rtp0 1 p5 0 /ta0 out /rtp0 0 hold byte cnv ss reset x in x out rde v ss (p3 3 )hlda (p3 2 )ale (p3 1 )weh (p3 0 )wel (p2 7 )a 7 /d 7 (p2 6 )a 6 /d 6 (p2 5 )a 5 /d 5 (p2 4 )a 4 /d 4 p7 4 /an 4 /r x d 2 p7 5 /an 5 /ad trg /t x d 2 p7 6 /an 6 /x cout p7 7 /an 7 /x cin v ss av ss v ref av cc v cc p8 0 /cts 0 /rts 0 /clks 1 p8 1 /clk 0 p8 2 /r x d 0 /clks 0 p8 3 /t x d 0 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 cs 0 (p0 0 ) cs 1 (p0 1 ) cs 2 (p0 2 ) cs 3 (p0 3 ) cs 4 (p0 4 ) rsmp(p0 5 ) a 16 (p0 6 ) a 17 (p0 7 ) a 8 /d 8 (p1 0 ) a 9 /d 9 (p1 1 ) a 10 /d 10 (p1 2 ) 1 4 3 2 5 6 7 8 9 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 outline 80p6n-a a 11 /d 11 (p1 3 ) a 12 /d 12 (p1 4 ) a 13 /d 13 (p1 5 ) a 14 /d 14 (p1 6 ) a 15 /d 15 (p1 7 ) a 0 /d 0 (p2 0 ) a 1 /d 1 (p2 1 ) a 2 /d 2 (p2 2 ) a 3 /d 3 (p2 3 ) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 m37735s4bfp 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 rdy p4 7 p4 6 p4 5 p4 4 p4 3 (p4 2 )/ 1 p7 1 /an 1 p7 2 /an 2 /cts 2 p7 3 /an 3 /clk 2 by setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pins level can be fixed in the stop or wait mode.
external rom version 7735 group users manual 20C5 functions to pin vcc, apply 5 v10% (when the main clock is the system clock) or 2.7 v to 5.5 v (when the sub- clock is the system clock). to pin vss, apply 0 v. connect to pin vcc. the microcomputer is reset when l level is input to this pin. pins x in and x out are the i/o pins of the clock generating circuit, respectively. connect these pins via a ceramic resonator or a quartz-crystal oscillator. when an external clock is used, the clock should be input to pin x in , and pin x out should be left open. ____ ____ this pin outputs read enable signal rde . rde s level is l in the data read period of the read cycle. input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. a 16-bit width is selected when the level is l, and an 8-bit width is selected when the level is h. power source input for the a-d converter. connect to pin vcc. power source input for the a-d converter. connect to pin vss. this is the reference voltage input pin for the a-d converter. ___ ___ _____ these pins respectively output signals cs 0 Ccs 4 , rsmp , and high-order 2 bits (a 16 , a 17 ) of address. ___ ___ l signals cs 0 Ccs 4 these signals are the chip-select signals. when the microcomputer accesses a certain area, the corresponding pin outputs l level. (refer to figure 12.1.3. ) _____ l signal rsmp this signal is the ready sampling signal and is used ____ to generate signal rdy for accessing the external memory area. l when the external data bus width = 8 bits (pin byte is at h level) addresss middle-order 8 bits (a 8 Ca 15 ) are output. l when the external bus width = 16 bits (pin byte pin is at l level) input/output of data (d 8 Cd 15 ) and output of addresss middle-order 8 bits (a 8 Ca 15 ) are performed with the time sharing system. name power source input cnvss reset input clock input clock output read enable output external data bus width selection input analog power source input reference voltage input chip select output, ready sampling output, address (high-order) output address (middle-order) output/data i/o 20.3 pin description 20.3 pin description tables 20.3.1 and 20.3.2 list the pin description. table 20.3.1 pin description (1) pin vcc, vss cnvss ______ reset x in x out ____ rde byte avcc avss v ref ____ cs 0 (p0 0 )C ____ cs 4 (p0 4 ), ______ rsmp (p0 5 ), a 16 (p0 6 ), a 17 (p0 7 ) a 8 /d 8 (p1 0 ) C a 15 /d 15 (p1 7 ) input/output input input input output output input input output i/o
external rom version 7735 group users manual 20C6 20.3 pin description table 20.3.2 pin description (2) input/output i/o output input input output i/o i/o i/o i/o i/o functions input/output of data (d 0 Cd 7 ) and output of addresss low-order 8 bits (a 0 Ca 7 ) are performed with the time sharing system. ____ ____ these pins respectively output signals wel , weh , ale, _____ and hlda . ____ ____ l signals wel, weh ____ signal wel is the write enable low signal. ____ signal weh is the write enable high signal. these signals levels are l in the data write period of the write cycle. the operations of these signals depend on the level of pin byte. (refer to table 12.1.1. ) l signal ale this signal is used to separate the multiplexed signal which consists of an address and data to the address and data. _____ l signal hlda this signal informs the external whether this microcomputer enters the hold state or not. _____ in hold state, pin hlda outputs l level. _____ the microcomputer is in hold state while pin hold s ____ input level is l and is in ready state while pin rdy s input level is l. the clock f 1 output can be stopped by software. (refer to chapter 14. clock generating circuit. ) p4 3 Cp4 7 function as i/o ports with the same functions as port p5. p5 is a cmos 8-bit i/o port and has an i/o direction register. each pin can be programmed for input or output. it can be programmed as i/o pins for timers a0Ca3, ___ ___ input pins ( ki 0 C ki 3 ) for the key input interrupt and output pins (rtp0 0 Crtp1 3 ) for the pulse output. p6 is an 8-bit i/o port with the same function as port p5 and can be programmed as i/o pins for timer a4, external interrupt input pins, and input pins for timers b0Cb2. p6 7 also functions as an output pin for the sub clock ( f sub ). p7 is an 8-bit i/o port with the same function as port p5 and can be programmed as analog input pins for the a-d converter. p7 6 and p7 7 can be programmed as i/o pins (x cout , x cin ) for the sub-clock (32 khz) oscillation circuit. when using p7 6 and p7 7 as pins x cout and x cin , connect a quartz-crystal oscillator between them. p7 2 Cp7 5 also function as uart2s i/o pins. p8 is an 8-bit i/o port with the same function as port p5 and can be programmed as serial i/os i/o pins. name address (low-order) output/data (low-order) i/o write enable low output, write enable high output, address latch enable output, hold acknowledge output hold request input, ready input, clock output, i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 pin a 0 /d 0 ( p2 0 ) Ca 7 /d 7 (p2 7 ) ____ wel (p3 0 ), ____ weh (p3 1 ), ale (p3 2 ), _____ hlda (p3 3 ) _____ hold , ____ rdy , f 1 (p4 2 ), p4 3 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7
external rom version 7735 group user? manual 20? 20.4 block description 20.4 block description figure 20.4.1 shows the m37735s4bfp block diagram. fig.20.4.1 m37735s4bfp block diagram x in x out reset v ref p8(8) p7(8) p5(8) p6(8) p4(5) cnvss byte av ss (0v) av cc (0v) v ss v cc x cin x cout 1 rdy hold hlda ale weh wel rde rsmp x cout x cin uart1 (9) uart0 (9) uart2 (9) clock input clock output reset input reference voltage input clock generating circuit data buffer db h (8) data buffer db l (8) instruction queue buffer q 0 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) data bank register dt(8) program counter pc(16) incrementer/decrementer(24) program bank register pg(8) input buffer register ib(16) direct page register dpr(16) stack pointer s(16) index register y(16) index register x(16) anthmetic logic unit(16) accumulator b(16) accumulator a(16) instruction register(8) data bus(even) data bus(odd) input/output port p8 input/output port p7 input/output port p6 input/output port p5 input/output port p4 watchdog timer external data bus width selection input timer tb1(16) timer tb2(16) address bus/ data bus timer tb0(16) timer ta1(16) timer ta2(16) timer ta3(16) timer ta4(16) timer ta0(16) ram 2048 bytes central processing unit (cpu) incrementer(24) program address register pa(24) data address register da(24) address bus bus interface unit (biu) processor status register ps(11) a-d converter(10) address (18) / data (16) chip select
external rom version 7735 group users manual 20C8 20.5 memory allocation 20.5 memory allocation the internal areas memory allocation is described below. for details, refer to section 2.4 memory allocation in part 1. for the external area, refer to section 20.6 processor modes. figure 20.5.1 shows the m37735s4bfps memory map and figure 20.5.2 shows the sfr areas memory map.
external rom version 7735 group users manual 20C9 20.5 memory allocation fig. 20.5.1 m37735s4bfps memory map 01ffff 16 100000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 000800 16 00ffff 16 010000 16 000000 16 00007f 16 int 1 int 0 dbc reset 00ffd6 16 00fffe 16 0fffff 16 ( note ) timer a4 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 a-d/uart2 trans./rece. uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a3 timer a2 timer a1 timer a0 int 2 /key input watchdog timer brk instruction zero divide interrupt vector table peripheral device control registers (sfr) uart1 transmission uart0 transmission refer to figure 20.5.2. : external memory area for the 7735 group? microcomputers other than the m37735s4bfp, refer to section ?ppendix 1. 773 5 group memory allocation . h ?ram size: 2 kbytes note: banks 10 16 to ff 16 cannot be accessed.
these registers are used when outputting an arbitrary data in the stop or wait mode. external rom version 7735 group users manual 20C10 20.5 memory allocation fig. 20.5.2 sfr areas memory map uart 0 transmission interrupt control register uart 1 transmission interrupt control register int 2 /key input interrupt control register port p1 direction register ( note 3 ) uart 0 transmit/receive mode register uart 0 baud rate register (brg0) uart 0 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 0 transmission buffer register uart 1 transmit/receive control register 0 uart 1 transmit/receive mode register uart 1 baud rate register (brg1) uart 1 transmit/receive control register 1 uart 0 receive buffer register uart 1 transmission buffer register uart 1 receive buffer register port p0 register ( note 3 ) a-d register 0 a-d register 2 port p1 register ( note 3 ) port p0 direction register ( note 3 ) port p2 register ( note 3 ) port p3 register ( note 3 ) port p4 register ( note 3 ) port p5 register port p6 register port p7 register port p8 register a-d control register 0 a-d control register 1 a-d register 1 a-d register 3 a-d register 4 a-d register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002a 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 00000b 00000c 00000d 00000e 00000f 00000a 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f 00004b 00004c 00004d 00004e 00004f 00004a 000044 address (hexadecimal notation) address (hexadecimal notation) timer a1 register timer a4 register timer a2 register timer a3 register timer b0 register timer b1 register timer b2 register count start flag one-shot start flag up-down flag timer a0 register timer a0 mode register timer a1 mode register timer a2 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 watchdog timer register watchdog timer frequency selection flag a-d/uart2 trans./rece. interrupt control register uart 0 receive interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register processor mode register 1 oscillation circuit control register 1 serial transmit control register port function control register oscillation circuit control register 0 timer a3 mode register port p2 direction register ( note 3 ) port p3 direction register ( note 3 ) port p4 direction register ( note 3 ) port p5 direction register port p6 direction register port p7 direction register port p8 direction register pulse output data register 1 ( note 1 ) a-d register 6 a-d register 7 uart2 transmit/receive mode register uart2 baud rate register (brg2) uart2 transmission buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register waveform output mode register ( note 1 ) notes 1: memory map of the m37735s4bfp differs from that of the m3773 5mhbxxxfp in addresses 1c 16 , 1d 16 , 62 16 , and 63 16. 2 : writing to the reserved area is disabled. 3 : pulse output data register 0 ( note 1 ) reserved area (notes 1, 2) a-d control register 1
external rom version 7735 group users manual 20C11 20.6 processor modes 20.6 processor modes the m37735s4bfp can operate only in the microprocessor mode. for the processor mode, refer to the description of the microprocessor mode in section 2.5 processor modes in part 1. also, be sure to set as follows: ? connect pin cnvss to vcc. ? fix the processor mode bit to 10 2 . figure 20.6.1 shows the structure of the processor mode regi ster 0. fig. 20.6.1 structure of processor mode register 0 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits wait bit software reset bit interrupt priority detection time selection bits must be fixed to 0. this bit is ignored. (it may be 0 or 1.) 0 0 0 0 0 0 0 0: do not select. 0 1: do not select. 1 0: microprocessor mode 1 1: do not select. microcomputer is reset by setting this bit to 1. this bit is 0 at reading. 0 0: 7 cycles of 0 1: 4 cycles of 1 0: 2 cycles of 1 1: do not select. 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) represents that bits 2 to 7 are not used for setti ng the processor mode. b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw wo rw rw rw rw 0: software wait is inserted when accessing external area. 1: no software wait is inserted when accessing external area.
external rom version 7735 group users manual 20C12 20.7 timer a, 20.8 reset 20.7 timer a the timer a description of the m37735s4bfp is the same as that of the 7733 group. for timer a description of the m37735s4bfp, refer to the following: ? 6. timer a (page 6-2 in part 1) ? 20.7 timer a (page 20-12 in part 1) 20.8 reset the reset description of the m37735s4bfp differs from that of the mask rom version in the state immediately after reset. the state immediately after reset of the m37735s4bfp differs from that of the mask rom version in the following addresses: addresses 1c 16 , 1d 16 , 62 16 and 63 16 . figures 20.8.1 and 20.8.2 show the state of sfr area and internal ram area immediately after reset (1) and (4). figure 20.8.1 corresponds to figure 13.1.3 in part 1. figure 20.8.2 corresponds to figure 13.1.6 in part 1. for the other descriptions, refer to chapter 13. reset. ______ for the pin state while pin reset is at l level, refer to table 13.1.1 .
external rom version 7735 group users manual 20C13 20.8 reset fig. 20.8.1 state of sfr area and internal ram area immediat ely after reset (1) : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. 0 1 ? : always 0 at reading 0 0 : always undefined at reading : 0 immediately after reset. must be fixed to 0. 10 16 11 16 12 16 13 16 port p8 direction register 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 address port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register a-d control register 0 a-d control register 1 port p0 register port p1 register port p2 register port p3 register port p0 direction register port p1 direction register port p2 direction register port p3 direction register register name access characteristics state immediately after reset rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 00 16 00 16 ? ? 00 16 00 16 00 16 00 0 0 0 0 000 0 00 00 16 0 0 000 ? 00 11 b7 b0 b7 b0 n sfr area (addresses 0 16 to 7f 16 ) rw ? ? ? ? ? 00 16 ? ? ? h the contents of addresses 1c 16 and 1d 16 of the m37735s4bfp differ from those of the m37735mhbxxxfp. abbreviations which represent access characteristics rw rw ?? 0 ? ?? ? ? 00 16 ? ? ? ? ? pulse output data register 1 pulse output data register 0 ? ? ? ? ? ? wo wo h h : it is possible to read the bit state at reading. the writ ten value becomes valid. : it is possible to read the bit state at reading. the writ ten value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : not implemented. it is impossible to read the bit state. the written value becomes invalid. rw ro wo
external rom version 7735 group users manual 20C14 20.8 reset fig. 20.8.2 state of sfr area and internal ram area immediat ely after reset (4) 0 ro uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address oscillation circuit control register 0 serial transmit control register a-d / uart 2 trans./rece. interrupt control register uart0 transmission interrupt control register uart1 transmission interrupt control register int 2 /key input interrupt control register watchdog timer frequency selection flag register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw( h 2) rw rw rw rw b7 b0 wo rw rw rw rw rw rw rw rw rw rw state immediately after reset ? ? ? ? ? 0 00 0 ? 0 ? ( h 1) b7 b0 ? 0 0 0 0 0 00 0 00 00 00 0 00 0 port function control register uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register rw rw wo rw rw rw 00 0 0 0 1 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 0 0 0 0 00 0 0 00 0 0 00 0 ? ? ? 00 0 00 0 00 0 00 0 a value of fff 16 is set to the watchdog timer. (refer to chapter 10. watchdog timer in part 1. ) for access characteristics at address 6c 16 , also refer to figure 14.3.2 in part 1. the contents of addresses 62 16 and 63 16 of the m37735s4bfp differ from those of the m37735mhbxxxfp. do not wirte to address 63 16 . n internal ram area (m37735s4bfp: addresses 80 16 to 87f 16 ) l at hardware reset (not including the case where the stop or wait mode is te rminated)...undefined. l at software reset...retains the state immediately before res et . l when the stop or wait mode is terminated (when hardware reset is used)...retains the state immedia tely before the stp or wit instr uction is executed. ? rw 00 0 h 1 h 2 h 3 h 4 waveform output mode register h 3 (reserved area) h 4 uart 2 transmit/receive mode register uart 2 baud rate register (brg2) uart 2 transmission buffer register uart 2 transmit/receive control register 0 uart 2 transmit/receive control register 1 uart 2 receive buffer register oscillation circuit control register 1 00 rw ? 00 0 00 0 0 wo wo wo rw ro 1 00 0 rw rw ro ro 00 0 0 00 1 0 ro 00 0 00 0 ? rw ? ? 0 00 0 0 00 0 ? 0 rw rw rw 0 ? 0 00 ? 0
external rom version 7735 group users manual 20C15 20.9 electrical characteristics 20.9 electrical characteristics except for icc, the electrical characteristics of the m37735s4bfp are the same as those of the m37735mhbxxxfp in the microprocessor mode. for the others, refer to chapter 15. electrical characteristics. electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, unless otherwise noted) max. 22.8 3.2 20 120 10 1 20 limits vcc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 12.5 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 5v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 1.5625 mhz), f(x cin ) : stopped, in operating (note 1) vcc = 5v, f(x in ) = 25 mhz (square waveform), f(x cin ) = 32.768 khz, when the wit instruction is executed (note 2) vcc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) vcc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when the wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped unit measuring conditions symbol parameter icc power source current min. typ. 11.4 1.6 10 60 5 ma ma a a a a a external bus is operating, output pins are open, and the other pins are con- nected to vss. notes 1: this is applied when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output disable selection bit = 1. 2: this is applied when the main clock external input selection bit = 1 and the system clock stop selection bit at wait state = 1. 3: this is applied when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4: this is applied when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1.
external rom version 7735 group users manual 20C16 20.10 low voltage version 20.10 low voltage version differences from the m37735s4bfp are mainly described below. 20.10.1 performance overview the performance overview of the low voltage version differs from that of the m37735s4bfp in the following: memory size and current consumption. for the other items, refer to section 18.1 performance overview. table 20.10.1 shows the m37735s4lhps performance overview. items memory size current consumption performance 2048 bytes 10.8 mw (when f(x in ) = 12-mhz square wave input, vcc = 3 v, and the main clock is the system clock, typ.) 120 w (when f(x cin ) = 32 khz, vcc = 3 v, the sub clock is the system clock, and the main clock is stopped, typ.) table 20.10.1 m37735s4lhps performance overview ram
external rom version 7735 group users manual 20C17 20.10 low voltage version 20.10.2 pin configuration figure 20.10.1 shows the m37735s4lhp pin configuration. fig. 20.10.1 m37735s4lhp pin configuration (top view) (p3 2 )ale (p3 1 )weh (p3 3 )hlda x out rde cnv ss reset hold 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p8 6 /r x d 1 p8 7 /t x d 1 cs 0 (p0 0 ) cs 1 (p0 1 ) cs 2 (p0 2 ) cs 3 (p0 3 ) cs 4 (p0 4 ) rsmp(p0 5 ) a 16 (p0 6 ) a 17 (p0 7 ) a 8 /d 8 (p1 0 ) a 9 /d 9 (p1 1 ) a 10 /d 10 (p1 2 ) a 11 /d 11 (p1 3 ) a 12 /d 12 (p1 4 ) a 13 /d 13 (p1 5 ) a 14 /d 14 (p1 6 ) a 15 /d 15 (p1 7 ) a 0 /d 0 (p2 0 ) a 1 /d 1 (p2 1 ) 60 59 58 75 74 73 72 71 69 68 67 66 65 70 80 79 78 77 76 64 63 62 61 30 26 27 28 29 31 32 33 34 35 36 21 23 22 24 25 37 38 39 40 rdy (p4 2 )/ 1 byte x in v ss (p3 0 )wel (p2 7 )a 7 /d 7 (p2 6 )a 6 /d 6 (p2 5 )a 5 /d 5 (p2 4 )a 4 /d 4 (p2 3 )a 3 /d 3 (p2 2 )a 2 /d 2 p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in /ki 3 /rtp1 3 p5 6 /ta3 out /ki 2 /rtp1 2 p5 5 /ta2 in /ki 1 /rtp1 1 p5 4 /ta2 out /ki 0 /rtp1 0 p5 3 /ta1 in /rtp0 3 p5 2 /ta1 out /rtp0 2 p5 1 /ta0 in /rtp0 1 p5 0 /ta0 out /rtp0 0 p4 7 p8 5 /clk 1 p8 4 /cts 1 /rts 1 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg /txd 2 p7 4 /an 4 /rxd 2 p7 3 /an 3 /clk 2 p7 2 /an 2 /cts 2 p7 1 /an 1 p7 0 /an 0 p6 7 /tb2 in / sub m37735s4lhp p4 3 p4 4 p4 5 p4 6 1 2 3 4 5 outline 80p6d-a by setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pins level can be fixed in the stop or wait mode.
external rom version 7735 group users manual 20C18 20.10 low voltage version 20.10.3 functional description except for the power-on reset conditions, the m37735s4lhp has the same functions as the m37735s4bfp for the other functions, refer to the following: 4. interrupts to 9. a-d converter in part 1, 2. central processing unit (cpu) in part 2, 3. programmable i/o ports in part 2, and 10. watchdog timer to 17. applications in part 2. the power-on reset condition of the m37735s4lhp is the same as that of the m37735mhlxxxhp. for the power-on reset condition, refer to section 18.3 functional description in part 1. 20.10.4 electrical characteristics except for icc, the electrical characteristics of the m37735s4lhp are the same as those of the m37735mhlxxxhp in the microprocessor mode. for the others, refer to section 18.4 electrical characteristics in part 2 . limits vcc = 5 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 6 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 3 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 6 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 3 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 0.75 mhz), f(x cin ) : stopped, in operating (note 1) vcc = 3v, f(x in ) = 12 mhz (square waveform), f(x cin ) = 32.768 khz, when the wit instruction is executed (note 2) vcc = 3 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) vcc = 3 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when the wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped electrical characteristics (vcc= 5 v, vss = 0 v, ta = C40 to 85 c, unless otherwise noted) unit measuring conditions symbol parameter i cc power source current min. typ. 5.4 3.6 0.5 6 40 3 ma ma ma a a a a a max. 10.8 7.2 1.0 12 80 6 1 20 notes 1: this is applied when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output disable selection bit = 1. 2: this is applied when the main clock external input selection bit = 1 and the system clock stop bit at wait state = 1. 3: this is applied when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4: this is applied when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1. external bus is operating, output pins are open, and the other pins are connected to vss.
appendix appendix appendix 1. memory allocation of 7735 group appendix 2. memory allocation in sfr area appendix 3. control registers appendix 4. package outlines appendix 5. hexadecimal instruction code table appendix 6. machine instructions appendix 7. examples of handling unused pins appendix 8. countermeasure examples against noise appendix 9. q & a
appendix 7735 group users manual 21-2 concerning chapter appendix, the 7735 group differs from t he 7733 group in the following sections. therefore, only the differences are described in this chapte r: ? appendix 1. memory allocation of 7735 group ? appendix 2. memory allocation in sfr area ? appendix 3. control registers ? appendix 7. examples of handling unused pins note: the following sections of the 7735 group are the same as th ose of the 7733 group. therefore, for these sections, refer to part 1: ? appendix 4. package outlines ( page 21-38 in part 1 ) ? appendix 5. hexadecimal instruction code table ( page 21-41 in part 1 ) ? appendix 6. machine instructions ( page 21-44 in part 1 ) ? appendix 8. countermeasure examples against noise ( page 21-61 in part 1 ) ? appendix 9. q & a ( page 21-71 in part 1 )
appendix 7735 group user? manual 21-3 appendix 1. memory allocation of 7735 group 1. m37735mhbxxxfp, m37735ehbxxxfp, m37735ehbfs, m37735mhlxxx hp, m37735ehlxxxhp fig. 1 memory allocation of m37735mhbxxxfp, m37735ehbxxxfp, m37735ehbfs, m37735mhlxxxhp, m37735ehlxxxhp (1) appendix 1. memory allocation of 7735 group 0 1 ffff 16 100000 16 000000 16 00007f 16 000080 16 000f f f 16 ffffff 16 001000 16 0 0 ffff 16 010000 16 002000 16 000000 16 00007f 16 000080 16 000f f f 16 0 0 ffff 16 010000 16 0 1 ffff 16 ffffff 16 000000 16 00007f 16 i nt 1 i nt 0 db c r eset 0 0 ffd 6 16 0 0 fffe 16 0 fffff 16 sfr area internal ram area 3968 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 60 kbytes internal rom area 64 kbytes bank 2 16 (4 kbytes) a-d/uart2 trans./rece. uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input watchdog timer brk instruction zero divide interrupt vector table sfr area internal ram area 3968 bytes internal rom area 56 kbytes internal rom area 64k bytes peripheral device control registers (sfr) ?memory allocation selection bits (b2, b1, b0)=(0, 0, 0) ?rom size: 124 kbytes ?ram size: 3.9 kbytes ?memory allocation selection bits (b2, b1, b0)=(0, 0, 1) ?rom size: 120 kbytes ?ram size: 3.9 kbytes uart1 transmission uart0 transmission : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode notes 1: access to internal rom area is disabled in the microprocess or mode. ?.5 processor modes?in part 1 . ) 2 : in the 7735 group, banks 10 16 to ff 16 cannot be accessed. refer to appendix 2. bank 10 16 (refer to section
appendix 7735 group users manual 21-4 fig. 2 memory allocation of m37735mhbxxxfp, m37735ehbxxxfp, m37735ehbfs, m37735mhlxxxhp, m37735ehlxxxhp (2) appendix 1. memory allocation of 7735 group 00ffff 16 010000 16 uart1 transmission 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 001000 16 000000 16 00007f 16 000080 16 00087f 16 00ffff 16 010000 16 ffffff 16 000000 16 reset 00007f 16 00ffd6 16 00fffe 16 a-d/uart2 trans./rece. 020000 16 008000 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 60 kbytes bank 2 16 (29.9 kbytes) uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide interrupt vector table sfr area internal ram area 2048 bytes peripheral device control registers (sfr) : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode ?memory allocation selection bits (b2, b1, b0)=(0, 1, 0) ?rom size: 60 kbytes ?ram size: 2048 bytes ?memory allocation selection bits (b2, b1, b0)=(1, 0, 0) ?rom size: 32 kbytes ?ram size: 2048 bytes (1.9 kbytes) uart0 transmission refer to appendix 2. 02ffff 16 notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: banks 10 16 to ff 16 cannot be accessed in the 7735 group and in external bus mode b of the 7736 group. internal rom area 32 kbytes
appendix 7735 group users manual 21-5 appendix 1. memory allocation of 7735 group fig. 3 memory allocation of m37735mhbxxxfp, m37735ehbxxxfp, m37735ehbfs, m37735mhlxxxhp, m37735ehlxxxhp (3) 00ffff 16 010000 16 020000 16 uart1 transmission 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 00c000 16 000000 16 00007f 16 000080 16 000fff 16 00ffff 16 010000 16 ffffff 16 000000 16 reset 00007f 16 00ffd6 16 00fffe 16 a-d/uart2 trans./rece. 008000 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 16 kbytes bank 2 16 (28 kbytes) uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide interrupt vector table sfr area internal ram area 3968 bytes peripheral device control registers (sfr) : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode ?memory allocation selection bits (b2, b1, b0)=(1, 0, 1) ?rom size: 16 kbytes ?ram size: 2048 bytes ?memory allocation selection bits (b2, b1, b0)=(1, 1, 0) ?rom size: 96 kbytes ?ram size: 3968 bytes (45.9 kbytes) uart0 transmission refer to appendix 2. 02ffff 16 notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: banks 10 16 to ff 16 cannot be accessed in the 7735 group and in external bus mode b of the 7736 group. internal rom area 32 kbytes 001000 16 internal rom area 64 kbytes 01ffff 16
appendix 7735 group user s manual 21-6 2. m37735s4bfp, m37735s4lhp appendix 1. memory allocation of 7735 group fig. 4 memory allocation of m37735s4bfp, m37735s4lhp r eset db c i nt 0 i nt 1 ffffff 16 000000 16 00007f 16 000080 16 0 0 ffff 16 010000 16 0 1 ffff 16 000000 16 00007f 16 0 0 ffd 6 16 0 0 fffe 16 100000 16 0 fffff 16 timer a4 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank 10 16 a-d/uart2 trans./rece. uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a3 timer a2 timer a1 timer a0 int 2 /key input watchdog timer brk instruction zero divide interrupt vector table peripheral device control registers (sfr) uart1 transmission uart0 transmission refer to appendix. 2 : external memory area bank ff 16 notes 1: addresses 00ffd6 16 to 00ffff 16 are the interrupt vector table. be sure to set rom to this area. 2 : in the 7735 group, banks 10 16 to ff 16 cannot be accessed. 00087f 16
appendix 7735 group user s manual 21-7 appendix 2. memory allocation in sfr area concerning section appendix 2. memory allocation in sfr area, the 7735 group differs from the 7733 group in the following: ? address 6f 16 (refer to figure 8.) the other description is the same as that of the 7733 group. therefore, refer to part 1: ? appendix 2. memory allocation in sfr area (page 21-6 in part 1) appendix 2. memory allocation in sfr area
appendix 7735 group user s manual 21-8 fig. 8 memory allocation in sfr area (4) figure 8 differs from that of the 7733 group only in h 3. 0 ro uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address oscillation circuit control register 0 serial transmit control register a-d / uart 2 trans./rece. interrupt control register uart0 transmission interrupt control register uart1 transmission interrupt control register int 2 /key input interrupt control register watchdog timer frequency selection flag register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw( h 2) rw rw rw rw b7 b0 wo rw rw rw rw rw rw rw rw rw rw state immediately after reset ? ? ? ? ? 0 00 0 ? 0 ? ( h 1) b7 b0 ? 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 port function control register uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register rw rw wo rw rw rw 00 0 0 0 1 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 ? ? ? 00 0 0 0 0 00 0 0 0 0 a value of fff 16 is set to the watchdog timer. (refer to chapter 10. watchdog timer. ) for access characteristics at address 6c 16 , also refer to figure 14.3.2 in part 1. the state of bit 3 at address 6f 16 immediately after reset depends on the product. (refer to figure 14.3.3 in part 2 : refer to this part because bit 3 at address 6f 16 of the 7735 group differs from that of the 7733 group. fix this bit to 0 in the 7735 group. do not wirte to the reserved area. (refer to figure 20.8.1 for the m37733s4bfp, m37733s4lhp, m3 7735s4bfp, 37735s4lhp.) n internal ram area (m37735mhbxxxfp: addresses 80 16 to fff 16 ) at hardware reset (not including the case where the stop or wait mode is te rminated)...undefined. at software reset...retains the state immediately before res et . when the stop or wait mode is terminated (when the hardware reset is used)...retains the state imm ediately before the stp or wit instruction is executed. ? rw h 3 00 0 h 1 h 2 h 3 h 4 (reserved area) h 4 memory allocation control register uart 2 transmit/receive mode register uart 2 baud rate register (brg2) uart 2 transmission buffer register uart 2 transmit/receive control register 0 uart 2 transmit/receive control register 1 uart 2 receive buffer register oscillation circuit control register 1 rw 0 ? 0 00 0 rw ? 00 0 0 0 0 0 wo wo wo rw ro 1 00 0 rw ro ro 00 0 0 00 1 0 ro 00 0 00 0 ? rw ? ? 0 00 0 0 00 0 0 0 0 appendix 2. memory allocation in sfr area rw
appendix 7735 group user s manual 21-9 appendix 3. control registers concerning section appendix 3. control registers, the 7735 group differs from the 7733 group in the following: ? oscillation circuit control register 1 the other control registers are the same as those of the 773 3 group. therefore, for the other control registers, refer to part 1: ? appendix 3. control registers (page 21-10 in part 1) appendix 3. control registers
appendix 7735 group user s manual 21-10 oscillation circuit control register 1 2: because this bit is 1 at reset, clear this bit to 0 with the initial setting program after reset. 3: the case where data 01010101 2 is written with the procedure shown below is not included. 4: for the 7733 group, refer to figure 14.3.3 in part 1. bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to 0 in the one time prom and eprom versions (notes 1 and 2) . must be fixed to 0 (note 3) . clock prescaler reset bit 0 0 0 0 undefined 0 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input fro m the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown be low. by writing 1 to this bit, clock prescaler is initialized. rw 1 (note 4) 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. must be fixed to 0 in the mask rom and external rom versions (note 1) . (note 1) (note 1) (note 1) 0 write data 01010101 2 . ( ldm instruction) ? when writing to bits 0 to 3 write data 00000xxx 2 . ( ldm instruction) next instruction (b2 to b0 in the above figure) write data 80 16 . ( ldm instruction) ? when performing clock prescaler reset appendix 3. control registers
appendix 7735 group user s manual 21-11 appendix 7. examples of handling unused pins the following are examples of handling unused pins. these are, however, just examples. in actual use, make the necessary adaptations and properly evaluate performance according to the user s application. 1. in single-chip mode table 1 examples of handling unused pins in single-chip mode notes 1: when leaving these pins open after they are set to the outpu t mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these ports function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. for unused pins, use the shortest possible wiring (within 20 mm from the microcomputer s pins). 2: this is applied when an external clock is input to pin x in . pins p0 C p8 _ e x out ( note 2 ) avcc avss, v ref , byte handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins open aft er they are set to the output mode ( note 1 ). leave this pin open. connect this pin to pin vcc. connect these pins to pin vss. fig. 9 examples of handling unused pins in single-chip mode p0 C p8 avss v ref byte m37735mhbxxxfp vss avcc e x out left open when setting ports to input mode vcc p0 C p8 avss v ref byte m37735mhbxxxfp vss avcc e x out left open when setting ports to output mode left open vcc appendix 7. examples of handling unused pins
appendix 7735 group user s manual 21-12 2. in memory expansion mode table 2 examples of handling unused pins in memory expansion mode pins p4 2 C p4 7 , p5 C p8 ( note 5 ) _________ ________ ________ weh , wel , rde , _____ __________ hlda, cs 0 C cs 4 , rsmp x out ( note 4 ) _____ ____ hold , rdy avcc avss, v ref handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be en hanced when the contents of the above ports direction registers are set periodically. this is bec ause these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputer s pins). 3: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory exp ansion mode by software. therefore, a voltage level of this pin is undefined and the power sourc e current may increase while this pin functions as an input port. 4: this is applied when an external clock is input to pin x in . 5: set pin p4 2 / f 1 as pin p4 2 . (clock f 1 output is disabled.) and then, for this pin, do the same handling as that for pins p4 3 to p4 7 and p5 to p8. fig. 10 examples of handling unused pins in memory expansion mode p4 2 C p4 7 , p5 C p8 hold rdy m37735mhbxxxfp vcc vss avcc x out cs 0 C cs 4 p4 2 C p4 7 , p5 C p8 hold rdy vss avcc x out cs 0 C cs 4 vcc m37735mhbxxxfp when setting ports to input mode when setting ports to output mode left open left open left open left open left open avss v ref avss v ref weh wel rde hlda rsmp weh wel rde hlda rsmp appendix 7. examples of handling unused pins
appendix 7735 group user s manual 21-13 3. in microprocessor mode table 3 examples of handling unused pins in microprocessor m ode handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. pins p4 3 C p4 7 , p5 C p8 _________ ________ ________ weh , wel , rde _____ ___________ hlda , f 1 , cs 0 C cs 4 , rsmp x out ( note 4 ) _____ ____ hold , rdy av cc av ss , v ref notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputer s pins). 3: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the microproce ssor mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. 4: this is applied when an external clock is input to pin x in . fig. 11 examples of handling unused pins in microprocessor m ode p4 3 C p4 7 , p5 C p8 f 1 rsmp hold rdy m37735mhbxxxfp weh wel rde hlda vcc vss avcc x out cs 0 C cs 4 p4 3 C p4 7 , p5 C p8 f 1 rsmp hold rdy vss avcc x out cs 0 C cs 4 vcc m37735mhbxxxfp when setting ports to input mode when setting ports to output mode left open left open left open left open left open avss v ref avss v ref weh wel rde hlda appendix 7. examples of handling unused pins
appendix appendix 7. examples of handling unused pins 7735 group users manual 21C14 memo
part 3 part 3 7736 group chapter 1 overview chapter 2 central processing unit (cpu) chapter 3 programmable i/o ports chapter 4 interrupts chapter 5 key input interrupt function chapter 6 timer a chapter 7 timer b chapter 8 serial i/o chapter 9 a-d converter chapter 10 watchdog timer chapter 11 stop and wait modes chapter 12 connecting external devices chapter 13 reset chapter 14 clock generating circuit chapter 15 electrical characteristics chapter 16 standard characteristics chapter 17 applications chapter 18 low voltage version chapter 19 built-in prom version appendix
7736 group users manual 2 part 3 7736 group the differences between the 7736 group and the 7733 group are mainly described below. for the 7733 group, refer to part 1. 7733 group. for the 7735 group, refer to part 2. 7735 group. the 7736 group differs from the 7733/7735 group in the following: ? external bus mode in the memory expansion mode and the microprocessor mode (in the 7736 group, pin bsels level determines the external bus mode, which is a or b.) ? output port p9 and i/o port p10 (ports p9 and p10 are assigned only for the 7736 group.) ? pin assignment for the key input interrupt (in the 7736 group, the pins are assigned to pins p10 4 to p10 7 .) ? pin assignment for uart2 (in the 7736 group, the pins are assigned to pins p9 0 to p9 3 .) ? external rom version (in the 7736 group, there is no external rom version.) ? package (in the 7736 group, the 100-pin qfp is used.)
chapter 1 chapter 1 overview 1.1 performance overview 1.2 pin configuration 1.3 pin description 1.4 block diagram
overview 7736 group users manual 1C2 items programmable i/o ports output port memory expansion package 1.1 performance overview performance 8 bits 5 9 4 bits 5 1 8 bits 5 1 possible ? external bus mode a: maximum of 16 mbytes ? external bus mode b: maximum of 1 mbytes 100-pin plastic molded qfp ports p0Cp2, p4Cp8, p10 port p3 port p9 concerning chapter 1. overview, the 7736 group differs from the 7733 group in the following sections. therefore, only the differences are described in this chapter: ? 1.1 performance overview ? 1.2 pin configuration ? 1.3 pin description ? 1.4 block diagram 1.1 performance overview concerning section 1.1 performance overview, the 7736 group differs from the 7733 group in the following: ? description of the programmable i/o ports, memory expansion, and package in table 1.1.1 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 1.1 performance overview (page 1-3 in part 1) table 1.1.1 m37736mhbxxxgps performance overview
over view 7736 group users manual 1C3 fig. 1.2.1 m37736mhbxxxgp pin configuration (top view) p4 6 p4 5 p4 4 p4 3 p4 2 / 1 p4 7 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out p7 4 /an 4 p7 5 /an 5 /ad trg p7 6 /an 6 /x cout p7 7 /an 7 /x cin v ss av ss v ref av cc v cc p8 0 /cts 0 /rts 0 /clks 1 p8 1 /clk 0 p8 2 /r x d 0 /clks 0 p8 3 /t x d 0 p0 0 /a 0 /cs 0 p0 1 /a 1 /cs 1 p0 2 /a 2 /cs 2 p0 3 /a 3 /cs 3 p0 4 /a 4 /cs 4 p0 5 /a 5 /rsmp 1 4 3 2 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 89 88 87 86 85 90 outline 100p6s-a 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 m37736mhbxxxgp 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p10 7 /ki 3 p10 6 /ki 2 p10 5 /ki 1 p10 4 /ki 0 p10 3 p10 2 p10 1 p10 0 p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 p4 1 /rdy p4 0 /hold byte p0 6 /a 6 /a 16 p0 7 /a 7 /a 17 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 25 26 27 28 29 30 31 33 32 34 40 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 56 55 54 53 52 51 84 83 82 81 cnv ss bsel reset x in x out e/rde v ss v cc evl1 evl0 p3 3 /hlda p3 2 /ale p3 1 /bhe/weh p3 0 /r/w/wel p2 7 /a 23 /a 7 /d 7 p2 6 /a 22 /a 6 /d 6 p2 5 /a 21 /a 5 /d 5 p1 7 /a 15 /d 15 p2 0 /a 16 /a 0 /d 0 p2 1 /a 17 /a 1 /d 1 p2 2 /a 18 /a 2 /d 2 p2 3 /a 19 /a 3 /d 3 p2 4 /a 20 /a 4 /d 4 p8 7 /t x d 1 p9 0 /cts 2 p9 1 /clk 2 p9 2 /rxd 2 p9 3 /txd 2 p9 4 p9 5 p9 6 p9 7 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 1.2 pin configuration figure 1.2.1 shows the m37736mhbxxxgp pin configuration. note: for the low voltage version, refer to chapter 18. low voltage version. 1.2 pin configuration
overview 7736 group users manual 1C4 pin _ e bsel external bus modes CC a b CC a, b processor modes single-chip mode memory expansion or microprocessor mode single-chip mode memory expansion or microprocessor mode i/o output output output input input functions same as the 7733 group. _ this pin outputs internal enable signal e . ________ this pin outputs read enable signal rde . ________ rdes level is l in the data read period of the read cycle. the level of a signal which is input to this pin may be h or l. the signal which is input to this pin determines the external bus mode. when this signals level is h, external bus mode a is selected; when this signals level is l, external bus mode b is selected. name enable output bus select input 1.3 pin description concerning section 1.3 pin description, the 7736 group differs from the 7733 group in the following: ___ ? description of pins e and bsel in table 1.3.1 ? description of pins p0 0 Cp0 7 , p2 0 Cp2 7 and p3 0 Cp3 3 in tables 1.3.2 and 1.3.3 ? description of pins p5 0 Cp5 7 , p7 0 Cp7 7 , p9 0 Cp9 7 , p10 0 Cp10 7 , evl0 and evl1 in table 1.3.4 ? 1.3.1 examples of handling unused pins the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 1.3 pin description (page 1-5 in part 1) table 1.3.1 pin description (1) 1.3 pin description
over view 7736 group users manual 1C5 table 1.3.2 pin description (2) pin functions i/o name processor mode CC a b CC a b i/o port p0 i/o port p2 same as the 7733 group. addresss low-order 8 bits (a 0 Ca 7 ) are output. ____ these pins respectively output signals cs 0 C cs 4 , rsmp , and addresss high-order 2 bits (a 16 and a 17 ). l signals cs 0 C cs 4 these signals are the chip select signals. when the microcomputer accesses a certain area, the corresponding pin outputs l level. (refer to table 2.5.4. ) _____ l signal rsmp this signal is the ready sampling signal and ________ is used to generate signal rdy for accessing external memory area. same as the 7733 group. input/output of data (d 0 Cd 7 ) and output of addresss high-order 8 bits (a 16 Ca 23 ) are performed with the time sharing method. input/output of data (d 0 Cd 7 ) and output of addresss low-order 8 bits (a 0 Ca 7 ) are performed with the time sharing method. p0 0 Cp0 7 a 0 Ca 7 cs 0 Ccs 4 , _____ rsmp, a 16 , a 17 p2 0 Cp2 7 a 16 /d 0 C a 23 /d 7 a 0 /d 0 C a 7 /d 7 single-chip mode memory expansion or microprocessor mode single-chip mode memory expansion or microprocessor mode i/o output output i/o output output external bus mode 1.3 pin description
overview 7736 group users manual 1C6 CC a b i/o port p3 i/o output output same as the 7733 group. __ ____ these pins respectively output signals r/ w , bhe , _____ ale, and hlda . __ l signal r/ w this signal indicates the data bus state. when this signal level is h, a data bus is in the read state. when this signal level is l, a data bus is in the write state. ____ l signal bhe this signals level is l when the microcomputer accesses an odd address. l signal ale this signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. _____ l signal hlda this signal informs the external whether this microcomputer enters the hold state or not. _____ in hold state, pin hlda outputs l level. ________ ____ these pins respectively output signals wel , weh , _____ ale, and hlda . ________ _________ l signal wel , weh ____ signal wel is the write enable low signal. ____ signal weh is the write enable high signal. these signals levels are l in the data write period of the write cycle. the operations of these signals depend on the level of pin byte. (refer to table 12.1.1 in part 2. ) l signal ale this signal is the same as that in external bus mode a. _____ l signal hlda this signal is the same as that in external bus mode a. table 1.3.3 pin description (3) pin functions i/o name processor mode single-chip mode memory expansion or microprocessor mode external bus mode p3 0 Cp3 3 __ r/w, ____ bhe, ale, _____ hlda ____ wel, ____ weh, ale, _____ hlda 1.3 pin description
over view 7736 group users manual 1C7 table 1.3.4 pin description (4) pin functions i/o name processor mode external bus mode p5 0 Cp5 7 p7 0 Cp7 7 p9 0 Cp9 7 i/o i/o output CC a, b CC a, b CC a, b i/o port p5 i/o port p7 output port p9 p5 is an 8-bit i/o port with the same function as port p0 and can be programmed as i/o pins for timers a0Ca3. p7 is an 8-bit i/o port with the same function as port p0 and can be programmed as analog input pins for the a-d converter. p7 6 and p7 7 can be programmed as i/o pins (x cout , x cin ) for the sub-clock (32 khz) oscillation circuit. when using p7 6 and p7 7 as pins x cout and x cin , connect a quartz-crystal oscillator between them. when inputting an external clock, input the clock from pin x cin . p9 is an 8-bit output-only port. after reset, p9 enters a floating state. when data is written to the port p9 register, p9 starts outputting (note) . p9 0 Cp9 3 also function as uart2s i/o pins. p10 is an 8-bit i/o port with the same function as port p0. pins 10 4 C10 7 can be programmed as input pins (ki 0 Cki 3 ) for the key input interrupt. leave these pins open. single-chip mode memory expansion o r microprocessor mode single-chip mode memory expansion o r microprocessor mode single-chip mode memory expansion o r microprocessor mode single-chip mode memory expansion o r microprocessor mode single-chip mode memory expansion o r microprocessor mode p10 0 Cp10 7 evl0, evl1 i/o port p10 CCCCCC i/o output CC a, b CC a, b note: after reset, be sure to write data to the port p9 latch. 1.3 pin description
over view 7736 group users manual 1C8 1.3.1 examples of handling unused pins the following are examples of handling unused pins. these are, however, just examples. in actual use, make the necessary adaptations and properly evaluate performance according to the users application. (1) in single-chip mode table 1.3.5 examples of handling unused pins in single-chip mode fig. 1.3.1 examples of handling unused pins in single-chip m ode handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins open aft er they are set to the output mode ( note 1 ). leave these pins open after writing data to the port p9 regi ster ( note 3 ). leave this pin open. connect this pin to pin vcc. connect these pins to pin vss. connect this pin to pin vcc or vss. pins p0Cp8, p10 p9 _ ____ e , rde evl0, evl1 x out ( note 2 ) avcc avss, v ref , byte bsel p0Cp8 , p10 av ss v ref byte bsel m37736mhbxxxgp v ss av cc e/rde x out evl0 evl1 left open n when setting ports to input mode v cc p0Cp10 av ss v ref byte bsel m37736mhbxxxgp v ss av cc e/rde x out evl0 evl1 left open n when setting ports to output mode left open v cc p9 notes 1: when leaving these pins open after they are set to the outpu t mode, note the following: these pins function as input ports from reset until the they are switch ed to the output mode by software. therefore, voltage levels of these pins are undefined and th e power source current may increase while these ports function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. for unused pins, use the shortest possible wiring (within 20 mm from the microcomputers pins). 2: this is applied when an external clock is input to pin x in . 3: when leaving port p9 pins open after writing data to the por t p9 register, note the following: these pins are in a floating state from reset until the data is wr itten to the port p9 register by software. therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. 1.3 pin description
over view 7736 group users manual 1C9 (2) in memory expansion mode (external bus mode a) table 1.3.6 examples of handling unused pins in memory expan sion mode (external bus mode a) pins p4 2 Cp4 7 , p5Cp8, p10 ( note 7 ) p9 _____ bhe ( note 3 ), ale ( note 4 ), hlda x out ( note 6 ) _____ ____ hold , rdy avcc avss, v ref evl0, evl1 handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open after writing data to the port p9 regi ster ( note 8 ). leave these pins open. ( note 5 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. leave these pins open. fig. 1.3.2 examples of handling unused pins in memory expans ion mode (external bus mode a) notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be en hanced when the contents of the above ports direction registers are set periodically. this is bec ause these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 20 mm from the microcomputers pins). 3: this is applied when h level is input to pin byte. 4: this is applied when h level is input to pin byte and the accessible area has a capacity of 64 kbytes. 5: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory exp ansion mode by software. therefore, a voltage level of this pin is undefined and the power sourc e current may increase while this pin functions as an input port. 6: this is applied when an external clock is input to pin x in . 7: set pin p4 2 / f 1 as pin p4 2 . (clock f 1 output is disabled.) and then, for this pin, do the same handling as that for pins p4 3 to p4 7 , p5 to p8 and p10. 8: when leaving port p9 pins open after writing data to the po rt p9 register, note the following: these pins are in a floating state from reset until the data is wr itten to the port p9 register by software. therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. p4 2 Cp4 7 , p5Cp8, p10 av ss v ref hold rdy left open m37736mhbxxxgp v cc v ss av cc x out evl0 evl1 n when setting ports to input mode bhe ale hlda left open p4 2 Cp4 7 , p5Cp10 av ss v ref hold rdy left open v ss av cc x out evl0 evl1 n when setting ports to output mode bhe ale hlda left open left open v cc m37736mhbxxxgp p9 1.3 pin description
over view 7736 group users manual 1C10 (3) in memory expansion mode (external bus mode b) table 1.3.7 examples of handling unused pins in memory expan sion mode (external bus mode b) pins p4 2 Cp4 7 , p5Cp8, p10 ( note 5 ) p9 ____ ____ ____ whe , whl , rde , _____ ___ ___ _____ hlda , cs 0 C cs 4 , rsmp x out ( note 4 ) _____ ____ hold , rdy avcc avss, v ref evl0, evl1 handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open after writing data to the port p9 regi ster ( note 6 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. leave these pins open. fig. 1.3.3 examples of handling unused pins in memory expans ion mode (external bus mode b) notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be en hanced when the contents of the above ports direction registers are set periodically. this is bec ause these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 20 mm from the microcomputers pins). 3: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory exp ansion mode by software. therefore, a voltage level of this pin is undefined and the power sourc e current may increase while this pin functions as an input port. 4: this is applied when an external clock is input to pin x in . 5: set pin p4 2 / f 1 as pin p4 2 . (clock f 1 output is disabled.) and then, for this pin, do the same handling as that for pins p4 3 to p4 7 , p5 to p8 and p10. 6: when leaving port p9 pins open after writing data to the po rt p9 register, note the following: these pins are in a floating state from reset until the data is wr itten to the port p9 register by software. therefore, voltage levels of these pins are undefined and th e power source current may increase while they are in a floating state. p4 2 Cp4 7 , p5Cp8, p10 av ss v ref hold rdy left open m37736mhbxxxgp v cc v ss av cc x out cs 0 Ccs 4 evl0 evl1 n when setting ports to input mode weh wel rde hlda rsmp left open p4 2 Cp4 7 , p5Cp10 av ss v ref hold rdy left open v ss av cc x out cs 0 Ccs 4 evl0 evl1 n when setting ports to output mode weh wel rde hlda rsmp left open left open v cc m37736mhbxxxgp p9 1.3 pin description
over view 7736 group users manual 1C11 (4) in microprocessor mode (external bus mode a) table 1.3.8 examples of handling unused pins in microprocess or mode (external bus mode a) handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open after writing data to the port p9 regi ster ( note 7 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. leave these pins open. notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 20 mm from the microcomputers pins). 3: this is applied when h level is input to pin byte. 4: this is applied when h level is input to pin byte and the accessible area has a capacity of 64 kbytes. 5: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the microproce ssor mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. 6: this is applied when an external clock is input to pin x in . 7: when leaving port p9 pins open after writing data to the po rt p9 register, note the following: these pins are in a floating state from reset until the data is written to the port p9 register by software. therefore, voltage levels of these pins are undefined and th e power source current may increase while they are in a floating state. fig. 1.3.4 examples of handling unused pins in microprocesso r mode (external bus mode a) pins p4 3 Cp4 7 , p5Cp8, p10 p9 _____ bhe ( note 3 ), ale ( note 4 ), hlda , f 1 x out ( note 6 ) _____ ____ hold , rdy av cc av ss , v ref evl0, evl1 p4 3 Cp4 7 , p5Cp8, p10 1 av ss v ref hold rdy left open m37736mhbxxxgp v cc v ss av cc x out evl0 evl1 n when setting ports to input mode bhe ale hlda left open p4 3 Cp4 7 , p5Cp10 1 av ss v ref hold rdy left open v ss av cc x out evl0 evl1 n when setting ports to output mode bhe ale hlda left open left open v cc m37736mhbxxxgp p9 1.3 pin description
over view 7736 group users manual 1C12 pins p4 3 Cp4 7 , p5Cp8, p10 p9 ____ ____ ____ whe , whl , rde , _____ _____ hlda , f 1 , cs 0 C cs 4 , rsmp x out ( note 4 ) _____ ____ hold , rdy av cc av ss , v ref evl0, evl1 (5) in microprocessor mode (external bus mode b) table 1.3.9 examples of handling unused pins in microprocess or mode (external bus mode b) handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open after writing data to the port p9 regi ster ( note 5 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. leave these pins open. fig. 1.3.5 examples of handling unused pins in microprocesso r mode (external bus mode b) notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 20 mm from the microcomputers pins). 3: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the microproce ssor mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. 4: this is applied when an external clock is input to pin x in . 5: when leaving port p9 pins open after writing data to the po rt p9 register, note the following: these pins are in a floating state from reset until the data is wr itten to the port p9 register by software. therefore, voltage levels of these pins are undefined and th e power source current may increase while they are in a floating state. p4 3 Cp4 7 , p5Cp8, p10 1 rsmp av ss v ref hold rdy left open m37736mhbxxxgp v cc v ss av cc x out cs 0 Ccs 4 evl0 evl1 n when setting ports to input mode weh wel rde hlda left open p4 3 Cp4 7 , p5Cp10 1 rsmp av ss v ref hold rdy left open v ss av cc x out cs 0 Ccs 4 evl0 evl1 n when setting ports to output mode weh wel rde hlda left open left open v cc m37736mhbxxxgp p9 1.3 pin description
over view 7736 group users manual 1C13 1.4 block diagram figure 1.4.1 shows the m37736mhbxxxgp block diagram. fig. 1.4.1 m37736mhbxxxgp block diagram bus interface unit (biu) clock input clock output enable output x in e reset input reset reference voltage input v ref clock generating circuit p8(8) p7(8) p5(8) p6(8) p4(8) p3(4) data buffer db h (8) data buffer db l (8) instruction queue buffer q 0 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) data bank register dt(8) program counter pc(16) incrementer/decrementer (24) program bank register pg(8) input buffer register ib(16) direct page register dpr(16) stack pointer s(16) index register y(16) index register x(16) anthmetic logic unit(16) accumulator b(16) accumulator a(16) data bus(even) data bus(odd) input/output port p8 input/output port p7 input/output port p6 input/output port p5 input/output port p3 input/output port p4 p2(8) input/output port p2 p1(8) input/output port p0 watchdog timer cnvss byte external data bus width selection input timer tb1(16) timer tb2(16) p0(8) input/output port p1 timer tb0(16) timer ta1(16) timer ta2(16) timer ta3(16) timer ta4(16) timer ta0(16) rom 124 kbyte ram 3968 byte uart1(9) uart0(9) av ss (0v) av cc incrementer (24) program address register pa(24) data address register da(24) address bus (0v) v ss v cc processor status register ps(11) a-d converter(10) uart2(9) x cin x cout x cin x cout p9(8) output port p9 p10(8) input/output port p10 bsel evl0 evl1 central processing unit (cpu) instruction register(8) 1.4 block diagram
overview 7736 group users manual 1C14 memo 1.4 block diagram
chapter 2 chapter 2 central processing unit (cpu) 2.1 central processing unit 2.2 bus interface unit 2.3 accessible area 2.4 memory allocation 2.5 processor modes
central processing unit (cpu) 7736 group users manual 2C2 2.5 processor modes concerning chapter 2. central processing unit (cpu), the 7 736 group differs from the 7733 group in the following section. therefore, only the differences ar e described below: ? 2.5 processor modes the following sections of the 7736 group differ depending on the external bus mode, which is a or b: ? 2.2 bus interface unit external bus mode a (page 2C10 in part 1) external bus mode b (page 2C2 in part 2) ? 2.3 accessible area external bus mode a (page 2C16 in part 1) external bus mode b (page 2C5 in part 2) the following sections of the 7736 group are the same as tho se of the 7733 group. therefore, for these sections, refer to the part 1: ? 2.1 central processing unit (page 2C2 in part 1) ? 2.4 memory allocation (page 2C18 in part 1) 2.5 processor modes concerning section 2.5 processor modes, the 7736 group dif fers from the 7733 group in the following: ? figure 2.5.2 the following differ depending on the external bus mode. the refore, refer to the corresponding part: ? figure 2.5.1 and table 2.5.1 external bus mode a (figure 2.5.1 and table 2.5.1 in part 1) external bus mode b (figure 2.5.1 and table 2.5.1 in part 2) the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 2.5 processor modes (page 2C23 in part 1)
central processing unit (cpu) 7736 group users manual 2C3 2.5 processor modes fig. 2.5.2 pin configuration in each processor mode (top vie w) p4 6 p4 5 p4 4 p4 3 p4 2 / 1 p4 7 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out p0 0 p0 1 p0 2 p0 3 p0 4 p0 5 1 4 3 2 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 89 88 87 86 85 90 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 m37736mhbxxxgp 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p10 7 /ki 3 p10 6 /ki 2 p10 5 /ki 1 p10 4 /ki 0 p10 3 p10 2 p10 1 p10 0 p0 6 p0 7 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 25 26 27 28 29 30 31 33 32 34 40 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 56 55 54 53 52 51 84 83 82 81 p1 7 p2 0 p1 2 p2 2 p2 3 p2 4 p8 7 /t x d 1 p9 0 /cts 2 p9 1 /clk 2 p9 2 /rxd 2 p9 3 /txd 2 p9 4 p9 5 p9 6 p9 7 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg p7 4 /an 4 p8 6 /r x d 1 p8 5 /clk 1 p8 4 /cts 1 /rts 1 p2 5 p2 6 p2 7 p3 0 p3 1 p3 2 p3 3 evl0 evl1 v cc v ss e/rde x out x in reset bsel cnv ss byte p4 0 p4 1 ] 1 ] 1 ] 1 connect this pin to vss in the single-chip mode. : these pins functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. p4 6 p4 5 p4 4 p4 3 p4 2 / 1 p4 7 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out a 0 /cs 0 a 1 /cs 1 a 2 /cs 2 a 3 /cs 3 a 4 /cs 4 a 5 /rsmp 1 4 3 2 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 89 88 87 86 85 90 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 m37736mhbxxxgp 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p10 7 /ki 3 p10 6 /ki 2 p10 5 /ki 1 p10 4 /ki 0 p10 3 p10 2 p10 1 p10 0 a 6 /a 16 a 7 /a 17 a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 25 26 27 28 29 30 31 33 32 34 40 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 56 55 54 53 52 51 84 83 82 81 a 15 /d 15 a 16 /a 0 /d 0 a 17 /a 1 /d 1 a 18 /a 2 /d 2 a 19 /a 3 /d 3 a 20 /a 4 /d 4 p8 7 /t x d 1 p9 0 /cts 2 p9 1 /clk 2 p9 2 /rxd 2 p9 3 /txd 2 p9 4 p9 5 p9 6 p9 7 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg p7 4 /an 4 p8 6 /r x d 1 p8 5 /clk 1 p8 4 /cts 1 /rts 1 a 21 /a 5 /d 5 a 22 /a 6 /d 6 a 23 /a 7 /d 7 r/w/wel bhe/weh ale hlda evl0 evl1 v cc v ss e/rde x out x in reset bsel cnv ss byte hold rdy ] 2 ] 2 1 in the microprocessor mode : these pins functions in the single-chip mode differ from those in the memory expansion or microprocessor mode.
central processing unit (cpu) 7736 group users manual 2C4 2.5 processor modes memo
chapter 3 chapter 3 programmable i/o ports 3.1 programmable i/o ports and output-only ports 3.2 port peripheral circuits 3.3 pull-up function 3.4 internal peripheral devices i/o functions (ports p4 2 , p5 to p8, p9 0 to p9 3 , and p10 4 to p10 7 )
7736 group users manual 3C2 programmable i/o ports functions of all ports in the single-chip mode and those of ports p4 3 to p4 7 and p5 to p10 in the memory expansion or the microprocessor mode are described below. for more information about ports p0 to p4, whose functions depend on the processor mode, refer to section 2.5 processor modes and chapter 12. connecting external devices. 3.1 programmable i/o ports and output-only ports the 7736 group has 76 programmable i/o ports (p0 to p8 and p10) and 8 output-only ports (p9). each of programmable i/o ports has a port direction register and a port register in the sfr area. each output-only port has a port register in the sfr area. figure 3.1.1 shows the memory map of port direction registers and port registers. note that ports p4 2 , p5 to p8, p9 0 to p9 3 and p10 4 to p10 7 also function as i/o pins for internal peripheral devices. for details, refer to section 3.4 internal peripheral devices i/o functions and the corresponding functional description. 3.1 programmable i/o ports and output-only ports port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p8 direction register 8 16 9 16 a 16 b 16 c 16 d 16 e 16 f 16 10 16 11 16 12 16 13 16 14 16 addresses port p0 register port p1 register port p0 direction register port p1 direction register port p2 register port p3 register port p2 direction register port p3 direction register 2 16 3 16 4 16 5 16 6 16 7 16 port p9 register port p10 register port p10 direction register 15 16 16 16 17 16 18 16 fig. 3.1.1 memory map of port direction registers and port registers
7736 group users manual 3C3 programmable i/o ports 3.1.1 port pi direction register this register determines the direction of programmable i/o ports. each bit of this register corresponds to one specified pin. figure 3.1.2 shows the structure of the port pi (i = 0 to 8 and 10) direction register. fig. 3.1.2 structure of port pi (i = 0 to 8 and 10) direction register bit bit name functions 0: input mode (the port functions as an input port.) 1: output mode (the port functions as an output port.) port pi direction register (i = 0 to 8 and 10) (addresses 4 16 ,5 16 ,8 16 ,9 16 ,c 16 ,d 16 ,10 16 ,11 16 ,14 16 ,18 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw note: writing to bits 4 to 7 of the port p3 direction register is invalid and these bits are fixed to ?? when they are read. 0 port pi 0 direction selection bit 0 rw 1 port pi 1 direction selection bit 0 rw 2 port pi 2 direction selection bit 0 rw 3 port pi 3 direction selection bit 0 rw 4 port pi 4 direction selection bit 0 rw 5 port pi 5 direction selection bit 0 rw 6 port pi 6 direction selection bit 0 rw 7 port pi 7 direction selection bit 0 rw pi 7 b1 b2 b3 b4 b5 b6 b7 bit corresponding pin pi 6 pi 5 pi 4 pi 3 pi 2 pi 1 pi 0 b0 3.1 programmable i/o ports and output-only ports
7736 group users manual 3C4 programmable i/o ports 3.1.2 port pi register data is input from or output to the external by writing or reading data to or from a port register. a port register consists of a port latch, which holds the output data, and a circuit, which reads the pin state. each bit of the port register corresponds to one specified pin. figure 3.1.3 shows the structure of the port pi (i = 0 to 10) register. (1) how to output data from programmable i/o port set the corresponding bit of the port direction register to the output mode. write data to the corresponding bit of the port register, and then the data is written into the port latch. a data which is set in the port latch is output. when a bit of a port register which corresponds to a port set for the output mode is read out, the contents of the port latch, instead of pin state, is read out. accordingly, output data can correctly be read out without influence of external load, etc. (refer to figures 3.2.1 and 3.2.2 ) (2) how to input data from programmable i/o port set the corresponding bit of the port direction register to the input mode. the pin enters a floating state. a when reading the corresponding bit of the port register in state , data which is input from the pin can be read in. when data is written to a port register which corresponds to a port set for the input mode, the data is written only into the port latch and not output to the external. pins retain a floating state. (3) how to output data from output-only port write data to the corresponding bit of the port register, and then the data is written into the port latch. data which is set in the port latch is output. when a bit of a port register which corresponds to a port is read out, the contents of the port latch, instead of pin state, is read out. accordingly, output data can correctly be read out without influence of external load, etc. (refer to figures 3.2.1 and 3.2.2 ) 3.1 programmable i/o ports and output-only ports
7736 group users manual 3C5 programmable i/o ports fig. 3.1.3 structure of port pi (i = 0 to 10) register data is input from or output to a pin by reading/writing from /to the corresponding bit. port pi register (i = 0 to 10) (addresses 2 16 ,3 16 ,6 16 ,7 16 ,a 16 ,b 16 ,e 16 ,f 16 ,12 16 ,13 16 ,16 16 ) b1 b0 b2 b3 b4 b5 b6 b7 notes 1: writing to bits 4 to 7 of the port p3 register is invalid and these bits are fixed to ??when they are read. 2: after reset, be sure to write data to the port p9 register. 0: ??level 1: ??level 7 port pi 7 ? pin undefined rw bit bit name functions at reset rw 0 port pi 0 ? pin rw undefined 1 port pi 1 ? pin rw undefined 2 port pi 2 ? pin rw undefined 3 port pi 3 ? pin rw undefined 4 port pi 4 ? pin rw undefined 5 port pi 5 ? pin rw undefined 6 port pi 6 ? pin rw undefined 3.1 programmable i/o ports and output-only ports
7736 group users manual 3C6 programmable i/o ports 3.2 port peripheral circuits figures 3.2.1 and 3.2.2 show the port peripheral circuits. 3.2 port peripheral circuits fig. 3.2.1 port peripheral circuits (1) ?ports p6 2 /int 0 to p6 4 /int 2 (inside dotted-line included) ports p10 4 /ki 0 to p10 7 /ki 3 (inside dotted-line not included) port direction register port latch data bus pull-up selection pull-up transistor ports p5 0 /ta0 out , p5 2 /ta1 out , p5 4 /ta2 out , p5 6 /ta3 out , p6 0 /ta4 out , p8 2 /rxd 0 /clks 0 (inside dotted-line included, and shaded area not included) ?ports p8 3 /txd 0 , p8 7 /txd 1 (inside dotted-line not included, and shaded area included) note 1: valid only when used as pin txdj for serial i/o. port direction register port latch data bus output 1 n-channel open-drain selection ( note 1 ) ports p4 2 / 1 (inside dotted-line not included, and shaded area not inclu ded) ? ports p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7, p3 0 to p3 3 , p4 3 to p4 6 , p10 0 to p10 3 (inside dotted-line not included) ports p4 0 /hold, p4 1 /rdy, p4 7 , p5 1 /ta0 in , p5 3 /ta1 in , p5 5 /ta2 in , p5 7 /ta3 in , p6 1 /ta4 in , p6 5 /tb0 in to p6 7 /tb2 in / sub , p8 6 /rxd 1 (inside dotted-line included) port direction register port latch data bus
7736 group users manual 3C7 programmable i/o por ts 3.2 port peripheral circuits fig. 3.2.2 port peripheral circuits (2) ? e (external bus mode a) ?ports p8 0 /cts 0 /rts 0 /clks 1 , p8 1 /clk 0 , p8 4 /cts 1 /rts 1 , p8 5 /clk 1 port direction register port latch data bus output 1 0 ?ports p7 0 /an 0 to p7 7 /an 7 /x cin port direction register port latch data bus analog input (note 2) sub-clock oscillation circuit note 2: the sub-clock oscillation circuit is present only in ports p7 6 and p7 7 ?ports p9 0 /cts 2 , p9 2 /r x d 2 (inside dotted-line included) ports p9 4 to p9 7 (inside dotted-line not included) port latch data bus output control ?port p9 1 /clk 2 (inside dotted-line included) port p9 3 /t x d 2 (inside dotted-line not included) port latch data bus output control output ? e / rde (external bus mode b) hold acknowledge
7736 group users manual 3C8 programmable i/o ports 3.3 pull-up function ___ ___ 3.3.1 pull-up function for ports p10 4 to p10 7 ( ki 0 to ki 3 ) ___ ___ ports p10 4 to p10 7 ( ki 0 to ki 3 ) can be pulled high by setting the port p10 pull-up selection bit (bit 6 at address 6d 16 ). figure 3.3.1 shows the structure of the port function control register. when pulling ports p10 4 to p10 7 high, clear bits 4 to 7 at address 18 16 (port p10 direction register) to 0. ____ ____ 3.3.2 pull-up function for ports p6 2 to p6 4 ( int 0 to int 2 ) ____ ____ ports p6 2 and p6 3 ( int 0 and int 1 ) can be pulled high by setting the port p6 pull-up selection bit 0 (bit 3 ____ at address 6d 16 ). port p6 4 ( int 2 ) can be pulled high by setting the port p6 pull-up selection bit 1 (bit 5 at address 6d 16 ). figure 3.3.1 shows the structure of the port function control register. when pulling ports p6 2 to p6 4 high, clear bits 2 to 4 at address 10 16 (port p6 direction register) to 0. 3.3 pull-up function
7736 group users manual 3C9 programmable i/o por ts 3.3 pull-up function fig. 3.3.1 structure of port function control register bit functions b7 b6 b5 b4 b3 b2 b1 b0 port function control register (address 6d 16 ) bit name 0: pins p0 to p3 are used for the external bus output. 1: pins p0 to p3 are used for the port output. 0 standby state selection bit 1 sub-clock output selection bit/ timer b2 clock source selection bit 0: no internal connection 1: internal connection with timer b2 2 timer b1 internal connect selection bit 3 port p6 pull-up selection bit 0 0: no pull-up for pins p10 4 / ki 0 to p10 7 / ki 3 1: with pull-up for pins p10 4 / ki 0 to p10 7 / ki 3 6 port p10 pull-up selection bit 7 key input interrupt selection bit 0: int 2 interrupt 1: key input interrupt 5 port p6 pull-up selection bit 1 4 must be fixed to 0. at reset rw rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 0 ?port-x c selection bit ] = 0 (when the sub clock is not used) timer b2 (event counter mode) clock source selection (note 1) 0: tb2 in input (event counter mode) 1: main clock divided by 32 (clock timer) ?port-x c selection bit = 1 (when the sub clock is used) sub-clock output selection 0: pin p6 7 /tb2 in / sub functions as a programmable i/o port. 1: sub clock sub is output from pin p6 7 /tb2 in / sub . (note 2) notes 1: when the port-xc selection bit = 0 and timer b2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: when timer b1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 2, 4 and 7 are not used fo r the pull-up function. ?key input interrupt selection bit = 0 0: no pull-up for pin p6 4 /int 2 1: with pull-up for pin p6 4 /int 2 ?key input interrupt selection bit = 1 0: pin p6 4 /int 2 is a port with no pull-up. 1: pin p6 4 /int 2 is an input pin with pull-up and is used for the key input interrupt. 0: no pull-up for pins p6 2 /int 0 and p6 3 /int 1 1: with pull-up for pins p6 2 /int 0 and p6 3 /int 1 port-xc selection bit ] : bit 4 of the oscillation circuit control register 0 (addr ess 6c 16 )
7736 group users manual 3C10 programmable i/o ports 3.4 internal peripheral devices i/o functions (ports p4 2 , p5 to p8, p9 0 to p9 3 and p10 4 to p10 7 ) ports p4 2 , p5 to p8, p9 0 to p9 3 and p10 4 to p10 7 also function as i/o pins for the internal peripheral devices. table 3.4.1 lists correspondence between each port and internal peripheral devices i/o pin. for internal peripheral devices i/o functions, refer to the cor responding functional description. for the clock f 1 output pin, refer to chapter 12. connecting external devices. for the sub-clock oscillation circuits i/o pins, refer to chapter 14. clock generating circuit. 3.4 internal peripheral devices i/o functions (ports p4 2 , p5 to p8, p9 0 to p9 3 and p10 4 to p10 7 ) table 3.4.1 correspondence between each port and internal pe ripheral devices i/o pin port p4 2 p5 0 , p6 0 , p6 1 p6 2 to p6 4 p6 5 , p6 6 p6 7 p7 0 , p7 5 p7 6 , p7 7 p8, p9 0 to p9 3 p10 4 to p10 7 internal peripheral devices i/o pin clock f 1 output pin timer as i/o pins input pins for external interrupts timer bs input pins timer bs input pin/clock f sub output pin a-d converters input pins a-d converters input pins/sub-clock oscillation circuits i /o pins i/o pins for serial i/o input pins for the key input interrupt function
chapter 4 chapter 4 interrupts 4.1 overview 4.2 interrupt sources 4.3 interrupt control 4.4 interrupt priority level 4.5 interrupt priority level detection circuit 4.6 interrupt priority level detection time 4.7 how interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) 4.8 return from interrupt routine 4.9 multiple interrupts ____ 4.10 external interrupts ( inti interrupt) 4.11 precautions for interrupts
7736 group users manual interrupts 4C2 interrupts of the 7736 group are the same as those of the 7733 group. therefore, for interrupts, refer to the corresponding sections in part 1: ? 4.1 overview (page 4-2 in part 1) ? 4.2 interrupt sources (page 4-4 in part 1) ? 4.3 interrupt control (page 4-6 in part 1) ? 4.4 interrupt priority level (page 4-10 in part 1) ? 4.5 interrupt priority level detection circuit (page 4-11 in part 1) ? 4.6 interrupt priority level detection time (page 4-13 in part 1) ? 4.7 how interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) (page 4-14 in part 1) ? 4.8 return from interrupt routine (page 4-17 in part 1) ? 4.9 multiple interrupts (page 4-17 in part 1) ____ ? 4.10 external interrupts ( int i interrupt) (page 4-19 in part 1) ? 4.11 precautions for interrupts (page 4-23 in part 1)
chapter 5 chapter 5 key input interrupt function 5.1 overview 5.2 block description 5.3 initial setting example for related registers
key input interrupt function 7736 group users manual 5C2 the key input interrupt function is used to generate an interrupt request when one of the input levels of four or five pins falls. by using this function when terminating the stop or wait mode, the key-on wakeup can be realized. for the way to terminate the stop or wait mode, refer to section 17.4 power saving. for the stop and wait modes, refer to chapter 11. stop and wait modes. 5.1 overview ___ ___ a key input interrupt request occurs when one of the input levels of pins ki 0 to ki 3 falls. therefore, by configuring an external key matrix shown in figure 5.1.1, an interrupt request can be generated only by ___ ___ pushing a key. pins ki 0 to ki 3 can be pulled high by software and the same function can also be selected ___ ___ for port p6 4 . therefore, when using the key input interrupt function, whether to use four pins (pins ki 0 to ki 3 ) ___ ___ or five pins (pins ki 0 to ki 3 and p6 4 ) can be selected. ____ the key input interrupt and the int 2 interrupt share the same interrupt vector addresses and interrupt control register. 5.1 overview ki 2 ki 1 ki 0 p6 4 /int 2 p6 3 p6 2 p6 1 p6 0 key matrix m37736mhbxxxfp ki 3 fig. 5.1.1 key matrix example when key input interrupt function is used
key input interrupt function 7736 group users manual 5C3 5.2 block description figure 5.2.1 shows the block diagram for the key input inter rupt function. 5.2 block description int 2 /key input interrupt control register interrupt control register p6 4 / int 2 p10 7 / ki 3 p10 5 / ki 1 p10 6 / ki 2 p10 4 / ki 0 int 2 /key input interrupt request key input interrupt selection bit (address 7f 16 ) when key input interrupt is selected, it is necessary to select edge sense which uses falling edge. pullCup transistor port p10 pull-up selection bit port p10 7 direction register 0 1 pullCup transistor pullCup transistor pullCup transistor port p6 pull-up selection bit 1 port p6 4 direction register 0 1 port p6 pull-up selection bit 1 fig. 5.2.1 block diagram for key input interrupt function ___ ___ ____ 5.2.1 pins ki 0 to ki 3 and p6 4 / int 2 when the key input interrupt function is selected, pins p10 4 to p10 7 become input pins for the key input ___ ___ interrupt ( ki 0 to ki 3 ). when selecting the key input interrupt function, clear all o f bits 4 to 7 at address 18 16 (port p10 direction register) to 0. ___ ___ when bits 4 to 7 at address 16 16 (port p10 register) are read out, the status of pins ki 0 to ki 3 can be read ____ in. when using pin p6 4 / int 2 as an input pin for the key input interrupt, set both of bi ts 5 and 7 at address 6d 16 to 1 and bit 4 at address 10 16 (port p6 direction register) to 0. when bit 4 at address e6 16 (port ____ p6 register) is read out, the status of pin p6 4 / int 2 can be read in. fig. 5.2.2 port p10 and p6 direction registers when key inpu t interrupt function is selected b7 b6 b5 b4 b3 b2 b1 b0 port p10 direction register (address 18 16 ) 0 00 0 b7 b6 b5 b4 b3 b2 b1 b0 port p 6 direction register (address 10 16 ) 0 0: must be set to 0. 0: must be set to 0.
key input interrupt function 7736 group users manual 5C4 5.2.2 port function control register figure 5.2.3 shows the structure of the port function contro l register. 5.2 block description fig. 5.2.3 structure of port function control register bit functions b7 b6 b5 b4 b3 b2 b1 b0 port function control register (address 6d 16 ) bit name 0: pins p0 to p3 are used for the external bus output. 1: pins p0 to p3 are used for the port output. 0 standby state selection bit 1 sub-clock output selection bit/ timer b2 clock source selection bit 0: no internal connection 1: internal connection with timer b2 2 timer b1 internal connect selection bit 3 port p6 pull-up selection bit 0 0: no pull-up for pins p10 4 /ki 0 to p10 7 /ki 3 1: with pull-up for pins p10 4 /ki 0 to p10 7 /ki 3 6 port p10 pull-up selection bit 7 key input interrupt selection bit 0: int 2 interrupt 1: key input interrupt 5 port p6 pull-up selection bit 1 4 must be fixed to 0. at reset rw rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 0 ?port-x c selection bit ] = 0 (when the sub clock is not used) timer b2 (event counter mode) clock source selection (note 1) 0: tb2 in input (event counter mode) 1: main clock divided by 32 (clock timer) ?port-x c selection bit = 1 (when the sub clock is used) sub-clock output selection 0: pin p6 7 /tb2 in / sub functions as a programmable i/o port. 1: sub clock sub is output from pin p6 7 /tb2 in / sub . (note 2) notes 1: when the port-xc selection bit = 0 and timer b2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: when timer b1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 4 are not used for the key input interrupt function. ?key input interrupt selection bit = 0 0: no pull-up for pin p6 4 /int 2 1: with pull-up for pin p6 4 /int 2 ?key input interrupt selection bit = 1 0: pin p6 4 /int 2 is a port with no pull-up. 1: pin p6 4 /int 2 is an input pin with pull-up and is used for the key input interrupt. 0: no pull-up for pins p6 2 /int 0 and p6 3 /int 1 1: with pull-up for pins p6 2 /int 0 and p6 3 /int 1 port-xc selection bit ] : bit 4 of the oscillation circuit control register 0 (addr ess 6c 16 )
key input interrupt function is selected. when this bit key input interrupt function 7736 group users manual 5C5 (1) port p6 pull-up selection bit (bit 5) ____ when using pin p6 4 / int 2 as an input pin for the key input interrupt, set this bit t o 1. when this bit ____ is set to 1, pin p6 4 / int 2 is pulled high. (2) port p10 pull-up selection bit (bit 6) ___ ___ this is a bit to pull pins ki 0 to ki 3 high. when configuring a key matrix, there is no need to co nnect ___ ___ pull-up transistors externally if this bit is set to 1, in other words, if pins ki 0 to ki 3 are set to be pulled high. (3) key input interrupt selection bit (bit 7) this is a bit to select the key input interrupt function. ____ the key input interrupt and the int 2 interrupt shar e the same interrupt vector addresses and interrupt control register. when this bit is set to 1, the = 1 and bit 5 (port p6 pull-up selection bit ) ____ ____ = 0, pin p6 4 / int 2 is a programmable i/o port. (at this time, the int 2 interrupt cannot be used.) when ____ both of this bit and bit 5 (port p6 pull-up selection bit 1) are 1, pin p6 4 / int 2 can be used for the key input interrupt. 5.2 block description
key input interrupt function 7736 group users manual 5C6 5.2.3 interrupt function ____ the key input interrupt and the int 2 interrupt share the same interrupt vector addresses and int errupt control register. specify addresses fff0 16 and fff1 16 (in order wor ds, the vector addresses for the int 2 /key input interrupt) as the interrupt vector addresses; specify the i nt 2 /key input interrupt control register (address 7f 16 ) as the interrupt control register. figure 5.2.4 shows the s tructure of the int 2 /key input interrupt control register when the key input interrupt function is selected. the operation at accepting a key input interrupt request is the same as that at accepting an int 2 interrupt request. 5.2 block description ____ fig. 5.2.4 structure of int 2 /key input interrupt control register when key input interru pt function is selected b7 b6 b5 b4 b3 b2 b1 b0 int 2 /key input interrupt control register (address 7f 16 ) bit 4 must be fixed to 0. 3 interrupt request bit 2 1 0 interrupt priority level selection bits bit name at reset undefined 0 0 0 0 0 0 rw functions 0 0 0: level 0 (interrupt is disabled.) 0 0 1: level 1 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 b2 b1 b0 0: no interrupt request has occurred. 1: interrupt request has occurred. 5 7 6 not implemented. 00 undefined rw rw rw rw rw rw C C
key input interrupt function 7736 group users manual 5C7 5.3 initial setting example for related registers figure 5.3.1 shows an initial setting example for registers related to the key input interrupt function. fig. 5.3.1 initial setting example for registers related to key input interrupt function 5.3 initial setting example for related registers setting of the interrupt priority level b0 int 2 /key input interrupt control register (address 7f 16 ) b7 0 00 interrupt priority level selection bits one of levels 1 to 7 must be set. interrupt request bit h in order to enable the key input interrupt, the interrupt disable flag (i) must be set to ??and the processor interrupt priority level (ipl) must be a value smaller than the int 2 /key input interrupt? priority level. (refer to chapter ?. interrupts?in part 1. ) b0 selection of the key input interrupt function selection of the key input interrupt function pull-up selection for pins ki 0 to ki 3 port function control register (address 6d 16 ) 0: no pull-up 1: pull-up port p10 pull-up selection bit b7 1 0 0: port p6 4 is a programmable i/o port with no pull-up. 1: port p6 4 is an input pin with pull-up and is used for the key input interrupt. port p6 pull-up selection bit 1 setting of port p10 and p6 direction registers b7 b0 port p10 direction register (address 18 16 ) p10 4 to p10 7 are set to the input mode. (must be set to ?000.? 0 0 0 0 b7 b0 port p6 direction register (address 10 16 ) when setting p6 4 as an input pin for the key input interrupt, set this bit to ?. 0
key input interrupt function 7736 group users manual 5C8 5.3 initial setting example for related registers memo
chapter 6 chapter 6 timer a 6.1 overview 6.2 block description 6.3 timer mode 6.4 event counter mode 6.5 one-shot pulse mode 6.6 pulse width modulation (pwm) mode
7736 group users manual 6-2 timer a timer a of the 7736 group is the same as that of the 7733 group. therefore, for timer a, refer to the corresponding sections in part 1: ? 6.1 overview (page 6-2 in part 1) ? 6.2 block description (page 6-3 in part 1) ? 6.3 timer mode (page 6-9 in part 1) ? 6.4 event counter mode (page 6-19 in part 1) ? 6.5 one-shot pulse mode (page 6-32 in part 1) ? 6.6 pulse width modulation (pwm) mode (page 6-41 in part 1)
chapter 7 chapter 7 timer b 7.1 overview 7.2 block description 7.3 timer mode 7.4 event counter mode 7.5 pulse period/pulse width measurement mode 7.6 clock timer
7736 group users manual 7-2 timer b timer b of the 7736 group is the same as that of the 7733 group. therefore, for timer b, refer to the corresponding sections in part 1: ? 7.1 overview (page 7-2 in part 1) ? 7.2 block description (page 7-3 in part 1) ? 7.3 timer mode (page 7-10 in part 1) ? 7.4 event counter mode (page 7-17 in part 1) ? 7.5 pulse period/pulse width measurement mode (page 7-25 in part 1) ? 7.6 clock timer (page 7-34 in part 1)
chapter 8 chapter 8 serial i/o 8.1 overview 8.2 block description 8.3 clock synchronous serial i/o mode 8.4 clock asynchronous serial i/o (uart) mode
serial i/o 7736 group users manual 8C2 8.2 block description in the 7736 group, the uart2s input pins are independent of pins p7 2 to p7 5 and are multiplexed with pins p9 0 to p9 3 . therefore, concerning chapter 8. serial i/o, the 7736 group differs from the 7733 group in the following sections. only the differences are described in this chapter: ? 8.2 block description ? 8.3 clock synchronous serial i/o mode ? 8.4 clock asynchronous serial i/o (uart) mode the following section of the 7736 group is the same as that of the 7733 group. therefore, refer to part 1: ? 8.1 overview(page 8-2 in part 1) 8.2 block description concerning section 8.2 block description, the 7736 group differs from the 7733 group in the following: ? 8.2.9 port p8 direction register the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 8.2 block description (page 8-4 in part 1)
serial i/o 7736 group users manual 8C3 8.2.9 port p8 direction register i/o pins of uarti are multiplexed with ports p8 and p9. when using pins p8 2 and p8 6 as serial data input pins (rxdi), set the corresponding bits of the port p8 direction register to 0 to set this port for the input _________ _________ mode. when using pins p8 0 , p8 1 , p8 3 Cp8 5 and p8 7 as uartis i/o pins ( ctsi / rtsi , clki, txdi), these pins are forcibly set as the uartis i/o pins, regardless of the port p8 direction registers contents. also, as for clks 0 and clks 1 , refer to section 8.3.1 (4) number of transfer clock output pins (uart0) in part 1. figure 8.2.16 shows the relationship between the port p8 direction register and uartis i/o pins. when using uart2, pins p9 0 Cp9 3 are forcibly set as the uart2s input or output pins. note that the functions of the uartis i/o pins can be switched by software. for details, refer to the description of each operating mode. 8.2 block description 0 1 2 3 4 5 6 7 pin p8 0 / cts 0 / rts 0 /clks 1 pin p8 2 /rxd 0 /clks 0 pin p8 3 /txd 0 pin p8 4 / cts 1 / rts 1 pin p8 6 /rxd 1 pin p8 5 /clk 1 port p8 direction register (address 14 16 ) b1 b0 b2 b3 b4 b5 b6 b7 pin p8 1 /clk 0 pin p8 7 /txd 1 rw 0 0 0 0 0 0 0 0 corresponding pin name functions bit at reset 0: input mode 1: output mode when using pins p8 2 and p8 6 as serial data? input pins (rxd 0 , rxd 1 ), set the corresponding bits to ?. rw rw rw rw rw rw rw rw note: for pins clks 0 and clks 1 , refer to section ?.3.1 (4) number of transfer clock output pins (uart0)?in part 1. fig. 8.2.16 relationship between port p8 direction register and uartis i/o pins
serial i/o 7736 group users manual 8C4 8.3 clock synchronous serial i/o mode concerning section 8.3 clock synchronous serial i/o mode, the 7736 group differs from the 7733 group in the following: ? table 8.3.2 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 8.3 clock synchronous serial i/o mode (page 8-21 in part 1 ) table 8.3.2 functions of i/o pins in clock synchronous seria l i/o mode functions serial data output serial data input transfer clock output transfer clock input ____ cts input ____ rts output programmable i/o port ____ cts input programmable i/o port method of selection (they output dummy data when only reception is performed.) port p8 direction registers corresponding bits =0 (it can be used as an input port when only transmission is performed.) (it can be used as an output port when only transmission is performed.) internal/external clock selection bit = 0 internal/external clock selection bit = 1 ____ ____ cts / rts enable bit = 0 ____ ____ cts / rts function selection bit = 0 ____ ____ cts / rts enable bit = 0 ____ ____ cts / rts function selection bit = 1 ____ ____ cts / rts enable bit = 1 ____ cts enable bit = 0 ____ cts enable bit = 1 port p8 direction register: address 14 16 internal/external clock selection bit: bit 3 at addresses 30 16 , 38 16 , and 64 16 ____ ____ cts / rts enable bit: bit 4 at addresses 34 16 and 3c 16 ____ ____ cts / rts function selection bit: bit 2 at addresses 34 16 and 3c 16 ____ cts enable bit: bit 2 at address 68 16 h pin txdi outputs h level from when a uartis operating mo de is selected until transfer starts. (pin txdi is in a floating state when n-channel open-drain o utput is selected.) h in uart0, multiple transfer clock output pins can be used. (refer to table 8.3.3 in part 1. ) ____ notes 1: the rts output function is not assigned for uart2. 2: as for clks 0 and clks 1 , refer to section 8.3.1 (4) number of transfer clock output pins (uart0) in part 1. pin name txdi (p8 3 , p8 7 , p9 3 ) rxd 0 (p8 2 ), rxd 1 (p8 6 ) rxd 2 (p9 2 ) clki (p8 1 , p8 5 , p9 1 ) cts 0 / rts 0 (p8 0 ), cts 1 / rts 1 (p8 4 ) ( note 1 ) cts 2 (p9 0 ) 8.3 clock synchronous serial i/o mode
serial i/o 7736 group users manual 8C5 8.4 clock asynchronous serial i/o (uart) mode concerning section 8.4 clock asynchronous serial i/o (uart) mode, the 7736 group differs from the 7733 group in the following: ? table 8.4.2 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 8.4 clock asynchronous serial i/o (uart) mode (page 8-44 i n part 1) pin name txdi (p8 3 , p8 7 , p9 3 ) rxd 0 (p8 2 ), rxd 1 (p8 6 ) rxd 2 (p9 2 ) clki (p8 1 , p8 5 , p9 1 ) cts 0 / rts 0 (p8 0 ) cts 1 / rts 1 (p8 4 ) (note) cts 2 (p9 0 ) functions serial data output serial data input programmable i/o port brgi count source input ____ cts input ____ rts output programmable i/o port ____ cts input programmable i/o port method of selection (they cannot be used as programmable i/o ports.) port p8 direction registers corresponding bit = 0 (it can be used as an input port when only transmission is p erformed.) (it can be used as an output port when only transmission is performed.) internal/external clock selection bit = 0 internal/external clock selection bit = 1 ____ ____ cts / rts enable bit = 0 ____ ____ cts / rts function selection bit = 0 ____ ____ cts / rts enable bit = 0 ____ ____ cts / rts function selection bit = 1 ____ ____ cts / rts enable bit = 1 ____ cts enable bit = 0 ____ cts enable bit = 1 table 8.4.2 functions of i/o pins in uart mode port p8 direction register: address 14 16 internal/external clock selection bit: bit 3 at addresses 30 16 , 38 16 , and 64 16 ____ ____ cts / rts enable bit: bit 4 at addresses 34 16 and 3c 16 ____ ____ cts / rts function selection bit: bit 2 at addresses 34 16 and 3c 16 ____ cts enable bit: bit 2 at addresses 68 16 h pin txdi outputs h level while not transmitting after a u artis operating mode is selected. (pin txdi is in a floating state when n-channel open-drain o utput is selected.) ____ note: the rtsi output function is not assigned for uart2. 8.4 clock asynchronous serial i/o (uart) mode
serial i/o 7736 group users manual 8C6 memo 8.4 clock asynchronous serial i/o (uart) mode
chapter 9 chapter 9 a-d converter 9.1 overview 9.2 block description 9.3 a-d conversion method 9.4 absolute accuracy and differential non-linearity error 9.5 one-shot mode 9.6 repeat mode 9.7 single sweep mode 9.8 repeat sweep mode 9.9 precautions for a-d converter
a-d converter 7736 group users manual 9C2 9.1 overview in the 7736 group, the a-d converters input pins are independent of uart2s i/o pins. therefore, concerning chapter 9. a-d converter, the 7736 group differs from the 7733 group in the following section. only the differences are described in this chapter: ? 9.2 block description the following sections of the 7736 group are the same as those of the 7733 group. therefore, refer to part 1: ? 9.1 overview (page 9-2 in part 1) ? 9.3 a-d conversion method (page 9-11 in part 1) ? 9.4 absolute accuracy and differential non-linearity error (page 9-14 in part 1) ? 9.5 one-shot mode (page 9-17 in part 1) ? 9.6 repeat mode (page 9-20 in part 1) ? 9.7 single sweep mode (page 9-23 in part 1) ? 9.8 repeat sweep mode (page 9-27 in part 1) ? 9.9 precautions for a-d converter (page 9-31 in part 1) 9.2 block description concerning section 9.2 block description, the 7736 group differs from the 7733 group in the following: ? 9.2.5 port p7 direction register the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 9.2 block description (page 9-3 in part 1)
a-d converter 7736 group users manual 9C3 9.2.5 port p7 direction register input pins of the a-d converter are multiplexed with port p7. when using these pins as a-d converters input pins, set the corresponding bits of the port p7 direction register to 0 to set these ports for the input mode. figure 9.2.6 shows the relationship between the port p7 direction register and i/o pins of the sub- clock oscillation circuit and peripheral functions. fig. 9.2.6 relationship between port p7 direction register and i/o pins of sub-clock oscillation circuit and peripheral functions analog input pins an 6 and an 7 function as the port p7s i/o pins and also function as i/o pins of the sub- clock oscillation circuit. for the pin which is forcedly set to the output mode when the function for the sub- clock oscillation circuit is selected, analog input is disabled. (refer to table 9.2.3. ) table 9.2.3 port p7s pin which is forcedly set to output mode 9.2 block description pin p7 6 /an 6 /x cout sub-clock oscillation circuit is operating by itself. (bit 4 at address 6c 16 = 1 and bit 2 at address 6f 16 = 0 ) conditions where pin is forcedly set to output mode bit corresponding bit? name functions 0 1 2 3 4 5 6 pin an 0 pin an 2 pin an 3 pin an 4 pin an 6 /x cout 0: input mode 1: output mode pin an 5 /ad trg port p7 direction register (address 11 16 ) b1 b0 b2 b3 b4 b5 b6 b7 pin an 1 at reset rw 0 0 0 0 0 0 0 when using these pins as a-d converter? input pins, set the corresponding bits to ?. 7 pin an 7 /x cin 0 rw rw rw rw rw rw rw rw
a-d converter 7736 group users manual 9C4 memo 9.2 block description
chapter 10 chapter 10 watchdog timer 10.1 block description 10.2 operation description 10.3 precautions for watchdog timer
w a tchdog timer 7736 group users manual 10-2 10.2 operation description concerning chapter 10. watchdog timer, the 7736 group diff ers from the 7733 group in the following section. therefore, only the differences are described in th is chapter: ? 10.2 operation description the following sections of the 7736 group are the same as tho se of the 7733 group. therefore, for these sections, refer to part 1: ? 10.1 block description (page 10-2 in part 1) ? 10.3 precautions for watchdog timer (page 10-10 in part 1) 10.2 operation description concerning section 10.2 operation description, the 7736 gr oup differs from the 7733 group in the following: ? figure 10.2.2 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 10.2 operation description (page 10-5 in part 1) bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to 0 (note 2) . clock prescaler reset bit 0 0 0 0 undefined 0 1 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input from the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown in figure 10.2.3 in part 1. by writing 1 to this bit, clock prescaler is initialized. rw 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. this bit is ignored. 2: the case where data 01010101 2 is written with the procedure shown in figure 10.2.3 in part 1 is not included. 3: represents that bits 3 to 7 are not used for the watchdog timer. (note 1) (note 1) (note 1) 5 fig. 10.2.2 structure of oscillation circuit control regist er 1
chapter 11 chapter 11 stop and wait modes 11.1 overview 11.2 clock generating circuit 11.3 stop mode 11.4 wait mode
stop and w ait modes 7736 group users manual 11C2 11.2 clock generating circuit concerning chapter 11. stop and wait modes of the 7736 gro up, description differs depending on the external bus mode. in external bus mode a, refer to the corresponding sections in part 1; in external bus mode b, refer to the corresponding sections in part 2. note that, for the structu re of the oscillation circuit control register 1, refer to figure 11.2.3 in part 3. ? 11.1 overview external bus modes a and b (page 11-2 in part 1) ? 11.2 clock generating circuit external bus mode a (page 11-3 in part 1) external bus mode b (page 11-2 in part 2) ? 11.3 stop mode external bus mode a (page 11-6 in part 1) external bus mode b (page 11-3 in part 2) ? 11.4 wait mode external bus mode a (page 11-13 in part 1) external bus mode b (page 11-6 in part 2) bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to 0 (note 2) . clock prescaler reset bit 0 0 0 0 undefined 0 1 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input from the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown in figure 11.2.4 in part 1. by writing 1 to this bit, clock prescaler is initialized. rw 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. this bit is ignored. 2: the case where data 01010101 2 is written with the procedure shown in figure 11.2.4 in part 1 is not included. 3: represents that bits 3 to 7 are not used for the stop and wait modes. (note 1) (note 1) (note 1) 5 fig. 11.2.3 structure of oscillation circuit control registe r 1
chapter 12 chapter 12 connecting external devices 12.1 signals required for accessing external devices 12.2 software wait 12.3 ready function 12.4 hold function
connecting external devices 7736 group users manual 12C2 concerning chapter 12. connecting external devices, the 7736 group differs depending on the external bus mode. in external bus mode a, refer to the corresponding sections in part 1; in external bus mode b, refer to the corresponding sections in part 2. ? 12.1 signals required for accessing external devices external bus mode a (12-2 in part 1) external bus mode b (page 12-3 in part 2) ? 12.2 software wait external bus mode a (page 12-13 in part 1) external bus mode b (page 12-16 in part 2) ? 12.3 ready function external bus mode a (page 12-16 in part 1) external bus mode b (page 12-19 in part 2) ? 12.4 hold function external bus mode a (page 12-19 in part 1) external bus mode b (page 12-23 in part 2)
chapter 13 chapter 13 reset 13.1 hardware reset 13.2 software reset
reset 7736 group users manual 13C2 concerning chapter reset, the 7736 group differs from the 7733 group in the following section. therefore, only the differences are described in this chapter: ? 13.1 hardware reset the following section of the 7736 group is the same as that of the 7733 group. therefore, for this section, refer to part 1: ? 13.2 software reset (page 13-12 in part 1) 13.1 hardware reset concerning section 13.1 hardware reset, the 7736 group differs from the 7733 group in the following: ? table 13.1.1 ? figure 13.1.6 for external bus mode b (note) the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 13.1 hardware reset (page 13-2 in part 1) note: in external bus mode a, figure 13.1.6 of the 7736 group is the same as that of the 7733 group. 13.1 hardware reset mask rom version built-in prom version pin cnvsss level vss or vcc vss vss pin state floating h level is output. floating h level is output. floating ?floating when h level is applied to both or one of pins p5 1 and p5 2 ?h or l level is output when l level is applied to both of pins p5 1 and p5 2 . h level is output. ______ table 13.1.1 pin state while pin reset is at l level pin (port) name p0 to p10 _ ____ e/rde p0 to p10 _ ____ e/rde p0, p1, p3 to p10 p2 _ ____ e/rde
reset 7736 group users manual 13C3 13.1 hardware reset figure 13.1.6 for the 7736 group differs from that for the 7 733 group only in bit 3 at address 6f 16 . 0 ro uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address oscillation circuit control register 0 serial transmit control register a-d / uart2 trans./rece. interrupt control register uart0 transmission interrupt control register uart1 transmission interrupt control register int 2 /key input interrupt control register watchdog timer frequency selection flag register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw( ] 2) rw rw rw rw b7 b0 wo rw rw rw rw rw rw rw rw rw rw state immediately after reset ? ? ? ? ? 0 00 0 ? 0 ? ( ] 1) b7 b0 ? 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 port function control register uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register rw rw wo rw rw rw 00 0 0 0 1 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 ? ? ? 00 0 0 0 0 00 0 0 0 0 value fff 16 is set to the watchdog timer. (refer to chapter 10. watchdog timer in part 1. ) for access characteristics at address 6c 16 , also refer to figure 14.3.2 in part 1. do not write data to address 62 16 . n internal ram area (m37736mhbxxxfp: addresses 80 16 to fff 16 ) at hardware reset (not including the case where the stop or wait mode is te rminated)...undefined. at software reset...retains the state immediately before res et . when the stop or wait mode is terminated (when hardware reset is applied)...retains the state imme diately before the stp or wit i nstruction is executed. ? rw ] 3 0 0 0 ] 1 (reserved area) ] 3 memory allocation control register uart2 transmit/receive mode register uart2 baud rate register (brg2) uart2 transmission buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register oscillation circuit control register 1 rw 0 ? 0 00 0 rw ? 00 0 0 0 0 0 wo wo wo rw ro 1 00 0 rw rw ro ro 00 0 0 00 1 0 ro 00 0 00 0 ? rw ? ? 0 00 0 0 00 0 ? 0 ] 2 ] 3 fig. 13.1.6 state of sfr area and internal ram area immediat ely after reset (4)
reset 7736 group users manual 13C4 13.1 hardware reset memo
chapter 14 chapter 14 clock generating circuit 14.1 overview 14.2 oscillation circuit example 14.3 clock control
clock genera ting circuit 7736 group users manual 14-2 14.3 clock control concerning chapter 14. clock generating circuit, the 7736 group differs from the 7733 group in the following section. therefore, only the differences are d escribed in this chapter: ? 14.3 clock control the following sections of the 7736 group are the same as tho se of the 7733 group. therefore, for these sections, refer to part 1: ? 14.1 overview (page 14-2 in part 1) ? 14.2 oscillation circuit example (page 14-3 in part 1) 14.3 clock control concerning section 14.3 clock control, the 7736 group diff ers from that of the 7733 group in the following: ? figure 14.3.3 the other description is the same as that of the 7733 group. therefore, refer to part 1. ? 14.3 clock control (page 14-5 in part 1) bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to 0 (note 2) . clock prescaler reset bit 0 0 0 0 undefined 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillation circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is used when terminating stop mode. 1: sub clock is input from the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown in figure 14.3.4 in part 1. by writing 1 to this bit, clock prescaler is initialized. rw 1 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. this bit is ignored. 2: the case where data 01010101 2 is written with the procedure shown in figure 14.3.4 in part 1 is not included. 3: represents that bits 3 to 7 are not used for the clo ck generating circuit. (note 1) (note 1) (note 1) 5 fig. 14.3.3 structure of oscillation circuit control regist er 1
chapter 15 chapter 15 electrical characteristics 15.1 absolute maximum ratings 15.2 recommended operating conditions 15.3 electrical characteristics 15.4 a-d converter characteristics 15.5 internal peripheral devices 15.6 ready and hold 15.7 single-chip mode 15.8 memory expansion mode and microprocessor mode : with no wait 15.9 memory expansion mode and microprocessor mode : with wait 1 15.10 memory expansion mode and microprocessor mode : with wait 0 15.11 measuring circuit for ports p0 to p10 and pins f 1 _ and e
electrical characteristics 7736 group users manual 15C2 electrical characteristics of the m37736mhbxxxgp are describ ed in this chapter. concerning chapter 15. electrical characteristics, the 773 6 group differs from the 7733 group in the following sections. therefore, only the differe nces are described in this chapter: ? 15.1 absolute maximum ratings ? 15.2 recommended operating conditions ? 15.3 electrical characteristics ? 15.7 single-chip mode _ ? 15.11 measuring circuit for ports p0 to p10 and pins f 1 and e the following sections of the 7736 group differ depending on the external bus mode. in external bus mode a, refer to the corresponding sections in part 1; in ex ternal bus mode b, refer to the corresponding sections in part 2. ? 15.6 ready and hold external bus mode a (page 15-11 in part 1) external bus mode b (page 15-3 in part 2) ? 15.8 memory expansion mode and microprocessor mode : with no wait external bus mode a (page 15-15 in part 1) external bus mode b (page 15-5 in part 2) ? 15.9 memory expansion mode and microprocessor mode : with wait 1 external bus mode a (page 15-17 in part 1) external bus mode b (page 15-7 in part 2) ? 15.10 memory expansion mode and microprocessor mode : wit h wait 0 external bus mode a (page 15-19 in part 1) external bus mode b (page 15-9 in part 2) the following sections of the 7736 group are the same as tho se of the 7733 group. therefore, for these sections, refer to part 1: ? 15.4 a-d converter characteristics (page 15-5 in part 1) ? 15.5 internal peripheral devices (page 15-6 in part 1) 15.1 absolute maximum ratings absolute maximum ratings 15.1 absolute maximum ratings parameter power source voltage analog power source voltage input voltage input voltage output voltage power dissipation operating temperature storage temperature conditions ta = 25 c unit v v v v v mw c c symbol vcc avcc v i v i v o p d t opr t stg ratings C0.3 to 7 C0.3 to 7 C0.3 to 12 C0.3 to vcc+0.3 C0.3 to vcc+0.3 300 C20 to 85 C40 to 150 reset , cnvss, byte p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 7 , v ref , x in , bsel p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 , x out , e
electrical characteristics 7736 group users manual 15C3 15.2 recommended operating conditions recommended operating conditions (vcc = 5 v 10 %, ta = C20 to 85 c, unless otherwise noted) 15.2 recommended operating conditions f(x in ) :operating f(x in ) :stopped, f(x cin ) = 32.768 khz p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 7 , x in , reset , cnvss, byte, bsel, x cin (note 3) p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 7 , x in , reset , cnvss, byte, bsel, x cin (note 3) p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 3 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 4 Cp10 7 p4 4 Cp4 7 , p10 0 Cp10 3 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 3 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 4 Cp10 7 p4 4 Cp4 7 , p10 0 Cp10 3 parameter symbol limits min. max. 5.5 5.5 4.5 2.7 5.0 vcc 0 0 32.768 typ. unit 0.8 vcc 0.8 vcc vcc vcc vcc 0.2 vcc 0.2 vcc 0.16 vcc C10 C5 10 20 5 15 25 50 0.5 vcc 0 0 0 vcc avcc vss avss v ih v ih v ih v il v il v il i oh (peak) i oh (avg) i ol (peak) i ol (peak) i ol (avg) i ol (avg) f(x in ) f(x cin ) v v v v v v v v v v ma ma ma ma ma ma mhz khz power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage high-level input voltage high-level input voltage low-level input voltage low-level input voltage low-level input voltage high-level peak output current high-level average output current low-level peak output current low-level average output current main-clock oscillation frequency (note 4) sub-clock oscillation frequency low-level peak output current low-level average output current notes 1: average output current is the average value in an interval of 100 ms. 2: the sum of i ol (peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i oh (peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i ol (peak) for ports p4, p5, p6, and p7 must be 100 ma or less, and the sum of i oh (peak) for ports p4, p5, p6, and p7 must be 80 ma or less. 3: limits v ih and v il for x cin are applied when the sub clock external input selection bit = 1. 4: the maximum value of f(x in ) = 12.5 mhz when the main clock division selection bit = 1.
electrical characteristics 7736 group users manual 15C4 15.3 electrical characteristics electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) 15.3 electrical characteristics v oh v oh v oh v oh v ol v ol v ol v ol v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i il i il v ram symbol parameter measuring conditions min. max. limits unit C0.25 i oh = C10 ma i oh = C400 a i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i ol = 10 ma i ol = 20 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5 v v i = 0 v v i = 0 v, without a pull-up transistor v i = 0 v, with a pull-up transistor when clock is stopped 3 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 0.1 2 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 p3 0 Cp3 2 e p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 , p4 0 Cp4 3 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 5 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 4 Cp10 7 p4 4 Cp4 7 , p10 0 Cp10 3 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 p3 0 Cp3 2 e p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 7 , x in , reset , cnvss, byte, bsel p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 3 , p6 0 , p6 1 , p6 5 C p6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 3 , x in , reset , cnvss, byte, bsel p6 2 Cp6 4 , p10 4 Cp10 7 , hold , rdy , ta0 in Cta4 in , tb0 in Ctb2 in , int 0 C int 2 , ad trg , cts 0 , cts 1 , cts 2 , clk 0 , clk 1 , clk 2 , ki 0 C ki 3 v v v v v v v v v v v v v m a m a m a ma v typ. C0.5 2 2 0.45 1.9 0.43 1.6 0.4 1 0.5 0.4 0.4 5 C5 C5 C1.0 high-level output voltage high-level output voltage high-level output voltage high-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage hysteresis hysteresis reset hysteresis x in hysteresis x cin (when external clock is input) high-level input current low-level input current low-level input current ram hold voltage
electrical characteristics 7736 group users manual 15C5 max. 19 2.6 20 100 10 1 20 limits vcc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 12.5 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 5v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 1.5625 mhz), f(x cin ) : stopped, in operating (note 1) vcc = 5v, f(x in ) = 25 mhz (square waveform), f(x cin ) = 32.768 khz, when the wit instruction is executed (note 2) vcc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) vcc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when the wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped 15.3 electrical characteristics 15.4 a-d converter characteristics electrical characteristics (vcc= 5 v, vss = 0 v, ta = C20 to 85 c, unless otherwise noted) unit measuring conditions symbol parameter i cc power source current min. typ. 9.5 1.3 10 50 5 ma ma a a a a a in single-chip mode, output pins are open, and the other pins are con- nected to vss. notes 1: this is applied when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output disable selection bit = 1. 2: this is applied when the main clock external input selection bit = 1 and the system clock stop selection bit at wait state = 1. 3: this is applied when the cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4: this is applied when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1.
electrical characteristics 7736 group users manual 15C6 15.7 single-chip mode 15.7 single-chip mode timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. t c t w(h) t w(l) t r t f t su(p0dCe) t su(p1dCe) t su(p2dCe) t su(p3dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t su(p10dCe) t h(eCp0d) t h(eCp1d) t h(eCp2d) t h(eCp3d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) t h(eCp10d) min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits unit parameter 40 15 15 60 60 60 60 60 60 60 60 60 60 0 0 0 0 0 0 0 0 0 0 external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time port p0 input setup time port p1 input setup time port p2 input setup time port p3 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p10 input setup time port p0 input hold time port p1 input hold time port p2 input hold time port p3 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time port p10 input hold time symbol max. 8 8 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2: when the main clock division selection bit = 1, the minimum value of tc = 80 ns. 3: when the main clock division selection bit = 1, values of tw (h) /tc and tw (l) /tc must be set to values from 0.45 through 0.55. t d(eCp0q) t d(eCp1q) t d(eCp2q) t d(eCp3q) t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) t d(eCp9q) t d(eCp10q) port p0 data output delay time port p1 data output delay time port p2 data output delay time port p3 data output delay time port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time port p9 data output delay time port p10 data output delay time ns ns ns ns ns ns ns ns ns unit symbol max. 80 80 80 80 80 80 80 80 80 80 80 min. limits parameter switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note) , unless otherwise noted) measuring conditions fig. 15.11.1 note: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz.
electrical characteristics 7736 group users manual 15C7 15.7 single-chip mode t d(e?iq) t su(pid?) t h(e?id) t w(h) t c t r t f e port pi output port pi input (i = 0 to 10) x in t w(l) single-chip mode measuring conditions ? cc = 5 v 10 % ?nput timing voltage ?utput timing voltage : v il = 1.0 v, v ih = 4.0 v : v ol = 0.8 v, v oh = 2.0 v
electrical characteristics 7736 group users manual 15C8 __ 15.11 measuring circuit for ports p0 to p10 and pins f 1 and e __ 15.1 1 measuring circuit for ports p0 to p10 and pins f 1 and e __ fig. 15.11.1 measuring circuit for ports p0 to p10 and pins f 1 and e p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 50 pf e 1
chapter 16 chapter 16 standard characteristics 16.1 standard characteristics
standard characteristics 16.1 standard characteristics 7736 group users manual 16C2 concerning chapter 16. standard characteristics, the 7736 group differs from the 7733 group in the following sections. therefore, only the deferences are described in this chapter: ? 16.1.1 programmable i/o port (cmos output) standard characteristics: p0 to p3, p4 0 to p4 3 , p5 to p9, and p10 4 to p10 7 ? 16.1.2 programmable i/o port (cmos output) standard characteristics: p4 4 to p4 7 and p10 0 to p10 3 the following sections of the 7736 group are the same as those of the 7733 group. therefore, for these sections, refer to part 1: ?16.1.3 iccCf(x in ) standard characteristics (page 16-4 in part 1) ?16.1.4 a-d converter standard characteristics (page 16-5 in part 1)
standard characteristics 16.1 standard characteristics 7736 group users manual 16C3 16.1 standard characteristics standard characteristics described below are characteristic examples of the m37736mhbxxxgp and are not guaranteed. for each parameters limits, refer to chapter 15. electrical characteristics. 16.1.1 programmable i/o port (cmos output) standard characteristics: p0 to p3, p4 0 to p4 3 , p5 to p9, and p10 4 to p10 7 (1) p-channel i oh Cv oh characteristics (2) n-channel i ol Cv ol characteristics 50.0 40.0 30.0 10.0 20.0 0 1.0 2.0 3.0 4.0 5.0 ta = 25? ta = 85? power source voltage v cc = 5 v v oh [ v ] i oh [ ma ] p channel 50.0 40.0 30.0 20.0 10.0 0 1.0 2.0 3.0 4.0 5.0 ta = 25? ta = 85? power source voltage v cc = 5 v v ol [ v ] i ol [ ma ] n channel
standard characteristics 16.1 standard characteristics 7736 group users manual 16C4 16.1.2 programmable i/o port (cmos output) standard characteristics: p4 4 to p4 7 and p10 0 to p10 3 (1) p-channel i oh Cv oh characteristics power source voltage v cc = 5 v v oh [ v ] i oh [ ma ] p channel power source voltage v cc = 5 v v ol [ v ] i ol [ ma ] n channel 50.0 40.0 30.0 10.0 20.0 0 1.0 2.0 3.0 4.0 5.0 ta = 25? ta = 85? 50.0 40.0 30.0 20.0 10.0 0 1.0 2.0 3.0 4.0 5.0 ta = 25? ta = 85? (2) n-channel i ol Cv ol characteristics
chapter 17 chapter 17 applications 17.1 memory expansion 17.2 serial i/o 17.3 watchdog timer 17.4 power saving 17.5 timer b
17C2 applications 7736 group users manual concerning chapter 17. applications, the 7736 group differs from the 7733 group in the following section. therefore, only the differences are described in this chapter: ? 17.4 power saving the following section of the 7736 group differs depending on the external bus mode, which is a or b: ? 17.1 memory expansion external bus mode a (page 17C2 in part 1) external bus mode b (page 17C2 in part 2 ) the following sections of the 7736 group are the same as those of the 7733 group. therefore, for these sections, refer to part 1: ? 17.2 serial i/o (page 17C28 in part 1) ? 17.3 watchdog timer (page 17C41 in part 1) ? 17.5 timer b (page 17C54 in part 1)
17C3 applica tions 7736 group users manual 17.4 power saving 17.4 power saving power saving examples (in other words, examples to save powe r consumption) with the stop or wait mode used in external bus mode a are described below. the followi ng examples differ from examples in external bus mode b only in external bus pins allocated to ports p0 t o p3. therefore, for power saving in external bus mode b, refer to this section. 17.4.1 power saving example with stop mode used in this example, power saving is realized by using the stop mode. the stop mode is terminated by using the key input interrupt function. (1) specifications the microcomputer operates in the single-chip mode. pins p10 0 to p10 3 are used as output pins for the key matrix scanning. input pins ( ki 0 to ki 3 ) for the key input interrupt function are used as key input pins. pins ki 0 to ki 3 are pulled high by using the pull-up function. a the initial output levels of pins p10 0 to p10 3 are l. ? when a key input interrupt request occurs owing to a key pu sh, the key data is read-in. (this reading is surely performed independent of power saving.) ? in the stop mode, interrupts other than a key input interru pt are disabled. ? an external clock is used as the main clock.
17C4 applications 7736 group users manual 17.4 power saving (2) initial settings for related registers fig. 17.4.1 initial settings for related registers pins ki 0 to ki 3 are pulled high. port p10 direction register (address 18 16 ) pins p10 0 to p10 3 : output mode b7 b0 00 0 pins p10 4 to p10 7 ( ki 0 to ki 3 ): input mode 01111 x: it may be ??or ?. pins p10 0 to p10 3 ? output (scan output) level: ? b7 b0 port p10 register (address 16 16 ) 0000 key input interrupt function is selected. must be fixed to ?. b7 b0 port function control register (address 6d 16 ) 11 0 interrupt disable flag (i) b7 b0 int 2 /key input interrupt control register (address 7f 16 ) 0 00 interrupt priority level is set. (note that a value other than ?00 2 ?is set.) interrupt request bit: 0 (initialized) must be fixed to ?. ?? interrupt is enabled. must be fixed to ?. an external clock is selected as the main clock. watchdog timer is not used when the stop mode is terminated. oscillation circuit control register 1 (address 6f 16 ) (note) b7 b0 x 0 1 0 pin p6 4 / int 2 is not used for the key input interrupt. note: when writing a value to this register, write a value of ?5 16 ?by using the ldm instruction, and then write a value of ?a 16 .?(refer to figure 11.2.4. ) x x x x x
17C5 applica tions 7736 group users manual 17.4 power saving fig. 17.4.2 approximate flowchart interrupts other than a key input interrupt are disabled. notes 1: when pin v ref and resistor ladder network are connected, current flows in to the resistor ladder network. when using the a-d converter after the stop mode is terminat ed, do as follows: q reconnect pin v ref and resistor ladder network. w and then, start a-d conversion after a period of 1 s or more passed. when a port is connected to an external device and so on, th ere is a possibility that current consumption increases according to the ports level. in order to avoid t his problem, do as follows: ?when output mode is selected: fix the ports level to a lev el where no current flows into the external. ?when input mode is selected : pull the port high or low vi a a resistor. (floating state is disabled.) key input interrupt request occurs. (key is pushed.) main routine stp v ref connection selection bit 1 (bit 5 at address 1f 16 ) pin v ref is disconnected from resistor ladder network. (note 1) port level is fixed. (note 2) stop mode is selected. bits 2 to 0 at addresses 70 16 to 7e 16 000 2 2: key input ( int 2 ) interrupt routine key data is read-in. register return processing rti port p10 registers bits which correspond to pins p10 0 to p10 3 0 (bits 0 to 3 at address 16 16 ) scan output: l level port p10 registers bits which correspond to pins p10 0 to p10 3 0 (bits 0 to 3 at address 16 16 ) scan output: l level register save processing (3) approximate flowchart
17C6 applications 7736 group users manual (4) settings for performing power saving in memory expansion or microprocessor mode in the memory expansion or microprocessor mode, when saving power consumption, it is necessary to fix the i/o pins levels of the external bus and bus control signals in the stop mode. for this purpose, set the standby state selection bit to 1. 17.4 power saving
17C7 applica tions 7736 group users manual fig. 17.4.3 fixing i/o pins levels of external bus and bus control signals (microprocessor mode) note: regardless of this setting, in the following cases, pin 1 outputs l level in the stop mode: l when the signal output disable selection bit is set to 0 in the microprocessor mode l when the clock 1 output selection bit is set to 1 in the memory expansion mode stp v ref connection selection bit 1 (bit 5 at address 1f 16 ) pin v ref is disconnected from resistor ladder network. stop mode is selected. interrupt request occurs. port p0 register 00111111 2 (address 2 16 ) port p1 register 00000000 2 (address 3 16 ) port p2 register 00000000 2 (address 6 16 ) port p3 register 00001011 2 (address 7 16 ) levels of ports other than the above are fixed. signal output disable selection bit 1 (bit 6 at address 6c 16 ) i/o pins levels of external bus, chip-select signals and bus control signals in the stop mode are set. (these levels can be set by the corresponding port registers bits.) in this example, i/o pins for l-active signals are set to h and the other pins are set to l. ports which correspond to i/o pins of external bus, chip- select signals and bus control signals: output mode (this setting is done in order to output a value set to a port register in the stop mode) pin 1 s state in the stop mode is set (note) . in this example, l level output is set. pin e s output level in the stop mode is set. in this example, it is set to l. port p0 direction register ff 16 (address 4 16 ) port p1 direction register ff 16 (address 5 16 ) port p2 direction register ff 16 (address 8 16 ) port p3 direction register ff 16 (address 9 16 ) main routine port p4 registers bit which corresponds to p4 2 pin 0 (bit 2 at address a 16 ) port p4 direction registers bit which corresponds to p4 2 pin 1 (bit 2 at address c 16 ) standby state selection bit 1 (bit 0 at address 6d 16 ) standby state selection bit: 1 (in the stop mode, a value which is set to the corresponding port register is output from an i/o pin of the external bus, chip-select signals or bus control signals.) 17.4 power saving
17C8 applica tions 7736 group users manual 17.4.2 power saving example with wait mode used in this example, power saving is realized by using the wait mode. while power is saved, the clock function is realized by using the clock timer (timer b2). (1) specifications the microcomputer operates in the single-chip mode. the frequency of the sub clock (f(x cin )) = 32.768 khz. an external clock is used as the sub clock. a clock counting is performed by using the clock timer. (an i nterrupt request occurs every second.) ? when an int 0 interrupt request occurs (note) , the wait mode is terminated. note: an interrupt request occurs at every falling edge of the si gnal input from pin int 0 . ? in the wait mode, interrupts other than the following inter rupts are disabled. ?timer b2 interrupt ? int 0 interrupt ? an external input is used as the main clock. 17.4 power saving
17C9 applica tions 7736 group users manual (2) initial settings for related registers fig. 17.4.4 initial settings for related registers x: it may be 0 or 1. b7 b0 timer b2 interrupt control register (address 7c 16 ) interrupt priority level is set. (note that a value other th an 000 2 is set.) 0 interrupt request bit: 0 (initialized) interrupt disable flag (i) 0: interrupt is enabled. b7 b0 int 0 interrupt control register (address 7d 16 ) interrupt priority level is set. (note that a value other th an 000 2 is set.) 0 interrupt request bit: 0 (initialized) 0 0 an interrupt request occurs at the falling edge. interval of the clock timers interrupt request occurrence: 1 second b15 b8 timer b2 register (addresses 55 16 and 54 16 ) 03 16 b7 b0 ff 16 settings for the clock timer. b7 b0 timer b2 mode register (address 5d 16 ) x 0 101 the sub-clock oscillation circuit: oscillating (timer b2 functions as the clock timer.) b7 b0 oscillation circuit control register 0 (address 6c 16 ) 1 in the wait mode, clocks 2 to 512 are stopped. 1 x xx an external clock is selected as the main clock. watchdog timer is not used when the stop mode is terminated. b7 b0 oscillation circuit control register 1 (address 6f 16 ) 0 xx 1 1 an external clock is selected as the sub clock and p7 6 functions as a port. watchdog timer is not used when the stop mode is terminated. must be fixed to 0. note: when writing a value to this register, write a value of 55 16 by using the ldm instruction, and then write a value of 0a 16 . (refer to figure 11.2.4. ) 17.4 power saving
17C10 applications 7736 group users manual (3) approximate flowchart fig. 17.4.5 approximate flowchart (1) [f_wit]: flag used to determine whether an int 0 interrupt request has occurred or not main clock oscillation circuit: oscillating <> main routine system clock selection bit ? (bit 3 at address 6c 16 ) system clock: main clock sub clock <> v ref connection selection bit ? (bit 5 at address 1f 16 ) pin v ref is disconnected from resistor ladder network. (note 1) port level is fixed. (note 2) wait mode is selected. main clock stop bit ? (bit 2 at address 6c 16 ) main clock oscillation circuit: stopped <> main clock stop bit ? (bit 2 at address 6c 16 ) 0: int 0 interrupt [f_wit] ? clock timer interrupt request occurs. [f_wit] = ?? ? ?? clock timer interrupt wit int 0 interrupt request occurs. (by this setting, the wait mode is terminated only when an int 0 interrupt request occurs.) bits 2 to 0 at addresses 70 16 to 7b 16 , 7e 16 , and 7f 16 ?00 2 interrupts other than timer b2 and int 0 interrupts are disabled. timer b2 count start flag ? (bit 7 at address 40 16 ) clock timer starts counting . system clock selection bit ? (bit 3 at address 6c 16 ) system clock: sub clock main clock (note 3) <> <> <> <> <>: refer to figure 17.4.8. for notes 1 to 3 , refer to the next page. 17.4 power saving
17C11 applica tions 7736 group users manual fig. 17.4.6 approximate flowchart (2) notes 1: when pin v ref and resistor ladder network are connected, current flows in to the resistor ladder network. when using the a-d converter after the wait mode is terminat ed, do as follows: q reconnect pin v ref and resistor ladder network. w and then, start a-d conversion after a period of 1 s or more passed. 2: when a port is connected to an external device and so on, th ere is a possibility that current consumption increases according to the ports level. in order to avoid this problem, do as follows: ?when output mode is selected: fix the ports level to a lev el where no current flows into the external. ?when input mode is selected: pull the port high or low via a resistor. (floating state is disabled.) 3: do not switch the system clock until oscillation of a clock which is input from the external is stabilized. timer b2 interrupt routine register save processing clock count register return processing rti int 0 interrupt routine register save processing [f_wit] 0 register return processing rti [f_wit]: flag used to determine whether an int 0 interrupt request has occurred or not 17.4 power saving
17C12 applications 7736 group users manual main clock sub clock system clock system clock selection bit main clock stop bit <> <> <> <> ? ? ? ? main clock sub clock main clock fig. 17.4.7 state of main clock, sub clock, and system clock 17.4 power saving
chapter 18 chapter 18 low voltage version 18.1 performance overview 18.2 pin configuration 18.3 functional description 18.4 electrical characteristics 18.5 standard characteristics 18.6 applications
18-2 low voltage version concerning chapter 18. low voltage version, the 7736 group differs from the 7733 group in the following sections. therefore, only the differences are desc ribed in this chapter: ? 18.1 performance overview ? 18.2 pin configuration ? 18.3 functional description ? 18.4 electrical characteristics ? 18.5 standard characteristics ? 18.6 applications 7736 group users manual
low voltage version 7736 group users manual 18-3 18.1 performance overview concerning section 18.1 performance overview, the 7736 group differs from the 7733 group in the follow- ing: ? table 18.1.1: programmable i/o ports, output port, memory expansion, and package the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 18.1 performance overview (page 18-3 in part 1) table 18.1.1 m37736mhlxxxhp performance overview items programmable i/o ports output port memory expansion package performance 8 bits 5 8 4 bits 5 1 8 bits 5 1 possible ? external bus mode a: maximum of 16 mbytes ? external bus mode b: maximum of 1 mbytes 100-pin plastic molded fine-pitch qfp ports p0Cp2, p4Cp8, p10 port p3 port p9 18.1 performance overview
18-4 low voltage version 18.2 pin configuration figure 18.2.1 shows the m37736mhlxxxhp pin configuration. fig. 18.2.1 m37736mhlxxxhp pin configuration (top view) 46 47 48 49 50 21 22 23 24 25 p3 2 /ale p3 1 /bhe/weh p3 3 /hlda x out v ss cnv ss reset p4 0 /hold 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p0 0 /a 0 /cs 0 p0 1 /a 1 /cs 1 p0 2 /a 2 /cs 2 p0 3 /a 3 /cs 3 p0 4 /a 4 /cs 4 p0 5 /a 5 /rsmp p0 6 /a 6 /a 16 p0 7 /a 7 /a 17 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 p1 7 /a 15 /d 15 p2 0 /a 16 /a 0 /d 0 p2 1 /a 17 /a 1 /d 1 p2 2 /a 18 /a 2 /d 2 55 54 53 52 51 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 75 74 73 95 94 93 92 91 89 88 87 86 85 90 100 99 98 97 96 84 83 82 81 35 31 32 33 34 36 37 38 39 40 41 26 28 27 29 30 42 43 44 45 p4 1 /rdy p4 2 / 1 byte x in v cc p3 0 /r/w/wel p2 7 /a 23 /a 7 /d 7 p2 6 /a 22 /a 6 /d 6 p2 5 /a 21 /a 5 /d 5 p2 4 /a 20 /a 4 /d 4 p2 3 /a 19 /a 3 /d 3 p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out p4 7 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p9 0 /cts 2 p9 1 /clk 2 p8 0 /cts 0 /rts 0 /clks 1 p8 1 /clk 0 p8 2 /r x d 0 /clks 0 p8 3 /t x d 0 p8 4 /cts 1 /rts 1 av ss v ref av cc v cc p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 /ad trg p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 p7 4 /an 4 p6 6 /tb1 in p6 7 /tb2 in / sub p7 0 /an 0 m37736mhlxxxhp p4 5 p4 6 1 2 3 4 5 outline 100p6d-a 80 79 78 77 76 p10 7 /ki 3 p10 6 /ki 2 p10 5 /ki 1 p10 4 /ki 0 p10 3 p10 2 p10 1 p10 0 p4 3 p4 4 bsel e/rde evl1 evl0 p9 2 /r x d 2 p9 3 /t x d 2 p9 4 p9 5 p9 6 p9 7 v ss 18.2 pin configuration 7736 group users manual
low voltage version 7736 group users manual 18-5 18.3 functional description the m37736mhlxxxhp has the same functions as the m37736mhbxxxgp except for the power-on reset conditions. for the power-on reset conditions, refer to section 18.3.1 in part 1. for the other functions, refer to the corresponding chapters in parts 2 and 3: ? part 2 : chapters 4. interrupts to 9. a-d converter ? part 3 : chapters 2. central processing unit, 3. programmable i/o ports, 8. serial i/ o to 14. clock generating circuit 18.3 functional description
low volt age version 7736 group users manual 18C6 18.4 electrical characteristics 18.4 electrical characteristics concerning section 18.4 electrical characteristics, the 77 36 group differs from the 7733 group in the following sections: ? 18.4.1 absolute maximum ratings ? 18.4.2 recommended operating conditions ? 18.4.3 electrical characteristics ? 18.4.7 single-chip mode __ ? 18.4.11 measuring circuit for ports p0 to p10 and pins f 1 and e the following sections of the 7736 group differ depending on the external bus mode. in external bus mode a, refer to the corresponding sections in part 1; in externa l bus mode b, refer to the corresponding sections in part 2. ? 18.4.6 ready and hold external bus mode a (page 18-16 in part 1) external bus mode b (page 18-5 in part 2) ? 18.4.8 memory expansion mode and microprocessor mode : wi th no wait external bus mode a (page 18-20 in part 1) external bus mode b (page 18-7 in part 2) ? 18.4.9 memory expansion mode and microprocessor mode : wi th wait 1 external bus mode a (page 18-22 in part 1) external bus mode b (page 18-9 in part 2) ? 18.4.10 memory expansion mode and microprocessor mode : w ith wait 0 external bus mode a (page 18-24 in part 1) external bus mode b (page 18-11 in part 2) the following sections of the 7736 group are the same as tho se of the 7733 group. therefore, for these sections, refer to part 1: ? 18.4.4 a-d converter characteristics (page 18-10 in part 1) ? 18.4.5 internal peripheral devices (page 18-11 in part 1 )
low voltage version 7736 group users manual 18C7 18.4 electrical characteristics 18.4.1 absolute maximum ratings absolute maximum ratings parameter power source voltage analog power source voltage input voltage input voltage output voltage power dissipation operating temperature storage temperature conditions ta = 25 c unit v v v v v mw c c ratings C0.3 to 7 C0.3 to 7 C0.3 to 12 C0.3 to vcc+0.3 C0.3 to vcc+0.3 200 C40 to 85 C65 to 150 ______ reset , cnvss, byte p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 7 , v ref , x in , bsel p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , __ p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 , x out , e symbol vcc avcc v i v i v o p d t opr t stg
low voltage version 7736 group users manual 18C8 18.4 electrical characteristics 18.4.2 recommended operating conditions recommended operating conditions (vcc = 2.7 to 5.5 v, ta = C40 to 85 c, unless otherwise noted) v v v v v v v v v v ma ma ma ma ma ma mhz khz power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage high-level input voltage high-level input voltage low-level input voltage low-level input voltage low-level input voltage high-level peak output current high-level average output current low-level peak output current low-level peak output current low-level average output current low-level average output current main-clock oscillation frequency (note 4) sub-clock oscillation frequency vcc avcc vss avss v ih v ih v ih v il v il v il i oh (peak) i oh (avg) i ol (peak) i ol (peak) i ol (avg) i ol (avg) f(x in ) f(x cin ) parameter symbol limits min. max. 5.5 5.5 2.7 2.7 typ. unit 0.8 vcc 0.8 vcc vcc vcc vcc 0.2 vcc 0.2 vcc 0.16 vcc C10 C5 10 16 5 12 12 50 0.5 vcc 0 0 0 f(x in ) :operating f(x in ) :stopped, f(x cin ) = 32.768 khz p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 7 , x in , reset , cnvss, byte, bsel, x cin (note 3) p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 7 , x in , reset , cnvss,byte, bsel, x cin (note 3) p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 3 , p5 4 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 4 Cp10 7 p4 4 Cp4 7 , p10 0 Cp10 3 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 3 , p5 4 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 4 Cp10 7 p4 4 Cp4 7 , p10 0 Cp10 3 vcc 0 0 32.768 notes 1: average output current is the average value of an interval of 100 ms. 2: the sum of i ol (peak) for ports p0, p1, p2, p3, p8 and p9 must be 80 ma or less, the sum of i oh (peak) for ports p0, p1, p2, p3, p8 and p9 must be 80 ma or less, the sum of i ol (peak) for ports p4, p5, p6, p7 and p10 must be 100 ma or less, and the sum of i oh (peak) for ports p4, p5, p6, p7 and p10 must be 80 ma or less. 3: limits v ih and v il for x cin are applied when the sub clock external input selection bit = 1. 4: the maximum value of f(x in ) = 6 mhz when the main clock division selection bit = 1.
low voltage version 7736 group users manual 18C9 18.4 electrical characteristics 18.4.3 electrical characteristics electrical characteristics (vcc = 5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz, unless otherwise noted) high-level output voltage high-level output voltage high-level output voltage high-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage hysteresis hysteresis reset hysteresis x in hysteresis x cin (when external clock is input) high-level input current low-level input current low-level input current ram hold voltage symbol parameter test conditions min. max. v v v v v v v v v v v v v m a m a m a ma v limits unit typ. p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 p3 0 Cp3 2 _ e p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 , p4 0 Cp4 3 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 5 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 4 Cp10 7 p4 4 Cp4 7 , p5 0 Cp5 3 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 3 p3 0 Cp3 2 e p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 7 , x in , reset , cnvss, byte, bsel p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 , p6 1 , p6 5 C p6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p10 0 Cp10 7 , x in , reset , cnvss, byte, bsel p6 2 Cp6 4 , p10 4 Cp10 7 3 2.5 4.7 3.1 4.8 2.6 3.4 4.8 2.6 0.4 0.1 0.2 0.1 0.1 0.06 0.1 0.06 C0.25 C0.08 2 v oh v oh v oh v oh v ol v ol v ol v ol v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i il i il v ram 2 0.5 1.8 1.5 0.45 1.9 0.43 0.4 1.6 0.4 0.4 1 0.7 0.5 0.4 0.4 0.26 0.4 0.26 5 4 C5 C4 C5 C4 C1.0 C0.35 hold , rdy , ta0 in Cta4 in , tb0 in Ctb2 in , int 0 C int 2 , ad trg , cts 0 , cts 1 , cts 2 , clk 0 , clk 1 , clk 2 , ki 0 C ki 3 vcc = 5 v vcc = 3 v vcc = 5 v vcc = 3 v vcc = 5 v, i oh = C10 ma vcc = 3 v, i oh = C1 ma vcc = 5 v, i oh = C400 a vcc = 5 v, i oh = C10 ma vcc = 5 v, i oh = C400 m a vcc = 3 v, i oh = C1 ma vcc = 5 v, i oh = C10 ma vcc = 5 v, i oh = C400 m a vcc = 3 v, i oh = C1 ma vcc = 5 v, i ol = 10 ma vcc = 3 v, i ol = 1 ma vcc = 5 v, i ol = 16 ma vcc = 3 v, i ol = 10 ma vcc = 5 v, i ol = 2 ma vcc = 5 v, i ol = 10 ma vcc = 5 v, i ol = 2 ma vcc = 3 v, i ol = 1 ma vcc = 5 v, i ol = 10 ma vcc = 5 v, i ol = 2 ma vcc = 3 v, i ol = 1 ma vcc = 5 v vcc = 3 v vcc = 5 v vcc = 3 v vcc = 5 v vcc = 3 v vcc = 5 v vcc = 3 v vcc = 5 v, v i = 5 v vcc = 3 v, v i = 3 v vcc = 5 v, v i = 0 v vcc = 3 v, v i = 0 v v i = 0 v, without a pull-up transistor v i = 0 v, with a pull-up transistor when clock is stopped C0.5 C0.18
low voltage version 7736 group users manual 18C10 18.4 electrical characteristics limits vcc = 5 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 6 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 3 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 6 mhz), f(x cin ) = 32.768 khz, in operating (note 1) vcc = 3 v, f(x in ) = 12 mhz (square waveform), (f(f 2 ) = 0.75 mhz), f(x cin ) : stopped, in operating (note 1) vcc = 3v, f(x in ) = 12 mhz (square waveform), f(x cin ) = 32.768 khz, when the wit instruction is executed (note 2) vcc = 3 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) vcc = 3 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when the wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped electrical characteristics (vcc= 5 v, vss = 0 v, ta = C40 to 85 c, unless otherwise noted) unit measuring conditions symbol parameter i cc power source current min. typ. 4.5 3 0.4 6 30 3 ma ma ma a a a a a max. 9 6 0.8 12 60 6 1 20 notes 1: this is applied when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output disable selection bit = 1. 2: this is applied when the main clock external input selection bit = 1 and the system clock stop bit at wait state = 1. 3: this is applied when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4: this is applied when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1. in single-chip mode, output pins are open, and the other pins are connected to vss.
low voltage version 7736 group users manual 18C11 18.4 electrical characteristics 18.4.7 single-chip mode timing requirements (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note 1) , unless otherwise noted) h the rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. t c t w(h) t w(l) t r t f t su(p0dCe) t su(p1dCe) t su(p2dCe) t su(p3dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t su(p10dCe) t h(eCp0d) t h(eCp1d) t h(eCp2d) t h(eCp3d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) t h(eCp10d) min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits unit parameter 83 33 33 200 200 200 200 200 200 200 200 200 200 0 0 0 0 0 0 0 0 0 0 external clock input cycle time (note 2) external clock input high-level pulse width (note 3) external clock input low-level pulse width (note 3) external clock rise time external clock fall time port p0 input setup time port p1 input setup time port p2 input setup time port p3 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p10 input setup time port p0 input hold time port p1 input hold time port p2 input hold time port p3 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time port p10 input hold time symbol max. 15 15 notes 1: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz. 2: when the main clock division selection bit = 1, the minimum value of tc = 166 ns. 3: when the main clock division selection bit = 1, values of tw (h) /tc and tw (l) /tc must be set to values from 0.45 through 0.55. t d(eCp0q) t d(eCp1q) t d(eCp2q) t d(eCp3q) t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) t d(eCp9q) t d(eCp10q) port p0 data output delay time port p1 data output delay time port p2 data output delay time port p3 data output delay time port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time port p9 data output delay time port p10 data output delay time ns ns ns ns ns ns ns ns ns ns ns unit symbol max. 300 300 300 300 300 300 300 300 300 300 300 min. limits parameter switching characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C40 to 85 c, f(x in ) = 12 mhz (note) , unless otherwise noted) measuring conditions fig. 18.4.1 note: this is applied when the main clock division selection bit = 0 and f(f 2 ) = 6 mhz.
low volt age version 7736 group users manual 18C12 18.4 electrical characteristics t d(eCp0q) t su(p0dCe) t h(eCp0d) t w(h) t c t r t f e port pi output port pi input (i = 0 to 10) x in t w(l) single-chip mode measuring conditions ?v cc = 2.7 to 5.5 v ?input timing voltage ?output timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc : v ol = 0.8 v, v oh = 2.0 v
low vol t age version 7736 group users manual 18C13 18.4 electrical characteristics _ fig. 18.4.1 measuring circuit for ports p0 to p10 and pins f 1 and e p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 50 pf e 1 __ 18.4.11 measuring circuit for ports p0 to p10 and pins f 1 and e
low volt age version 7736 group users manual 18C14 18.5 standard characteristics concerning section 18.5 standard characteristics, the 7736 group differs from the 7733 group in the following sections. therefore, only the differences are desc ribed in this section: ? 18.5.1 programmable i/o port (cmos output) standard chara cteristics: p0 to p3, p4 0 to p4 3 , p5 to p9, and p10 4 to p10 7 ? 18.5.2 programmable i/o port (cmos output) standard chara cteristics: p4 4 to p4 7 and p10 0 to p10 3 the other description is the same as that of the 7736 group. therefore, refer to part 1: ?18.5 standard characteristics (page 18-27 in part 1) standard characteristics described below are characteristics examples of the m37736mhlxxxhp and are not guaranteed. for each parameters limits, refer to sectio n 18.4 electrical characteristics. 18.5.1 programmable i/o port (cmos output) standard characte ristics: ports p0 to p3, p4 0 Cp4 3 , p5Cp9 and p10 4 Cp10 7 (1) p-channel i oh Cv oh characteristics (2) n-channel i ol Cv ol characteristics v oh [v] p-channel power source voltage v cc = 3 v 20.0 16.0 12.0 4.0 8.0 0 0.6 1.2 1.8 2.4 3.0 i oh [ma] ta = 25 c ta = 85 c n-channel power source voltage v cc = 3 v 20.0 16.0 12.0 8.0 4.0 0 0.6 1.2 1.8 2.4 3.0 v ol [v] i ol [ma] ta = 25 c ta = 85 c 18.5 standard characteristics
low voltage version 7736 group users manual 18C15 18.5.2 programmable i/o port (cmos output) standard characteristics: ports p4 4 to p4 7 and p5 0 to p5 3 (1) p-channel i oh Cv oh characteristics (2) n-channel i ol Cv ol characteristics v oh [v] p-channel power source voltage v cc = 3 v 20.0 16.0 12.0 4.0 8.0 0 0.6 1.2 1.8 2.4 3.0 i oh [ma] ta = 25 ? ta = 85 ? n-channel power source voltage v cc = 3 v 20.0 16.0 12.0 8.0 4.0 0 0.6 1.2 1.8 2.4 3.0 v ol [v] i ol [ma] ta = 25 ? ta = 85 ? 18.5 standard characteristics
low volt age version 7736 group users manual 18C16 18.6 applications in external bus mode a, section 18.6 applications is the s ame as that of the 7733 group. therefore, refer to part 1: ? 18.6 applications (page 18-32 in part 1) in external bus mode b, section 18.6 applications is the s ame as that of the 7735 group. therefore, refer to part 2: ? 18.6 applications (page 18-13 in part 2) 18.6 applications
chapter 19 chapter 19 built-in prom version 19.1 eprom mode 19.2 usage precaution
built-in prom version 7736 group users manual 19-2 19.1 eprom mode 19.1 eprom mode concerning chapter 19. built-in prom version, the 7736 group differs from the 7733 group in the following section. therefore, only the differences are described in this chapter: ? 19.1 eprom mode the following section is the same as that of the 7733 group. therefore, for this section, refer to part 1: ? 19.2 usage precaution (page 19-10 in part 1) 19.1 eprom mode concerning section 19.1 eprom mode, the 7736 group differs from the 7733 group in the following: ? table 19.1.1 ? figures 19.1.1 and 19.1.2 the other description is the same as that of the 7733 group. therefore, refer to part 1: ? 19.1 eprom mode (page 19-3 in part 1) functions connect to vss. connect to vss. connect to pin vcc. left open. pin p9 0 Cp9 7 p10 0 Cp10 7 bsel evl0, evl1 input/output input input input output name input port p9 input port p10 bus select input CC table 19.1.1 pin description in eprom mode
built-in prom version 7736 group users manual 19-3 19.1 eprom mode fig. 19.1.1 pin connections in eprom mode (m37736ehbgp) 86 p8 2 /rxd 0 /clks 0 87 p8 1 /clk 0 1 p6 6 /tb1 in 2 p6 5 /tb0 in 3 p6 4 /int 2 4 p6 3 /int 1 5 p6 2 /int 0 6 p6 1 /ta4 in 7 p6 0 /ta4 out 8 9 10 p5 7 /ta3 in 11 p5 6 /ta3 out 12 p5 5 /ta2 in 13 p5 4 /ta2 out 14 p5 3 /ta1 in 15 p5 2 /ta1 out 16 p5 1 /ta0 in 17 p5 0 /ta0 out 18 p10 7 /ki 3 19 p10 6 /ki 2 20 p10 5 /ki 1 21 p10 4 /ki 0 22 p10 3 23 24 100 p7 0 /an 0 99 p7 2 /an 2 98 p7 3 /an 3 97 p7 4 /an 4 96 p7 5 /an 5 /ad trg 95 p7 6 /an 6 /x cout 94 p7 7 /an 7 /x cin 93 v ss 92 av ss 91 v ref 90 av cc 89 v cc 88 p8 0 /cts 0 /rts 0 /clks 1 85 p8 3 /txd 0 m37736ehbgp oe ce p4 1 /rdy pgm v cc p6 7 /tb2 in / sub 45 p2 5 /a 21 /a 5 /d 5 44 p2 6 /a 22 /a 6 /d 6 31 p4 0 /hold 32 byte 33 cnv ss 34 bsel 35 x in 36 x out 37 e/rde 38 v ss 39 p3 3 /hlda 40 p3 2 /ale 41 p3 1 /beh/weh 42 p3 0 /r/w/wel 43 p2 7 /a 23 /a 7 /d 7 46 v pp d 5 d 6 d 7 v ss * a 16 25 26 27 28 29 30 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 p4 7 p10 0 p10 2 p10 1 reset v cc evl1 evl 0 49 48 47 50 75 p9 4 74 p9 5 73 p9 6 72 p9 7 71 p0 0 /a 0 /cs 0 70 p0 1 /a 1 /cs 1 69 p0 2 /a 2 /cs 2 68 p0 3 /a 3 /cs 3 67 p0 4 /a 4 /cs 4 66 p0 5 /a 5 /rsmp 65 p0 6 /a 6 /a 16 64 p0 7 /a 7 /a 17 63 p1 0 /a 8 /d 8 62 p1 1 /a 9 /d 9 61 p1 2 /a 10 /d 10 60 p1 3 /a 11 /d 11 59 p1 4 /a 12 /d 12 58 p1 5 /a 13 /d 13 57 p1 6 /a 14 /d 14 56 p1 7 /a 15 /d 15 55 p2 0 /a 16 /a 0 /d 0 54 p2 1 /a 17 /a 1 /d 1 53 p2 2 /a 18 /a 2 /d 2 52 p2 3 /a 19 /a 3 /d 3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 9 a 10 a 11 a 12 a 13 a 14 d 0 d 1 d 2 d 3 a 15 51 p2 4 /a 20 /a 4 /d 4 d 4 80 p8 7 /txd 1 79 p9 0 /cts 2 78 p9 1 /clk 2 77 p9 2 /rxd 2 76 p9 3 /txd 2 p7 1 /an 1 82 83 84 81 p8 6 /rxd 1 p8 5 /clk 1 p8 4 /cts 1 /rts 1 outline 100p6s-a * : connect these pins to a resonator or an oscillator. : eprom pin.
built-in prom version 7736 group users manual 19-4 19.1 eprom mode 85 5 86 p8 2 /rxd 0 /clks 0 87 p8 1 /clk 0 1 p6 6 /tb1 in 2 p6 5 /tb0 in 3 p6 4 /int 2 4 p6 3 /int 1 5 p6 2 /int 0 6 p6 1 /ta4 in 7 p6 0 /ta4 out 8 9 10 p5 7 /ta3 in 11 p5 6 /ta3 out 12 p5 5 /ta2 in 13 p5 4 /ta2 out 14 p5 3 /ta1 in 15 p5 2 /ta1 out 16 p5 1 /ta0 in 17 p5 0 /ta0 out 18 p10 7 /ki 3 19 p10 6 /ki 2 20 p10 5 /ki 1 21 p10 4 /ki 0 22 p10 3 23 24 100 0 p7 0 /an 0 99 p7 2 /an 2 98 p7 3 /an 3 97 p7 4 /an 4 96 p7 5 /an 5 /ad trg 95 p7 6 /an 6 /x cout 94 4 p7 7 /an 7 /x cin 93 3 v ss 92 2 av ss 91 1 v ref 90 0 av cc 89 v cc 88 p8 0 /cts 0 /rts 0 /clks 1 p8 3 /txd 0 m37736ehlhp oe ce p4 1 /rdy pgm v cc p6 7 /tb2 in / sub 45 p2 5 /a 21 /a 5 /d 5 44 p2 6 /a 22 /a 6 /d 6 31 p4 0 /hold 32 byte 33 cnv ss 34 bsel 35 x in 36 x out 37 e/rde 38 v ss 39 p3 3 /hlda 40 p3 2 /ale 41 p3 1 /beh/weh 42 p3 0 /r/w/wel 43 p2 7 /a 23 /a 7 /d 7 46 v pp d 5 d 6 d 7 v ss * a 16 25 26 27 28 29 30 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 p4 7 p10 0 p10 2 p10 1 reset v cc evl1 evl 0 49 48 47 50 75 p9 4 74 p9 5 73 p9 6 72 p9 7 71 p0 0 /a 0 /cs 0 70 p0 1 /a 1 /cs 1 69 p0 2 /a 2 /cs 2 68 p0 3 /a 3 /cs 3 67 p0 4 /a 4 /cs 4 66 p0 5 /a 5 /rsmp 65 p0 6 /a 6 /a 16 64 p0 7 /a 7 /a 17 63 p1 0 /a 8 /d 8 62 p1 1 /a 9 /d 9 61 p1 2 /a 10 /d 10 60 p1 3 /a 11 /d 11 59 p1 4 /a 12 /d 12 58 p1 5 /a 13 /d 13 57 p1 6 /a 14 /d 14 56 p1 7 /a 15 /d 15 55 p2 0 /a 16 /a 0 /d 0 54 p2 1 /a 17 /a 1 /d 1 53 p2 2 /a 18 /a 2 /d 2 52 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 9 a 10 a 11 a 12 a 13 a 14 d 0 d 1 d 2 a 15 51 p2 3 /a 19 /a 3 /d 3 d 3 p2 4 /a 20 /a 4 /d 4 d 4 80 79 78 77 p9 2 /rxd 2 76 p9 3 /txd 2 p8 7 /txd 1 p9 0 /cts 2 p9 1 /clk 2 p7 1 /an 1 82 83 84 81 p8 6 /rxd 1 p8 5 /clk 1 p8 4 /cts 1 /rts 1 outline 100p6d-a * : connect these pins to a resonator or an oscillator. : eprom pin. fig. 19.1.2 pin connections in eprom mode (m37736ehlhp)
appendix appendix appendix 1. memory allocation of 7736 group appendix 2. memory allocation in sfr area appendix 3. control registers appendix 4. package outlines appendix 5. hexadecimal instruction code table appendix 6. machine instructions appendix 7. examples of handling unused pins appendix 8. countermeasure examples against noise appendix 9. q & a
appendix 7736 group user? manual 20-2 concerning chapter ?ppendix,?the 7736 group differs from t he 7733 group in the following secti o therefore, only the differences are described in this chapte r: ??ppendix 1. memory allocation of 7736 group ??ppendix 2. memory allocation in sfr area ??ppendix 3. control registers ??ppendix 4. package outlines ??ppendix 7. examples of handling unused pins note: the following sections of the 7736 group are the same as th ose of the 7733 group. therefore, f these sections, refer to part 1: ??ppendix 5. hexadecimal instruction code table? ( page 21-41 in part 1 ) ??ppendix 6. machine instructions ( page 21-44 in part 1 ) ??ppendix 8. countermeasure examples against noise ( page 21-61 in part 1 ) ??ppendix 9. q & a? ( page 21-71 in part 1 )
appendix 7736 group users manual 20-3 appendix 1. memory allocation of 7736 group 1. m37736mhbxxxgp, m37736ehbxxxgp, m37736ehbgs, m37736mhlxxx hp, m37736ehlxxxhp fig. 1 memory allocation of m37736mhbxxxgp, m37736ehbxxxgp, m37736ehbgs, m37736mhlxxxhp, m37736ehlxxxhp (1) appendix 1. memory allocation of 7736 group 0 1 ffff 16 000000 16 00007f 16 000080 16 000f f f 16 ffffff 16 001000 16 0 0 ffff 16 010000 16 002000 16 000000 16 00007f 16 000080 16 000f f f 16 0 0 ffff 16 010000 16 0 1 ffff 16 ffffff 16 000000 16 00007f 16 i nt 1 i nt 0 db c r eset 0 0 ffd 6 16 0 0 fffe 16 sfr area internal ram area 3968 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 60 kbytes internal rom area 64 kbytes bank 2 16 (4 kbytes) a-d/uart2 trans./rece. uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input watchdog timer brk instruction zero divide interrupt vector table sfr area internal ram area 3968 bytes internal rom area 56 kbytes internal rom area 64k bytes peripheral device control registers (sfr) ? memory allocation selection bits (b2, b1, b0)=(0, 0, 0) ? rom size: 124 kbytes ? ram size: 3.9 kbytes ? memory allocation selection bits (b2, b1, b0)=(0, 0, 1) ? rom size: 120 kbytes ? ram size: 3.9 kbytes uart0 transmission : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode notes 1: access to internal rom area is disabled in the microprocess or mode. (refer to section 2.5 processor modes in part 1 . ) 2 : in external bus mode b, banks 10 16 to ff 16 cannot be accessed. refer to appendix 2 in part 1. 020000 16 0 2 ffff 16 f f 0000 16 uart1 transmission
appendix 7736 group users manual 20-4 fig. 2 memory allocation of m37736mhbxxxgp, m37736ehbxxxgp, m37736ehbgs, m37736mhlxxxhp, m37736ehlxxxhp (2) appendix 1. memory allocation of 7736 group 00ffff 16 010000 16 uart1 transmission 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 001000 16 000000 16 00007f 16 000080 16 00087f 16 00ffff 16 010000 16 ffffff 16 000000 16 reset 00007f 16 00ffd6 16 00fffe 16 a-d/uart2 trans./rece. 020000 16 008000 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 60 kbytes bank 2 16 (29.9 kbytes) uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide interrupt vector table sfr area internal ram area 2048 bytes peripheral device control registers (sfr) : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode ?memory allocation selection bits (b2, b1, b0)=(0, 1, 0) ?rom size: 60 kbytes ?ram size: 2048 bytes ?memory allocation selection bits (b2, b1, b0)=(1, 0, 0) ?rom size: 32 kbytes ?ram size: 2048 bytes (1.9 kbytes) uart0 transmission refer to appendix 2. 02ffff 16 notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: banks 10 16 to ff 16 cannot be accessed in the 7735 group and in external bus mode b of the 7736 group. internal rom area 32 kbytes
appendix 7736 group users manual 20-5 fig. 3 memory allocation of m37736mhbxxxgp, m37736ehbxxxgp, m37736ehbgs, m37736mhlxxxhp, m37736ehlxxxhp (3) 00ffff 16 010000 16 020000 16 uart1 transmission 01ffff 16 ff0000 16 000000 16 00007f 16 000080 16 00087f 16 ffffff 16 00c000 16 000000 16 00007f 16 000080 16 000fff 16 00ffff 16 010000 16 ffffff 16 000000 16 reset 00007f 16 00ffd6 16 00fffe 16 a-d/uart2 trans./rece. 008000 16 sfr area internal ram area 2048 bytes bank 0 16 bank 1 16 bank ff 16 internal rom area 16 kbytes bank 2 16 (28 kbytes) uart1 reception uart0 reception timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 int 0 watchdog timer dbc brk instruction zero divide interrupt vector table sfr area internal ram area 3968 bytes peripheral device control registers (sfr) : unused area in the single-chip mode external memory area in the memory expansion or microprocessor mode ?memory allocation selection bits (b2, b1, b0)=(1, 0, 1) ?rom size: 16 kbytes ?ram size: 2048 bytes ?memory allocation selection bits (b2, b1, b0)=(1, 1, 0) ?rom size: 96 kbytes ?ram size: 3968 bytes (45.9 kbytes) uart0 transmission refer to appendix 2. 02ffff 16 notes 1: access to internal rom area is disabled in the microprocessor mode. (refer to section ?.5 processor modes. ) 2: banks 10 16 to ff 16 cannot be accessed in the 7735 group and in external bus mode b of the 7736 group. internal rom area 32 kbytes 001000 16 internal rom area 64 kbytes 01ffff 16 appendix 1. memory allocation of 7736 group
appendix 7736 group user s manual 20-6 appendix 2. memory allocation in sfr area appendix 2. memory allocation in sfr area concerning section appendix 2. memory allocation in sfr area, the 7736 group differs from the 7733 group in the following: ? address 6f 16 (refer to figure 8.) the other description is the same as that of the 7733 group. therefore, refer to part 1: ? appendix 2. memory allocation in sfr area (page 21-6 in part 1)
appendix 7736 group user s manual 20-7 appendix 2. memory allocation in sfr area fig. 8 memory allocation in sfr area (4) ? 0 ro uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address oscillation circuit control register 0 serial transmit control register a-d / uart 2 trans./rece. interrupt control register uart0 transmission interrupt control register uart1 transmission interrupt control register int 2 /key input interrupt control register watchdog timer frequency selection flag register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw( h 2) rw rw rw rw b7 b0 rw rw rw rw rw rw rw rw rw rw state immediately after reset ? ? ? ? 0 00 0 ? 0 ? ( h 1) b7 b0 ? 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 port function control register uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register rw rw wo rw rw rw 00 0 0 0 1 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 ? ? ? 00 0 0 0 0 00 0 0 0 0 a value of fff 16 is set to the watchdog timer. (refer to chapter 10. watchdog timer in part 1. ) for access characteristics at address 6c 16 , also refer to figure 14.3.2 in part 1. do not wirte to the reserved area. n internal ram area (m37736mhbxxxgp: addresses 80 16 to fff 16 ) at hardware reset (not including the case where the stop or wait mode is te rminated)...undefined. at software reset...retains the state immediately before res et . when the stop or wait mode is terminated (when the hardware reset is used)...retains the state imm ediately before the stp or wit instruction is executed. ? rw 1 00 0 h 1 h 2 h 3 (reserved area) ( h 3 ) memory allocation control register uart 2 transmit/receive mode register uart 2 baud rate register (brg2) uart 2 transmission buffer register uart 2 transmit/receive control register 0 uart 2 transmit/receive control register 1 uart 2 receive buffer register oscillation circuit control register 1 rw 0 ? 0 00 0 rw ? 00 0 0 0 0 0 wo wo wo rw ro 1 00 0 rw ro ro 00 0 0 00 1 0 ro 00 0 00 0 ? rw ? ? 0 00 0 0 00 0 0 0 0 rw
appendix 7736 group user s manual 20-8 appendix 3. control registers appendix 3. control registers concerning section appendix 3. control registers, the 7736 group differs from the 7733 group in the following: ? port pi register ? port pi direction register ? port function control register ? oscillation circuit control register 1 the other control registers are the same as those of the 773 3 group. therefore, for the other control registers, refer to part 1: ? appendix 3. control registers (page 21-10 in part 1)
appendix 7736 group user s manual 20-9 appendix 3. control registers port pi register port pi direction register bit bit name functions 0: input mode (the port functions as an input port.) 1: output mode (the port functions as an output port.) port pi direction register (i = 0 to 8 and 10) (addresses 4 16 ,5 16 ,8 16 ,9 16 ,c 16 ,d 16 ,10 16 ,11 16 ,14 16 ,18 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw note: writing to bits 4 to 7 of the port p3 direction register is invalid and these bits are fixed to 0 when they are read. 0 port pi 0 direction selection bit 0 rw 1 port pi 1 direction selection bit 0 rw 2 port pi 2 direction selection bit 0 rw 3 port pi 3 direction selection bit 0 rw 4 port pi 4 direction selection bit 0 rw 5 port pi 5 direction selection bit 0 rw 6 port pi 6 direction selection bit 0 rw 7 port pi 7 direction selection bit 0 rw pi 7 b1 b2 b3 b4 b5 b6 b7 bit corresponding pin pi 6 pi 5 pi 4 pi 3 pi 2 pi 1 pi 0 b0 data is input from or output to a pin by reading/writing from /to the corresponding bit. port pi register (i = 0 to 10) (addresses 2 16 ,3 16 ,6 16 ,7 16 ,a 16 ,b 16 ,e 16 ,f 16 ,12 16 ,13 16 ,16 16 ) b1 b0 b2 b3 b4 b5 b6 b7 notes 1: writing to bits 4 to 7 of the port p3 register is invalid an d these bits are fixed to 0 when they are read. 2: after reset, be sure to write data to the port p9 register. 0: l level 1: h level 7 port pi 7 s pin undefined rw bit bit name functions at reset rw 0 port pi 0 s pin rw undefined 1 port pi 1 s pin rw undefined 2 port pi 2 s pin rw undefined 3 port pi 3 s pin rw undefined 4 port pi 4 s pin rw undefined 5 port pi 5 s pin rw undefined 6 port pi 6 s pin rw undefined
appendix 7736 group user s manual 20-10 appendix 3. control registers port function control register bit functions b7 b6 b5 b4 b3 b2 b1 b0 port function control register (address 6d 16 ) bit name 0: pins p0 to p3 are used for the external bus output. 1: pins p0 to p3 are used for the port output. 0 standby state selection bit 1 sub-clock output selection bit/ timer b2 clock source selection bit 0: no internal connection 1: internal connection with timer b2 2 timer b1 internal connect selection bit 3 port p6 pull-up selection bit 0 0: no pull-up for pins p10 4 / ki 0 to p10 7 / ki 3 1: with pull-up for pins p10 4 / ki 0 to p10 7 / ki 3 6 port p10 pull-up selection bit 7 key input interrupt selection bit 0: int 2 interrupt 1: key input interrupt 5 port p6 pull-up selection bit 1 4 must be fixed to 0. at reset rw rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 0 ? port-x c selection bit ] = 0 (when the sub clock is not used) timer b2 (event counter mode) clock source selection (note 1) 0: tb2 in input (event counter mode) 1: main clock divided by 32 (clock timer) ? port-x c selection bit = 1 (when the sub clock is used) sub-clock output selection 0: pin p6 7 /tb2 in / f sub functions as a programmable i/o port. 1: sub clock f sub is output from pin p6 7 /tb2 in / f sub . (note 2) notes 1: when the port-xc selection bit = 0 and timer b2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is inval id. 2: when timer b1 operates in the event counter mode, bit 2 is valid. ? key input interrupt selection bit = 0 0: no pull-up for pin p6 4 /int 2 1: with pull-up for pin p6 4 /int 2 ? key input interrupt selection bit = 1 0: pin p6 4 /int 2 is a port with no pull-up. 1: pin p6 4 /int 2 is an input pin with pull-up and is used for the key input interrupt. 0: no pull-up for pins p6 2 /int 0 and p6 3 /int 1 1: with pull-up for pins p6 2 /int 0 and p6 3 /int 1 port-xc selection bit ] : bit 4 of the oscillation circuit control register 0 (addr ess 6c 16 )
appendix 7736 group user s manual 20-11 appendix 3. control registers oscillation circuit control register 1 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 main clock division selection bit sub clock external input selection bit must be fixed to 0 (note 2). clock prescaler reset bit 0 0 0 0 undefined 0 oscillation circuit control register 1 (address 6f 16 ) 0: sub-clock oscillati on circuit is operating by itself. pin p7 6 functions as pin x cout . watchdog timer is u sed when terminating stop mode. 1: sub clock is input fro m the external. pin p7 6 functions as a programmable i/o port. watchdog timer is n ot used when terminating stop mode. rw rw rw rw wo not implemented. not implemented. b1 b0 b2 b3 b4 b5 b6 b7 notes 1: when writing to this register, follow the procedure shown in figure 10.2.3. by writing 1 to this bit, clock prescaler is initialized. rw 1 0 undefined main clock external input selection bit 0: main clock is divided by 2. 1: main clock is not divided by 2. 0: main-clock oscillation circuit is operating by itself. watchdog timer is used when terminating stop mode. 1: main clock is input from the external. watchdog timer is not used when terminating stop mode. this bit is ignored. 2: the case where data 01010101 2 is written with the procedure shown in figure 10.2.3 is not included. (note 1) (note 1) (note 1) write data 01011101 2 . ( ldm instruction) ? when writing to bits 0 to 3 write data 00000xxx 2 . ( ldm instruction) next instruction (b2 to b0 in figure 10.2.2) write data 80 16 . ( ldm instruction) ? when performing clock prescaler reset x
appendix 7736 group user s manual 20-12 appendix 4. package outlines appendix 4. package outlines
appendix 7736 group user s manual 20-13 appendix 4. package outlines
appendix 7. examples of handling unused pins appendix 7736 group user s manual 20 C 14 appendix 7. examples of handling unused pins the following are examples of handling unused pins. these are, however, just examples. in actual use, make the necessary adaptations and properly evaluate performance according to the user s application. 1. in single-chip mode table 1 examples of handling unused pins in single-chip mode handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins open aft er they are set to the output mode ( note 1 ). leave these pins open after writing data to the port p9 regi ster ( note 3 ). leave this pin open. connect this pin to pin vcc. connect these pins to pin vss. connect this pin to pin vcc or vss. pins p0 C p8, p10 p9 _ ____ e , rde evl0, evl1 x out ( note 2 ) avcc avss, v ref , byte bsel notes 1: when leaving these pins open after they are set to the outpu t mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these ports function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. for unused pins, use the shortest possible wiring (within 20 mm from the microcomputer s pins). 2: this is applied when an external clock is input to pin x in . 3: when leaving port p9 pins open after writing data to the por t p9 register, note the following: these pins are in a floating state from reset until the data is wr itten to the port p9 register by software. therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. fig. 9 examples of handling unused pins in single-chip mode p0 C p8 , p10 av ss v ref byte bsel m37736mhbxxxgp v ss av cc e/rde x out evl0 evl1 left open n when setting ports to input mode v cc p0 C p10 av ss v ref byte bsel m37736mhbxxxgp v ss av cc e/rde x out evl0 evl1 left open n when setting ports to output mode left open v cc p9
appendix appendix 7. examples of handling unused pins 7736 group user s manual 20 C 15 2. in memory expansion mode (external bus mode a) table 2 examples of handling unused pins in memory expansion mode (external bus mode a) pins p4 2 C p4 7 , p5 C p8, p10 ( note 7 ) p9 _____ bhe ( note 3 ), ale ( note 4 ), hlda x out ( note 6 ) _____ ____ hold , rdy avcc avss, v ref evl0, evl1 handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open after writing data to the port p9 regi ster ( note 8 ). leave these pins open. ( note 5 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. leave these pins open. notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be en hanced when the contents of the above ports direction registers are set periodically. this is bec ause these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 20 mm from the microcomputer s pins). 3: this is applied when h level is input to pin byte. 4: this is applied when h level is input to pin byte and the accessible area has a capacity of 64 kbytes. 5: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory exp ansion mode by software. therefore, a voltage level of this pin is undefined and the power sourc e current may increase while this pin functions as an input port. 6: this is applied when an external clock is input to pin x in . 7: set pin p4 2 / f 1 as pin p4 2 . (clock f 1 output is disabled.) and then, for this pin, do the same handling as that for pins p4 3 to p4 7 , p5 to p8 and p10. 8: when leaving port p9 pins open after writing data to the po rt p9 register, note the following: these pins are in a floating state from reset until the data is wr itten to the port p9 register by software. therefore, voltage levels of these pins are undefined and th e power source current may increase while they are in a floating state. fig. 10 examples of handling unused pins in memory expansion mode (external bus mode a) p4 2 C p4 7 , p5 C p8, p10 av ss v ref hold rdy left open m37736mhbxxxgp v cc v ss av cc x out evl0 evl1 n when setting ports to input mode bhe ale hlda left open p4 2 C p4 7 , p5 C p10 av ss v ref hold rdy left open v ss av cc x out evl0 evl1 n when setting ports to output mode bhe ale hlda left open left open v cc m37736mhbxxxgp p9
appendix 7. examples of handling unused pins appendix 7736 group user s manual 20 C 16 3. in memory expansion mode (external bus mode b) table 3 examples of handling unused pins in memory expansion mode (external bus mode b) pins p4 2 C p4 7 , p5 C p8, p10 ( note 5 ) p9 ____ ____ ____ whe , whl , rde , _____ ___ ___ _____ hlda , cs 0 C cs 4 , rsmp x out ( note 4 ) _____ ____ hold , rdy avcc avss, v ref evl0, evl1 handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open after writing data to the port p9 regi ster ( note 6 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. leave these pins open. fig. 11 examples of handling unused pins in memory expansion mode (external bus mode b) notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be en hanced when the contents of the above ports direction registers are set periodically. this is bec ause these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputer s pins). 3: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory exp ansion mode by software. therefore, a voltage level of this pin is undefined and the power sourc e current may increase while this pin functions as an input port. 4: this is applied when an external clock is input to pin x in . 5: set pin p4 2 / f 1 as pin p4 2 . (clock f 1 output is disabled.) and then, for this pin, do the same handling as that for pins p4 3 to p4 7 , p5 to p8 and p10. 6: when leaving port p9 pins open after writing data to the po rt p9 register, note the following: these pins are in a floating state from reset until the data is wr itten to the port p9 register by software. therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. p4 2 C p4 7 , p5 C p8, p10 av ss v ref hold rdy left open m37736mhbxxxgp v cc v ss av cc x out cs 0 C cs 4 evl0 evl1 n when setting ports to input mode weh wel rde hlda rsmp left open p4 2 C p4 7 , p5 C p10 av ss v ref hold rdy left open v ss av cc x out cs 0 C cs 4 evl0 evl1 n when setting ports to output mode weh wel rde hlda rsmp left open left open v cc m37736mhbxxxgp p9
appendix appendix 7. examples of handling unused pins 7736 group user s manual 20 C 17 4. in microprocessor mode (external bus mode a) table 4 examples of handling unused pins in microprocessor m ode (external bus mode a) handling example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open after writing data to the port p9 regi ster ( note 7 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. leave these pins open. notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputer s pins). 3: this is applied when h level is input to pin byte. 4: this is applied when h level is input to pin byte and the accessible area has a capacity of 64 kbytes. 5: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the microproce ssor mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. 6: this is applied when an external clock is input to pin x in . 7: when leaving port p9 pins open after writing data to the po rt p9 register, note the following: these pins are in a floating state from reset until the data is written to the port p9 register by software. therefore, voltage levels of these pins are undefined and th e power source current may increase while they are in a floating state. fig. 12 examples of handling unused pins in microprocessor m ode (external bus mode a) pins p4 3 C p4 7 , p5 C p8, p10 p9 _____ bhe ( note 3 ), ale ( note 4 ), hlda , f 1 x out ( note 6 ) _____ ____ hold , rdy av cc av ss , v ref evl0, evl1 p4 3 C p4 7 , p5 C p8, p10 f 1 av ss v ref hold rdy left open m37736mhbxxxgp v cc v ss av cc x out evl0 evl1 n when setting ports to input mode bhe ale hlda left open p4 3 C p4 7 , p5 C p10 f 1 av ss v ref hold rdy left open v ss av cc x out evl0 evl1 n when setting ports to output mode bhe ale hlda left open left open v cc m37736mhbxxxgp p9
appendix 7. examples of handling unused pins appendix 7736 group user s manual 20 C 18 pins p4 3 C p4 7 , p5 C p8, p10 p9 ____ ____ ____ whe , whl , rde , _____ _____ hlda , f 1 , cs 0 C cs 4 , rsmp x out ( note 4 ) _____ ____ hold , rdy av cc av ss , v ref evl0, evl1 5. in microprocessor mode (external bus mode b) table 5 examples of handling unused pins in microprocessor m ode (external bus mode b) processing example connect these pins to pin vcc or vss via resistors after the se pins are set to the input mode, or leave these pins after th ey are set to the output mode ( notes 1 and 2 ). leave these pins open after writing data to the port p9 regi ster ( note 5 ). leave these pins open. ( note 3 ) leave this pin open. connect these pins to pin vcc via resistors after these pins are set to the input mode. (these pins are pulled high.) ( note 2 ) connect this pin to pin vcc. connect these pins to pin vss. leave these pins open. fig. 13 examples of handling unused pins in microprocessor m ode (external bus mode b) notes 1: when leaving these pins open after they are set to the outp ut mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. software reliability can be enhanced when the contents of th e above ports direction registers are set periodically. this is because these contents may be chan ged by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputer s pins). 3: when vss level is applied to pin cnvss, note the following: these pins function as input ports from reset until the processor mode is switched to the microproce ssor mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. 4: this is applied when an external clock is input to pin x in . 5: when leaving port p9 pins open after writing data to the po rt p9 register, note the following: these pins are in a floating state from reset until the data is wr itten to the port p9 register by software. therefore, voltage levels of these pins are undefined and th e power source current may increase while they are in a floating state. p4 3 C p4 7 , p5 C p8, p10 f 1 rsmp av ss v ref hold rdy left open m37736mhbxxxgp v cc v ss av cc x out cs 0 C cs 4 evl0 evl1 n when setting ports to input mode weh wel rde hlda left open p4 3 C p4 7 , p5 C p10 f 1 rsmp av ss v ref hold rdy left open v ss av cc x out cs 0 C cs 4 evl0 evl1 n when setting ports to output mode weh wel rde hlda left open left open v cc m37736mhbxxxgp p9
glossary this section briefly explains the terms used in this users manual. note that the terms defined here are applied to this manual only.
7733/7735/7736 group users manual term meaning relevant term verb noun noun noun verb noun verb/ noun noun verb/ noun noun noun noun noun noun noun verb noun noun noun noun noun noun noun noun noun access access count up/countup count down /countdown internal area prefetch external area scan output stop mode /wait mode msb first lsb first means one of the following: reading out, writing to, and both of them. an accessible memory area. its capacity is one of the following; a maximum of 16 mbytes (for the 7733 group or external bus mode a of the 7736 group) and a maximum of 1 mbytes (for the 7735 group or external bus mode b of the 7736 group). indicates whether accessible or not. means moving the programs execution point (in other words, address) to another location regardless of con- ditions. __ ____ ____ ____ ____ a generic name for ale, e , rde , wel , weh , rdy , _____ _____ _____ hold , hlda , byte, and rsmp signals means decrementing by 1 and counting. a signal which is counted by timers a, b, brg, and the watchdog timer. it is f 2 , f 16 , f 64 , or f 512 , which is selected by the count source selection bits, etc. means incrementing by 1 and counting. a value which can be read out when the timer ai (bi) register is read out. note that, at the reload timing, it is the reloaded value (n), and not ffff 16 or 0000 16 . chip select signal (for the 7735 group or external bus mode b of the 7736 group) timer which correctly counts the number of external pulses without using a divider an accessible area for external devices. it has a capacity of 1 mbytes. a generic name for the external address bus and the external data bus a device connected externally to the microcomputer. a generic name for a memory, an i/o, and a periph- eral ic. means taking an op-code and operand from an instruction queue buffer into the cpu. a function which allows the user to control the count source input of a timer an accessible internal area. a generic name for areas of the internal ram, inter- nal rom, and sfr. a routine which is automatically executed when an interrupt request is accepted. set the start address of this routine into the interrupt vector table. an interrupt which is generated by a key input switches which are arranged in lattice-like form a function which terminates the stop or the wait mode by using the key input a kind of data transfer format of serial i/o. it means transferring lsb (in other words, the least significant bit) first. a clock which is input from pin x in a kind of data transfer format of serial i/o. it means transferring msb (in other words, the most significant bit) first. access accessible area access characteristics branch bus control signal count down /countdown count source count up/countup counter contents(value) ___ cs event counter external area external bus external device fetch gate function (of timer) internal area interrupt routine key input interrupt key matrix key-on wakeup lsb first main clock msb first
7733/7735/7736 group users manual term meaning relevant term underflow countup/count up stop mode wait mode fetch pull-up pull-down scan output return input key matrix bus control signal wait mode main clock internal clock f clock synchronous serial i/o overflow count down/countdown stop mode overflow power saving prefetch pull-down pull-up read-modify-write instruction return input scan output signal required for accessing external device stop mode sub clock synchronizing clock system clock uart underflow wait mode noun noun verb noun noun noun noun noun noun noun noun noun noun noun noun noun a state where the result obtained by the countup is greater than the counter resolution means saving the power consumption by using the stop or wait mode, etc. means taking an op-code and operand from a memory into an instruction queue buffer. means connecting with vss line for stabilizing its i/o level. means connecting with vcc line for stabilizing its i/o level. an instruction which reads the contents of sfr and ram, modifies them, and writes them back to the same addresses. they are the asl , clb , dec , inc , lsr , rol , ror , and seb instructions input signal from the key matrix to the microcomputer. it is used to detect a key input output signal from the microcomputer to the key matrix. it is used to detect a key input. a generic name for a bus control signal, an address bus signal, a data bus signal, and a chip select signal. (note that the chip select signal is only for the 7735 group or external bus mode b of the 7736 group.) a state where all of the oscillation circuits stop oper- ating and the program execution is stopped. by ex- ecuting the stp instruction, the microcomputer enters the stop mode. a clock which is input from pin x cin a transfer clock for the clock synchronous serial i/o one of the following: the main clock, which is input from pin x in or the sub clock, which is input from pin x cin note: in the microcomputers other than the 7733/7735/ 7736 group, definition of system clock may be different. clock asynchronous serial i/o. when it is used as the name of a functional block, this term also means the serial i/o which can be switched to the clock synchronous serial i/o. a state where the result obtained by the countdown is greater than the counter resolution a state where one or more oscillation circuits are op- erating (in other words, they are oscillating), however, the program execution is stopped. by executing the wit instruction, the microcomputer enters the wait mode.
rev. rev. no. date 1.00 first edition 970425 2.00 the following are revised. 980731 revision description list 7733/7735/7736 group users manual (1) revision description page part 1 p2-8 (2) bit 1: zero flag (z) part 1 p2-19 fig. 2.4.1 part 1 p21-30 part 1 p2-21 fig. 2.4.3 part 1 p21-3 fig. 2 part 2 p21-4 fig. 2 part 3 p20-4 fig. 2 part 1 p6-47 line 23 previous version this flag is ignored for an addition instruction in the decimal mode (the adc instruction). notes 1: ????? 2: when changing these bits, this change must be performed in an area which is internal rom area before and after this change, for example addresses 008000 16 to 00ffff 16 . also, when changing these bits, be sure to follow the procedure listed below. 3: in the m37733s4bfp, m37733s4lhp, m37735s4bfp, or m37735s4lhp, writ- ing to address 63 16 is disabled. omitted. revised version this flag is ignored for an addition and subtrac- tion instructions (the adc and the sbc instructions) in the decimal mode. notes 1: ????? 2: when changing these bits, this change must be performed in an area which is internal rom area before and after this change, for example addresses 00c000 16 to 00ffff 16 . also, when changing these bits, be sure to follow the procedure listed below. 3: this figure is applied only to the h37733mhbxxxfp. for the other mi- crocomputers, please refer to the latest datasheets on the english document cd- rom or our web site. refer to pages 2 and 3. f u n c t i o n s 0 0 0 : 1 2 4 k ( 0 0 1 0 0 0 1 6 ` 0 1 f f f f 1 6 ) 0 0 1 : 1 2 0 k ( 0 0 2 0 0 0 1 6 ` 0 1 f f f f 1 6 ) 0 1 0 : d o n o t s e l e c t . 0 1 1 : d o n o t s e l e c t . 1 0 0 : d o n o t s e l e c t . 1 0 1 : d o n o t s e l e c t . 1 1 0 : 9 6 k ( 0 0 8 0 0 0 1 6 ` 0 1 f f f f 1 6 ) 1 1 1 : 3 2 k ( 0 0 8 0 0 0 1 6 ` 0 0 f f f f 1 6 ) b 2 b 1 b 0 r o m s i z e ( a d d r e s s e s ) f u n c t i o n s 0 0 0 : 1 2 4 k b y t e s , 3 9 6 8 b y t e s 0 0 1 : 1 2 0 k b y t e s , 3 9 6 8 b y t e s 0 1 0 : 6 0 k b y t e s , 2 0 4 8 b y t e s 0 1 1 : d o n o t s e l e c t . 1 0 0 : 3 2 k b y t e s , 2 0 4 8 b y t e s 1 0 1 : 1 6 k b y t e s , 2 0 4 8 b y t e s 1 1 0 : 9 6 k b y t e s , 3 9 6 8 b y t e s 1 1 1 : d o n o t s e l e c t . b 2 b 1 b 0 r o m s i z e r a m s i z e 2: when the counter operates as an 8-bit pulse width modulator, after a trigger occurs, pin taiout outputs l level of which width is the same as the pwm pulses h level width which was set. and then, pin taiout starts the pwm pulse output. 2: when the counter operates as an 8-bit pulse width modulator, pin taiout outputs l level of which width is the same as the pwm pulses h level width which was set. and then, pin taiout starts the pwm pulse output.
i n t e r n a l r a m a r e a 2 0 4 8 b y t e s n o t e s 1 : a c c e s s t o i n t e r n a l r o m a r e a i s d i s a b l e d i n t h e m i c r o p r o c e s s o r m o d e . ( r e f e r t o s e c t i o n 2 . 5 p r o c e s s o r m o d e s . ) 2 : b a n k s 1 0 1 6 t o f f 1 6 c a n n o t b e a c c e s s e d i n t h e 7 7 3 5 g r o u p a n d i n e x t e r n a l b u s m o d e b o f t h e 7 7 3 6 g r o u p . : u n u s e d a r e a i n t h e s i n g l e - c h i p m o d e e x t e r n a l m e m o r y a r e a i n t h e m e m o r y e x p a n s i o n o r m i c r o p r o c e s s o r m o d e 0 0 0 0 7 f 1 6 0 0 0 0 0 0 1 6 f f 0 0 0 0 1 6 0 2 f f f f 1 6 i n t e r n a l r o m a r e a 6 0 k b y t e s s f r a r e a i n t 0 d b c w a t c h d o g t i m e r i n t 1 i n t 2 / k e y i n p u t t i m e r a 0 t i m e r a 1 t i m e r a 2 t i m e r a 3 t i m e r a 4 t i m e r b 0 t i m e r b 1 t i m e r b 2 u a r t 0 r e c e p t i o n u a r t 0 t r a n s m i s s i o n u a r t 1 r e c e p t i o n u a r t 1 t r a n s m i s s i o n r e s e t z e r o d i v i d e b r k i n s t r u c t i o n i n t e r r u p t v e c t o r t a b l e 0 0 f f d 6 1 6 a - d / u a r t 2 t r a n s . / r e c e . 0 0 0 0 8 0 1 6 0 0 0 8 7 f 1 6 0 0 1 0 0 0 1 6 f f f f f f 1 6 i n t e r n a l r a m a r e a 2 0 4 8 b y t e s 0 0 f f f f 1 6 0 1 0 0 0 0 1 6 0 1 f f f f 1 6 0 2 0 0 0 0 1 6 ( 1 . 9 k b y t e s ) 0 0 0 0 7 f 1 6 0 0 0 0 0 0 1 6 i n t e r n a l r o m a r e a 3 2 k b y t e s s f r a r e a 0 0 0 0 8 0 1 6 0 0 0 8 7 f 1 6 0 0 8 0 0 0 1 6 f f f f f f 1 6 0 0 f f f f 1 6 0 1 0 0 0 0 1 6 ( 2 9 . 9 k b y t e s ) ? m e m o r y a l l o c a t i o n s e l e c t i o n b i t s ( b 2 , b 1 , b 0 ) = ( 0 , 1 , 0 ) ? r o m s i z e : 6 0 k b y t e s ? r a m s i z e : 2 0 4 8 b y t e s 0 0 0 0 0 0 1 6 p e r i p h e r a l d e v i c e c o n t r o l r e g i s t e r s ( s f r ) r e f e r t o a p p e n d i x 2 . 0 0 0 0 7 f 1 6 b a n k 0 1 6 b a n k 1 1 6 b a n k 2 1 6 b a n k f f 1 6 0 0 f f f e 1 6 ? m e m o r y a l l o c a t i o n s e l e c t i o n b i t s ( b 2 , b 1 , b 0 ) = ( 1 , 0 , 0 ) ? r o m s i z e : 3 2 k b y t e s ? r a m s i z e : 2 0 4 8 b y t e s (2) revision description list 7733/7735/7736 group users manual revised version
(3) m 7 7 0 0 - 8 1 - 9 8 0 1 1 9 9 8 n 11 6 ? 0 0 0 0 7 f 1 6 0 0 0 0 0 0 1 6 f f 0 0 0 0 1 6 0 2 f f f f 1 6 0 0 f f d 6 1 6 0 0 0 0 8 0 1 6 0 0 0 8 7 f 1 6 0 0 c 0 0 0 1 6 f f f f f f 1 6 0 0 f f f f 1 6 0 1 0 0 0 0 1 6 0 1 f f f f 1 6 0 2 0 0 0 0 1 6 0 0 0 0 7 f 1 6 0 0 0 0 0 0 1 6 0 0 0 0 8 0 1 6 0 0 8 0 0 0 1 6 f f f f f f 1 6 0 0 f f f f 1 6 0 1 0 0 0 0 1 6 0 0 0 0 0 0 1 6 0 0 0 0 7 f 1 6 b a n k 0 1 6 b a n k 1 1 6 b a n k 2 1 6 b a n k f f 1 6 0 0 f f f e 1 6 0 1 f f f f 1 6 0 0 0 f f f 1 6 0 0 1 0 0 0 1 6 ? m e m o r y a l l o c a t i o n s e l e c t i o n b i t s ( b 2 , b 1 , b 0 ) = ( 1 , 0 , 1 ) ? r o m s i z e : 1 6 k b y t e s ? r a m s i z e : 2 0 4 8 b y t e s ? m e m o r y a l l o c a t i o n s e l e c t i o n b i t s ( b 2 , b 1 , b 0 ) = ( 1 , 1 , 0 ) ? r o m s i z e : 9 6 k b y t e s ? r a m s i z e : 3 9 6 8 b y t e s i n t e r n a l r a m a r e a 3 9 6 8 b y t e s i n t e r n a l r o m a r e a 1 6 k b y t e s s f r a r e a i n t e r n a l r a m a r e a 2 0 4 8 b y t e s ( 4 5 . 9 k b y t e s ) i n t e r n a l r o m a r e a 3 2 k b y t e s s f r a r e a ( 2 8 k b y t e s ) i n t e r n a l r o m a r e a 6 4 k b y t e s p e r i p h e r a l d e v i c e c o n t r o l r e g i s t e r s ( s f r ) r e f e r t o a p p e n d i x 2 . i n t 0 d b c w a t c h d o g t i m e r i n t 1 i n t 2 / k e y i n p u t t i m e r a 0 t i m e r a 1 t i m e r a 2 t i m e r a 3 t i m e r a 4 t i m e r b 0 t i m e r b 1 t i m e r b 2 u a r t 0 r e c e p t i o n u a r t 0 t r a n s m i s s i o n u a r t 1 r e c e p t i o n u a r t 1 t r a n s m i s s i o n r e s e t z e r o d i v i d e b r k i n s t r u c t i o n i n t e r r u p t v e c t o r t a b l e a - d / u a r t 2 t r a n s . / r e c e . : u n u s e d a r e a i n t h e s i n g l e - c h i p m o d e e x t e r n a l m e m o r y a r e a i n t h e m e m o r y e x p a n s i o n o r m i c r o p r o c e s s o r m o d e n o t e s 1 : a c c e s s t o i n t e r n a l r o m a r e a i s d i s a b l e d i n t h e m i c r o p r o c e s s o r m o d e . ( r e f e r t o s e c t i o n 2 . 5 p r o c e s s o r m o d e s . ) 2 : b a n k s 1 0 1 6 t o f f 1 6 c a n n o t b e a c c e s s e d i n t h e 7 7 3 5 g r o u p a n d i n e x t e r n a l b u s m o d e b o f t h e 7 7 3 6 g r o u p . revision description list 7733/7735/7736 group users manual revised version
rev. rev. no. date 2.00 980731 (4) revision description list 7733/7735/7736 group users manual revision description page part 1 p7-31 line 7 part 1 p8-40 fig.8.3.13 part 1 p8-46 table 8.4.4 part 1 p8-59 line 2 part 1 p8-59 fig.8.4.11 part 1 p8-60 fig. 8.4.12 part 1 p8-62 line 20 part 1 p11-17 table 11.4.3 14400 f 2 52( 3f 16 ) 14490.57 53( 40 16 ) 14467.59 and then, reception is started when st is detected. 14400 f 2 52( 34 16 ) 14490.57 53( 35 16 ) 14467.59 and then, the transfer clock is generated when st is detected, and reception is started. c t s r t s i c t s i r t s i r e c e p t i o n i s s t a r t e d a t t h e f a l l i n g e d g e o f s t a r t b i t . t r a n s f e r c l o c k t h e t r a n s f e r c l o c k i s g e n e r a t e d a t t h e f a l l i n g e d g e o f s t a r t b i t , a n d r e c e p t i o n i s s t a r t e d . t r a n s f e r c l o c k i n t e r r u p t c o n d i t i o n s f o r e a c h f u n c t i o n w h i c h g e n e r a t e s i n t e r r u p t r e q u e s t w h e n c l o c k s f 2 a n d f 5 1 2 a r e s t o p p e d w h e n c l o c k s f 2 a n d f 5 1 2 a r e n o t s t o p p e d a - d c o n v e r s i o n i n t e r r u p t d i s a b l e de n a b l e d i n t e r r u p t c o n d i t i o n s f o r e a c h f u n c t i o n w h i c h g e n e r a t e s i n t e r r u p t r e q u e s t w h e n c l o c k s f 2 a n d f 5 1 2 a r e s t o p p e d w h e n c l o c k s f 2 a n d f 5 1 2 a r e n o t s t o p p e d d i s a b l e d a - d c o n v e r s i o n i n t e r r u p t e n a b l e d i n o n e - s h o t m o d e a n d s i n g l e s w e e p m o d e c t s i r t s i c l k c l k i c t s i r t s i c l k c l k i revised version previous version the timer bi overflow flag is cleared to 0 at the next count timing of the count source when a value is written to the timer bi mode register with the count start flag = 1. the timer bi overflow flag is cleared to 0 when a value is written to the timer bi mode register with the count start flag = 1. ? for the slave microcomputer whose address matches bits 6 to 0 in the receive data, terminate the sleep mode. (do not terminate the sleep mode for the other slave microcomputers.) ? for the slave microcomputer whose address matches bits 6 to 0 in the receive data, clear the sleep mode. (do not terminate the sleep mode for the other slave microcomputers.)
rev. rev. no. date 2.00 980731 (5) revision description list 7733/7735/7736 group users manual revision description page part 1 p19-4 table 19.1.3 part 1 p21-80 part 1 p21-82 line 18 a when writing data to the oscillation circuit control register 1 ? when initializing the clock prescaler write data 80 16 . ( ldm instruction) clock prescaler is reset. ? when writing to bits 0 to 2 write data 01010101 16 . ( ldm instruction) next instruction write data 0000 0xxx 16 . ( ldm instruction) bits 0 to 2 are set. a when writing data to the memory allocation control register write data 01010101 16 . ( ldm instruction) next instruction write data 0000 1xxx 16 . ( ldm instruction) bits 0 to 2 are set. a when writing data to the oscillation circuit control register 1 ? when initializing the clock prescaler write data 80 16 . ( ldm instruction) clock prescaler is reset. ? when writing to bits 0 to 2 write data 01010101 2 . ( ldm instruction) next instruction write data 0000 1xxx 2 . ( ldm instruction) (note) bits 0 to 2 are set. note: in the case of the 7735 group, write data 00000xxx 2 . a when writing data to the memory allocation control register write data 01010101 2 . ( ldm instruction) next instruction write data 0000 0xxx 2 . ( ldm instruction) bits 0 to 2 are set. ? ? ? ? ? ? ? ? ? ? revised version previous version memory allocation selection bits programmable area b2 b1 b0 0 0 0 01000 16 C1ffff 16 0 0 1 02000 16 C1ffff 16 1 1 0 08000 16 C1ffff 16 1 1 1 08000 16 C0ffff 16 memory allocation selection bits programmable area b2 b1 b0 0 0 0 01000 16 C1ffff 16 0 0 1 02000 16 C1ffff 16 0 1 0 01000 16 C0ffff 16 1 0 0 08000 16 C0ffff 16 1 0 1 0c000 16 C0ffff 16 1 1 0 08000 16 C1ffff 16 ????? addresses 00 8000 16 to 00ffff 16 . ????? addresses 00 c000 16 to 00ffff 16 .
mitsubishi semiconductors users manual 7733 group/7735 group/7736 group mar. first edition 1997 editioned by committee of editing of mitsubishi semiconductor users manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1997 mitsubishi electric corporation
users manual 7733 group 7735 group 7735 group h-ef493-a ki-9703 printed in japan (rod) ? 1997 mitsubishi electric corporation. new publication, effective mar. 1997. specifications subject to change without notice.

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